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Ip=[178.72.21.4]; Helo=[localhost.localdomain] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF00009B9C.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8P190MB1911 X-BESS-ID: 1740089058-305508-25334-16456-1 X-BESS-VER: 2019.1_20250219.2339 X-BESS-Apparent-Source-IP: 104.47.17.171 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUioBkjpK+cVKVpaW5kZAVgZQMNXMxMDE2DzF0j zR0jTNxMAoKdnC1NI4NckwxcTIODVZqTYWABAFdQ9BAAAA X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.262653 [from cloudscan19-233.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS113687 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Danylo Vodopianov Implement PHY host loopback configuration for Agilex FPGA Signed-off-by: Danylo Vodopianov --- .../link_agx_100g/nt4ga_agx_link_100g.c | 116 ++++++++++++++++++ drivers/net/ntnic/meson.build | 1 + drivers/net/ntnic/nim/i2c_nim.c | 70 +++++++++-- .../nthw/core/include/nthw_si5332_si5156.h | 6 + .../net/ntnic/nthw/core/nthw_si5332_si5156.c | 31 +++++ 5 files changed, 216 insertions(+), 8 deletions(-) create mode 100644 drivers/net/ntnic/nthw/core/nthw_si5332_si5156.c diff --git a/drivers/net/ntnic/link_mgmt/link_agx_100g/nt4ga_agx_link_100g.c b/drivers/net/ntnic/link_mgmt/link_agx_100g/nt4ga_agx_link_100g.c index f3862b7fe3..9551dfdfdc 100644 --- a/drivers/net/ntnic/link_mgmt/link_agx_100g/nt4ga_agx_link_100g.c +++ b/drivers/net/ntnic/link_mgmt/link_agx_100g/nt4ga_agx_link_100g.c @@ -19,6 +19,11 @@ typedef enum { LOOPBACK_HOST } loopback_host_t; +typedef enum { + LOOPBACK_LINE_NONE, + LOOPBACK_LINE +} loopback_line_t; + static int nt4ga_agx_link_100g_ports_init(struct adapter_info_s *p_adapter_info, nthw_fpga_t *fpga); @@ -93,6 +98,105 @@ static int phy_set_host_loopback(adapter_info_t *drv, int port, loopback_host_t return 0; } +static int phy_set_line_loopback(adapter_info_t *drv, int port, loopback_line_t loopback) +{ + nthw_phy_tile_t *p = drv->fpga_info.mp_nthw_agx.p_phy_tile; + uint32_t addr; + + switch (loopback) { + case LOOPBACK_LINE_NONE: + for (uint8_t lane = 0; lane < 4; lane++) { + uint8_t quad_lane; + + for (uint8_t fgt = 0; fgt < 4; fgt++) { + uint8_t quad_and_lane_no = + (uint8_t)nthw_phy_tile_read_xcvr(p, port, lane, 0xFFFFC); + quad_lane = quad_and_lane_no & 0x3; /* bits[1:0] */ + + if (quad_lane == lane) + break; + } + + nthw_phy_tile_write_xcvr(p, port, 0, 0x41830u + (0x8000u * quad_lane), + 0x03); + + addr = nthw_phy_tile_read_xcvr(p, 0, 0, 0x41768u + (0x8000u * quad_lane)) | + (1u << 24u); + nthw_phy_tile_write_xcvr(p, port, 0, 0x41768u + (0x8000u * quad_lane), + addr); + + addr = nthw_phy_tile_read_xcvr(p, 0, 0, 0x41414u + (0x8000u * quad_lane)) & + ~(1u << 29u); + nthw_phy_tile_write_xcvr(p, port, 0, 0x41414u + (0x8000u * quad_lane), + addr); + + addr = nthw_phy_tile_read_xcvr(p, 0, 0, 0x4141Cu + (0x8000u * quad_lane)) & + ~(1u << 30u); + nthw_phy_tile_write_xcvr(p, port, 0, 0x4141Cu + (0x8000u * quad_lane), + addr); + + addr = nthw_phy_tile_read_xcvr(p, 0, 0, 0x41418u + (0x8000u * quad_lane)) & + ~(1u << 31u); + nthw_phy_tile_write_xcvr(p, port, 0, 0x41418u + (0x8000u * quad_lane), + addr); + } + + break; + + case LOOPBACK_LINE: + for (uint8_t lane = 0; lane < 4; lane++) { + uint8_t quad_lane; + + for (uint8_t fgt = 0; fgt < 4; fgt++) { + uint8_t quad_and_lane_no = + (uint8_t)nthw_phy_tile_read_xcvr(p, port, lane, 0xFFFFC); + quad_lane = quad_and_lane_no & 0x3; /* bits[1:0] */ + + if (quad_lane == lane) + break; + } + + addr = nthw_phy_tile_read_xcvr(p, port, 0, + 0x41830u + (0x8000u * quad_lane)) & + 0u; + nthw_phy_tile_write_xcvr(p, port, 0, 0x41830u + (0x8000u * quad_lane), + addr); + + addr = nthw_phy_tile_read_xcvr(p, port, 0, + 0x41768u + (0x8000u * quad_lane)) & + ~(1u << 24u); + nthw_phy_tile_write_xcvr(p, port, 0, 0x41768u + (0x8000u * quad_lane), + addr); + + addr = nthw_phy_tile_read_xcvr(p, port, 0, + 0x41414u + (0x8000u * quad_lane)) | + (1u << 29u); + nthw_phy_tile_write_xcvr(p, port, 0, 0x41414u + (0x8000u * quad_lane), + addr); + + addr = nthw_phy_tile_read_xcvr(p, port, 0, + 0x4141Cu + (0x8000u * quad_lane)) | + (1u << 30u); + nthw_phy_tile_write_xcvr(p, port, 0, 0x4141Cu + (0x8000u * quad_lane), + addr); + + addr = nthw_phy_tile_read_xcvr(p, port, 0, + 0x41418u + (0x8000u * quad_lane)) | + (1u << 31u); + nthw_phy_tile_write_xcvr(p, port, 0, 0x41418u + (0x8000u * quad_lane), + addr); + } + + break; + + default: + NT_LOG(ERR, NTNIC, "Port %d: Unhandled loopback value (%d)", port, loopback); + return -1; + } + + return 0; +} + /* * Utility functions */ @@ -156,6 +260,12 @@ set_loopback(struct adapter_info_s *p_adapter_info, int port, uint32_t mode, uin swap_tx_rx_polarity(p_adapter_info, port, false); break; + case 2: + NT_LOG(INF, NTNIC, "%s: Applying line loopback", + p_adapter_info->mp_port_id_str[port]); + phy_set_line_loopback(p_adapter_info, port, LOOPBACK_LINE); + break; + default: switch (last_mode) { case 1: @@ -165,6 +275,12 @@ set_loopback(struct adapter_info_s *p_adapter_info, int port, uint32_t mode, uin swap_tx_rx_polarity(p_adapter_info, port, true); break; + case 2: + NT_LOG(INF, NTNIC, "%s: Removing line loopback", + p_adapter_info->mp_port_id_str[port]); + phy_set_line_loopback(p_adapter_info, port, LOOPBACK_LINE_NONE); + break; + default: /* do nothing */ break; diff --git a/drivers/net/ntnic/meson.build b/drivers/net/ntnic/meson.build index 4799ebfb8e..271115cdd3 100644 --- a/drivers/net/ntnic/meson.build +++ b/drivers/net/ntnic/meson.build @@ -56,6 +56,7 @@ sources = files( 'nthw/core/nthw_mac_pcs.c', 'nthw/core/nthw_pcie3.c', 'nthw/core/nthw_phy_tile.c', + 'nthw/core/nthw_si5332_si5156.c', 'nthw/core/nthw_rpf.c', 'nthw/core/nthw_rmc.c', 'nthw/core/nthw_sdc.c', diff --git a/drivers/net/ntnic/nim/i2c_nim.c b/drivers/net/ntnic/nim/i2c_nim.c index 7dbbdb8873..f3cca9e555 100644 --- a/drivers/net/ntnic/nim/i2c_nim.c +++ b/drivers/net/ntnic/nim/i2c_nim.c @@ -13,6 +13,12 @@ #include "qsfp_registers.h" #include "nim_defines.h" +int nim_agx_read_id(struct nim_i2c_ctx *ctx); +static void nim_agx_read(struct nim_i2c_ctx *ctx, uint8_t dev_addr, uint8_t reg_addr, + uint8_t data_len, void *p_data); +static void nim_agx_write(struct nim_i2c_ctx *ctx, uint8_t dev_addr, uint8_t reg_addr, + uint8_t data_len, void *p_data); + #define NIM_READ false #define NIM_WRITE true #define NIM_PAGE_SEL_REGISTER 127 @@ -50,17 +56,17 @@ static int nim_read_write_i2c_data(nim_i2c_ctx_p ctx, bool do_write, uint16_t li if (ctx->type == I2C_HWIIC) { return nthw_iic_write_data(&ctx->hwiic, i2c_devaddr, a_reg_addr, seq_cnt, p_data); - - } else { - return 0; } - } else if (ctx->type == I2C_HWIIC) { - return nthw_iic_read_data(&ctx->hwiic, i2c_devaddr, a_reg_addr, seq_cnt, p_data); - - } else { + nim_agx_write(ctx, i2c_addr, a_reg_addr, seq_cnt, p_data); return 0; } + + if (ctx->type == I2C_HWIIC) + return nthw_iic_read_data(&ctx->hwiic, i2c_devaddr, a_reg_addr, seq_cnt, p_data); + + nim_agx_read(ctx, i2c_addr, a_reg_addr, seq_cnt, p_data); + return 0; } /* @@ -216,7 +222,7 @@ static int i2c_nim_common_construct(nim_i2c_ctx_p ctx) res = nim_read_id(ctx); else - res = -1; + res = nim_agx_read_id(ctx); if (res) { NT_LOG(ERR, NTNIC, "Can't read NIM id."); @@ -803,3 +809,51 @@ void nim_agx_setup(struct nim_i2c_ctx *ctx, nthw_pcal6416a_t *p_io_nim, nthw_i2c ctx->hwagx.p_ca9849 = p_ca9849; ctx->hwagx.p_io_nim = p_io_nim; } + +static void nim_agx_read(struct nim_i2c_ctx *ctx, + uint8_t dev_addr, + uint8_t reg_addr, + uint8_t data_len, + void *p_data) +{ + nthw_i2cm_t *p_nt_i2cm = ctx->hwagx.p_nt_i2cm; + nthw_pca9849_t *p_ca9849 = ctx->hwagx.p_ca9849; + uint8_t *data = (uint8_t *)p_data; + + rte_spinlock_lock(&p_nt_i2cm->i2cmmutex); + nthw_pca9849_set_channel(p_ca9849, ctx->hwagx.mux_channel); + + for (uint8_t i = 0; i < data_len; i++) { + nthw_i2cm_read(p_nt_i2cm, (uint8_t)(dev_addr >> 1), (uint8_t)(reg_addr + i), data); + data++; + } + + rte_spinlock_unlock(&p_nt_i2cm->i2cmmutex); +} + +static void nim_agx_write(struct nim_i2c_ctx *ctx, + uint8_t dev_addr, + uint8_t reg_addr, + uint8_t data_len, + void *p_data) +{ + nthw_i2cm_t *p_nt_i2cm = ctx->hwagx.p_nt_i2cm; + nthw_pca9849_t *p_ca9849 = ctx->hwagx.p_ca9849; + uint8_t *data = (uint8_t *)p_data; + + rte_spinlock_lock(&p_nt_i2cm->i2cmmutex); + nthw_pca9849_set_channel(p_ca9849, ctx->hwagx.mux_channel); + + for (uint8_t i = 0; i < data_len; i++) { + nthw_i2cm_write(p_nt_i2cm, (uint8_t)(dev_addr >> 1), (uint8_t)(reg_addr + i), + *data++); + } + + rte_spinlock_unlock(&p_nt_i2cm->i2cmmutex); +} + +int nim_agx_read_id(struct nim_i2c_ctx *ctx) +{ + nim_agx_read(ctx, 0xA0, 0, sizeof(ctx->nim_id), &ctx->nim_id); + return 0; +} diff --git a/drivers/net/ntnic/nthw/core/include/nthw_si5332_si5156.h b/drivers/net/ntnic/nthw/core/include/nthw_si5332_si5156.h index fb44c62f12..968d7eb74a 100644 --- a/drivers/net/ntnic/nthw/core/include/nthw_si5332_si5156.h +++ b/drivers/net/ntnic/nthw/core/include/nthw_si5332_si5156.h @@ -6,13 +6,19 @@ #ifndef __NTHW_SI5332_SI5156_H__ #define __NTHW_SI5332_SI5156_H__ +#include "nthw_i2cm.h" /* * PCA9849 I2c mux class */ struct nthw_pca9849 { + nthw_i2cm_t *mp_nt_i2cm; + uint8_t m_current_channel; + uint8_t m_dev_address; }; typedef struct nthw_pca9849 nthw_pca9849_t; +int nthw_pca9849_set_channel(nthw_pca9849_t *p, uint8_t channel); + #endif /* __NTHW_SI5332_SI5156_H__ */ diff --git a/drivers/net/ntnic/nthw/core/nthw_si5332_si5156.c b/drivers/net/ntnic/nthw/core/nthw_si5332_si5156.c new file mode 100644 index 0000000000..b5560e2990 --- /dev/null +++ b/drivers/net/ntnic/nthw/core/nthw_si5332_si5156.c @@ -0,0 +1,31 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2023 Napatech A/S + */ + +#include +#include "nt_util.h" +#include "ntlog.h" + +#include "nthw_drv.h" +#include "nthw_register.h" + +#include "nthw_si5332_si5156.h" + +int nthw_pca9849_set_channel(nthw_pca9849_t *p, uint8_t channel) +{ + int res; + + if (p->m_current_channel != channel) { + uint8_t data = channel + 4; + res = nthw_i2cm_write(p->mp_nt_i2cm, p->m_dev_address, 0, data); + + if (res) + return res; + + p->m_current_channel = channel; + nt_os_wait_usec(10000); + } + + return 0; +} -- 2.45.0