From: Bingbin Chen <chen.bingbin@zte.com.cn>
To: stephen@networkplumber.org, wang.junlong1@zte.com.cn
Cc: dev@dpdk.org, Bingbin Chen <chen.bingbin@zte.com.cn>
Subject: [PATCH v2 06/14] net/zxdh: add eram tables ops
Date: Sat, 22 Feb 2025 15:22:24 +0800 [thread overview]
Message-ID: <20250222072232.561353-7-chen.bingbin@zte.com.cn> (raw)
In-Reply-To: <20250222072232.561353-1-chen.bingbin@zte.com.cn>
[-- Attachment #1.1.1: Type: text/plain, Size: 32161 bytes --]
Implement the eram tables read and write operations
by dtb channel.
Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn>
---
drivers/net/zxdh/zxdh_np.c | 884 ++++++++++++++++++++++++++++++-------
drivers/net/zxdh/zxdh_np.h | 15 +
2 files changed, 738 insertions(+), 161 deletions(-)
diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c
index 87975c13c3..64ce699e52 100644
--- a/drivers/net/zxdh/zxdh_np.c
+++ b/drivers/net/zxdh/zxdh_np.c
@@ -27,6 +27,10 @@ static const ZXDH_VERSION_COMPATIBLE_REG_T g_np_sdk_version = {
ZXDH_NPSDK_COMPAT_ITEM_ID, 1, 0, 0, 0, {0} };
static const uint32_t hardware_ep_id[5] = {5, 6, 7, 8, 9};
static ZXDH_RB_CFG *g_dtb_dump_addr_rb[ZXDH_DEV_CHANNEL_MAX][ZXDH_DTB_QUEUE_NUM_MAX];
+static const char * const g_dpp_dtb_name[] = {
+ "DOWN TAB",
+ "UP TAB",
+};
static ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = {
{"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
@@ -196,6 +200,81 @@ static ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = {
},
};
+static ZXDH_DTB_FIELD_T g_dtb_eram_dump_cmd_info[] = {
+ {"valid", 127, 1},
+ {"up_type", 126, 2},
+ {"base_addr", 106, 19},
+ {"tb_depth", 83, 20},
+ {"tb_dst_addr_h", 63, 32},
+ {"tb_dst_addr_l", 31, 32},
+};
+
+static ZXDH_DTB_FIELD_T g_dtb_ddr_dump_cmd_info[] = {
+ {"valid", 127, 1},
+ {"up_type", 126, 2},
+ {"base_addr", 117, 30},
+ {"tb_depth", 83, 20},
+ {"tb_dst_addr_h", 63, 32},
+ {"tb_dst_addr_l", 31, 32},
+
+};
+
+static ZXDH_DTB_FIELD_T g_dtb_zcam_dump_cmd_info[] = {
+ {"valid", 127, 1},
+ {"up_type", 126, 2},
+ {"zgroup_id", 124, 2},
+ {"zblock_id", 122, 3},
+ {"ram_reg_flag", 119, 1},
+ {"z_reg_cell_id", 118, 2},
+ {"sram_addr", 116, 9},
+ {"tb_depth", 97, 10},
+ {"tb_width", 65, 2},
+ {"tb_dst_addr_h", 63, 32},
+ {"tb_dst_addr_l", 31, 32},
+
+};
+
+static ZXDH_DTB_FIELD_T g_dtb_etcam_dump_cmd_info[] = {
+ {"valid", 127, 1},
+ {"up_type", 126, 2},
+ {"block_sel", 124, 3},
+ {"addr", 121, 9},
+ {"rd_mode", 112, 8},
+ {"data_or_mask", 104, 1},
+ {"tb_depth", 91, 10},
+ {"tb_width", 81, 2},
+ {"tb_dst_addr_h", 63, 32},
+ {"tb_dst_addr_l", 31, 32},
+
+};
+
+static ZXDH_DTB_TABLE_T g_dpp_dtb_dump_info[] = {
+ {
+ "eram",
+ ZXDH_DTB_DUMP_ERAM,
+ 6,
+ g_dtb_eram_dump_cmd_info,
+ },
+ {
+ "ddr",
+ ZXDH_DTB_DUMP_DDR,
+ 6,
+ g_dtb_ddr_dump_cmd_info,
+ },
+ {
+ "zcam",
+ ZXDH_DTB_DUMP_ZCAM,
+ 11,
+ g_dtb_zcam_dump_cmd_info,
+ },
+ {
+ "etcam",
+ ZXDH_DTB_DUMP_ETCAM,
+ 10,
+ g_dtb_etcam_dump_cmd_info,
+ },
+};
+
#define ZXDH_SDT_MGR_PTR_GET() (&g_sdt_mgr)
#define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id])
#define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id])
@@ -305,6 +384,28 @@ zxdh_np_comm_convert32(uint32_t dw_data)
(p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \
VAL)
+static inline uint64_t
+zxdh_np_dtb_tab_down_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID,
+ uint32_t INDEX)
+{
+ return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.start_phy_addr +
+ INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size;
+}
+
+#define ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \
+ zxdh_np_dtb_tab_down_phy_addr_get(DEV_ID, QUEUE_ID, INDEX)
+
+static inline uint64_t
+zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID,
+ uint32_t INDEX)
+{
+ return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.start_phy_addr +
+ INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size;
+}
+
+#define ZXDH_DTB_TAB_UP_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX) \
+ zxdh_np_dtb_tab_up_phy_addr_get(DEV_ID, QUEUE_ID, INDEX)
+
static inline void
zxdh_np_init_d_node(ZXDH_D_NODE *ptr, void *pdata)
{
@@ -3058,6 +3159,12 @@ zxdh_np_dtb_table_info_get(uint32_t table_type)
return &g_dpp_dtb_table_info[table_type];
}
+static ZXDH_DTB_TABLE_T *
+zxdh_np_dtb_dump_info_get(uint32_t up_type)
+{
+ return &g_dpp_dtb_dump_info[up_type];
+}
+
static uint32_t
zxdh_np_dtb_write_table_cmd(uint32_t dev_id,
ZXDH_DTB_TABLE_INFO_E table_type,
@@ -3092,6 +3199,39 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id,
return rc;
}
+static uint32_t
+zxdh_np_dtb_write_dump_cmd(uint32_t dev_id,
+ ZXDH_DTB_DUMP_INFO_E dump_type,
+ void *p_cmd_data,
+ void *p_cmd_buff)
+{
+ uint32_t rc = ZXDH_OK;
+ uint32_t field_cnt = 0;
+ ZXDH_DTB_TABLE_T *p_table_info;
+ ZXDH_DTB_FIELD_T *p_field_info = NULL;
+ uint32_t temp_data = 0;
+
+ p_table_info = zxdh_np_dtb_dump_info_get(dump_type);
+ ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info);
+ p_field_info = p_table_info->p_fields;
+ ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_field_info);
+
+ for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) {
+ temp_data = *((uint32_t *)p_cmd_data + field_cnt) &
+ ZXDH_COMM_GET_BIT_MASK(uint32_t, p_field_info[field_cnt].len);
+
+ rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_cmd_buff,
+ ZXDH_DTB_TABLE_CMD_SIZE_BIT,
+ temp_data,
+ p_field_info[field_cnt].lsb_pos,
+ p_field_info[field_cnt].len);
+
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_comm_write_bits");
+ }
+
+ return rc;
+}
+
static uint32_t
zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id,
uint32_t mode,
@@ -3141,6 +3281,31 @@ zxdh_np_dtb_smmu0_write_entry_data(uint32_t dev_id,
return rc;
}
+static uint32_t
+zxdh_np_dtb_smmu0_dump_info_write(uint32_t dev_id,
+ uint32_t base_addr,
+ uint32_t depth,
+ uint32_t addr_high32,
+ uint32_t addr_low32,
+ uint32_t *p_dump_info)
+{
+ uint32_t rc = ZXDH_OK;
+
+ ZXDH_DTB_ERAM_DUMP_FORM_T dtb_eram_dump_form_info = {
+ .valid = 1,
+ .up_type = ZXDH_DTB_DUMP_MODE_ERAM,
+ .base_addr = base_addr,
+ .tb_depth = depth,
+ .tb_dst_addr_h = addr_high32,
+ .tb_dst_addr_l = addr_low32,
+ };
+
+ rc = zxdh_np_dtb_write_dump_cmd(dev_id, ZXDH_DTB_DUMP_ERAM,
+ &dtb_eram_dump_form_info, p_dump_info);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_write_dump_cmd");
+
+ return rc;
+}
static uint32_t
zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id,
@@ -3219,6 +3384,65 @@ zxdh_np_eram_dtb_len_get(uint32_t mode)
return dtb_len;
}
+static void
+zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data)
+{
+ p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32;
+ p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32;
+}
+
+static uint32_t
+zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info)
+{
+ uint32_t tbl_type = 0;
+ uint32_t clutch_en = 0;
+
+ ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL;
+ ZXDH_SDT_TBL_PORT_TBL_T *p_sdt_porttbl = NULL;
+
+ ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32,
+ ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN);
+ ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1);
+
+ switch (tbl_type) {
+ case ZXDH_SDT_TBLT_ERAM:
+ p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info;
+ p_sdt_eram->table_type = tbl_type;
+ p_sdt_eram->eram_clutch_en = clutch_en;
+ break;
+ case ZXDH_SDT_TBLT_PORTTBL:
+ p_sdt_porttbl = (ZXDH_SDT_TBL_PORT_TBL_T *)p_sdt_info;
+ p_sdt_porttbl->table_type = tbl_type;
+ p_sdt_porttbl->porttbl_clutch_en = clutch_en;
+ break;
+ default:
+ PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type);
+ return 1;
+ }
+
+ return 0;
+}
+
+static uint32_t
+zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info)
+{
+ ZXDH_SDT_TBL_DATA_T sdt_tbl = {0};
+ uint32_t rc;
+
+ if (sdt_no > ZXDH_DEV_SDT_ID_MAX - 1) {
+ PMD_DRV_LOG(ERR, "SDT NO [ %d ] is invalid!", sdt_no);
+ return ZXDH_PAR_CHK_INVALID_PARA;
+ }
+
+ zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl);
+
+ rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info);
+ if (rc != 0)
+ PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error.", sdt_no);
+
+ return rc;
+}
+
static uint32_t
zxdh_np_dtb_eram_one_entry(uint32_t dev_id,
uint32_t sdt_no,
@@ -3239,6 +3463,9 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id,
ZXDH_COMM_CHECK_POINT(p_dtb_one_entry);
ZXDH_COMM_CHECK_POINT(p_dtb_len);
+ rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get");
+
peramdata = (ZXDH_DTB_ERAM_ENTRY_INFO_T *)pdata;
index = peramdata->index;
base_addr = sdt_eram.eram_base_addr;
@@ -3389,6 +3616,98 @@ zxdh_np_dtb_item_ack_wr(uint32_t dev_id,
return 0;
}
+static uint32_t
+zxdh_np_dtb_item_ack_prt(uint32_t dev_id,
+ uint32_t queue_id,
+ uint32_t dir_flag,
+ uint32_t index)
+{
+ uint32_t rc = 0;
+ uint32_t i = 0;
+ uint32_t ack_data[4] = {0};
+
+ for (i = 0; i < ZXDH_DTB_ITEM_ACK_SIZE / 4; i++) {
+ rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, dir_flag, index, i, ack_data + i);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd");
+ }
+
+ PMD_DRV_LOG(INFO, "[%s] BD INFO:", g_dpp_dtb_name[dir_flag]);
+ PMD_DRV_LOG(INFO, "[ index : %u] : 0x%08x 0x%08x 0x%08x 0x%08x", index,
+ ack_data[0], ack_data[1], ack_data[2], ack_data[3]);
+
+ return rc;
+}
+
+static uint32_t
+zxdh_np_dtb_item_buff_rd(uint32_t dev_id,
+ uint32_t queue_id,
+ uint32_t dir_flag,
+ uint32_t index,
+ uint32_t pos,
+ uint32_t len,
+ uint32_t *p_data)
+{
+ uint64_t addr = 0;
+
+ if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) {
+ PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id);
+ return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT;
+ }
+
+ if (dir_flag == ZXDH_DTB_DIR_UP_TYPE) {
+ if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, index) ==
+ ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) {
+ addr = ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(dev_id, queue_id, index) + pos * 4;
+ ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(dev_id, queue_id, index, 0);
+ } else {
+ addr = ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, index) +
+ ZXDH_DTB_ITEM_ACK_SIZE + pos * 4;
+ }
+ } else {
+ addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, index) +
+ ZXDH_DTB_ITEM_ACK_SIZE + pos * 4;
+ }
+
+ memcpy(p_data, (uint8_t *)(addr), len * 4);
+
+ zxdh_np_comm_swap((uint8_t *)p_data, len * 4);
+
+ return ZXDH_OK;
+}
+
+static uint32_t
+zxdh_np_dtb_item_buff_prt(uint32_t dev_id,
+ uint32_t queue_id,
+ uint32_t dir_flag,
+ uint32_t index,
+ uint32_t len)
+{
+ uint32_t rc = 0;
+ uint32_t i = 0;
+ uint32_t j = 0;
+ uint32_t *p_item_buff = NULL;
+
+ p_item_buff = rte_zmalloc(NULL, len * sizeof(uint32_t), 0);
+ if (p_item_buff == NULL) {
+ PMD_DRV_LOG(INFO, "Alloc dtb item buffer failed!!!");
+ return ZXDH_RC_DTB_MEMORY_ALLOC_ERR;
+ }
+
+ zxdh_np_dtb_item_buff_rd(dev_id, queue_id, dir_flag, index, 0, len, p_item_buff);
+
+ PMD_DRV_LOG(INFO, "[%s] BUFF INFO:", g_dpp_dtb_name[dir_flag]);
+ for (i = 0, j = 0; i < len; i++, j++) {
+ if (j % 4 == 0)
+ PMD_DRV_LOG(INFO, "0x%08x ", (*(p_item_buff + i)));
+ else
+ PMD_DRV_LOG(INFO, "0x%08x ", (*(p_item_buff + i)));
+ }
+
+ rte_free(p_item_buff);
+
+ return rc;
+}
+
static uint32_t
zxdh_np_dtb_queue_item_info_set(uint32_t dev_id,
uint32_t queue_id,
@@ -3521,6 +3840,122 @@ zxdh_np_dtb_write_down_table_data(uint32_t dev_id,
return rc;
}
+static void
+zxdh_np_dtb_down_table_element_addr_get(uint32_t dev_id,
+ uint32_t queue_id,
+ uint32_t element_id,
+ uint32_t *p_element_start_addr_h,
+ uint32_t *p_element_start_addr_l,
+ uint32_t *p_element_table_addr_h,
+ uint32_t *p_element_table_addr_l)
+{
+ uint32_t addr_h = 0;
+ uint32_t addr_l = 0;
+
+ addr_h = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) >> 32) & 0xffffffff;
+ addr_l = ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) & 0xffffffff;
+
+ *p_element_start_addr_h = addr_h;
+ *p_element_start_addr_l = addr_l;
+
+ addr_h = ((ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) +
+ ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff;
+ addr_l = (ZXDH_DTB_TAB_DOWN_PHY_ADDR_GET(dev_id, queue_id, element_id) +
+ ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff;
+
+ *p_element_table_addr_h = addr_h;
+ *p_element_table_addr_l = addr_l;
+}
+
+static uint32_t
+zxdh_np_dtb_down_table_element_info_prt(uint32_t dev_id,
+ uint32_t queue_id,
+ uint32_t element_id)
+{
+ uint32_t rc = 0;
+ uint32_t element_start_addr_h = 0;
+ uint32_t element_start_addr_l = 0;
+ uint32_t element_table_addr_h = 0;
+ uint32_t element_table_addr_l = 0;
+
+ zxdh_np_dtb_down_table_element_addr_get(dev_id,
+ queue_id,
+ element_id,
+ &element_start_addr_h,
+ &element_start_addr_l,
+ &element_table_addr_h,
+ &element_table_addr_l);
+
+ PMD_DRV_LOG(INFO, "queue_id %d.", queue_id);
+ PMD_DRV_LOG(INFO, "element_id %d.", element_id);
+ PMD_DRV_LOG(INFO, "element_start_addr_h 0x%x.", element_start_addr_h);
+ PMD_DRV_LOG(INFO, "element_start_addr_l 0x%x.", element_start_addr_l);
+ PMD_DRV_LOG(INFO, "element_table_addr_h 0x%x..", element_table_addr_h);
+ PMD_DRV_LOG(INFO, "element_table_addr_l 0x%x.", element_table_addr_l);
+
+ rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_prt");
+
+ rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE, element_id, 24);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt");
+
+ return rc;
+}
+
+static uint32_t
+zxdh_np_dtb_tab_down_success_status_check(uint32_t dev_id,
+ uint32_t queue_id,
+ uint32_t element_id)
+{
+ uint32_t rc = 0;
+ uint32_t rd_cnt = 0;
+ uint32_t ack_value = 0;
+ uint32_t success_flag = 0;
+
+ while (!success_flag) {
+ rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE,
+ element_id, 0, &ack_value);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd");
+
+ PMD_DRV_LOG(DEBUG, "zxdh_np_dtb_item_ack_rd ack_value:0x%08x", ack_value);
+
+ if (((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_DOWN_ACK_VLD_MASK) {
+ success_flag = 1;
+ break;
+ }
+
+ if (rd_cnt > ZXDH_DTB_DOWN_OVER_TIME) {
+ PMD_DRV_LOG(ERR, "down queue %d item %d overtime!", queue_id, element_id);
+
+ rc = zxdh_np_dtb_down_table_element_info_prt(dev_id, queue_id, element_id);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_down_table_element_info_prt");
+
+ rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE,
+ element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr");
+
+ return ZXDH_ERR;
+ }
+
+ rd_cnt++;
+ rte_delay_us(ZXDH_DTB_DELAY_TIME);
+ }
+
+ if ((ack_value & 0xff) != ZXDH_DTB_TAB_ACK_SUCCESS_MASK) {
+ rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE,
+ element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr");
+ return ack_value & 0xff;
+ }
+
+ rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_DOWN_TYPE,
+ element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr");
+
+ return rc;
+}
+
+
int
zxdh_np_dtb_table_entry_write(uint32_t dev_id,
uint32_t queue_id,
@@ -3589,17 +4024,11 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id,
&element_id);
rte_free(p_data_buff);
+ rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id);
return rc;
}
-static void
-zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data)
-{
- p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32;
- p_sdt_data->data_low32 = g_sdt_info[dev_id][sdt_no].data_low32;
-}
-
int
zxdh_np_dtb_table_entry_delete(uint32_t dev_id,
uint32_t queue_id,
@@ -3673,71 +4102,25 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id,
&element_id);
rte_free(p_data_buff);
+ rc = zxdh_np_dtb_tab_down_success_status_check(dev_id, queue_id, element_id);
+
return rc;
}
-static uint32_t
-zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info)
+static void
+zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index,
+ uint32_t *p_row_index, uint32_t *p_col_index)
{
- uint32_t tbl_type = 0;
- uint32_t clutch_en = 0;
-
- ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL;
- ZXDH_SDT_TBL_PORT_TBL_T *p_sdt_porttbl = NULL;
-
- ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32,
- ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN);
- ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1);
+ uint32_t row_index = 0;
+ uint32_t col_index = 0;
- switch (tbl_type) {
- case ZXDH_SDT_TBLT_ERAM:
- p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info;
- p_sdt_eram->table_type = tbl_type;
- p_sdt_eram->eram_clutch_en = clutch_en;
+ switch (eram_mode) {
+ case ZXDH_ERAM128_TBL_128b:
+ row_index = index;
break;
-
- case ZXDH_SDT_TBLT_PORTTBL:
- p_sdt_porttbl = (ZXDH_SDT_TBL_PORT_TBL_T *)p_sdt_info;
- p_sdt_porttbl->table_type = tbl_type;
- p_sdt_porttbl->porttbl_clutch_en = clutch_en;
- break;
- default:
- PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type);
- return 1;
- }
-
- return 0;
-}
-
-static uint32_t
-zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info)
-{
- ZXDH_SDT_TBL_DATA_T sdt_tbl = {0};
- uint32_t rc;
-
- zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl);
-
- rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info);
- if (rc != 0)
- PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error", sdt_no);
-
- return rc;
-}
-
-static void
-zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index,
- uint32_t *p_row_index, uint32_t *p_col_index)
-{
- uint32_t row_index = 0;
- uint32_t col_index = 0;
-
- switch (eram_mode) {
- case ZXDH_ERAM128_TBL_128b:
- row_index = index;
- break;
- case ZXDH_ERAM128_TBL_64b:
- row_index = (index >> 1);
- col_index = index & 0x1;
+ case ZXDH_ERAM128_TBL_64b:
+ row_index = (index >> 1);
+ col_index = index & 0x1;
break;
case ZXDH_ERAM128_TBL_1b:
row_index = (index >> 7);
@@ -3750,74 +4133,6 @@ zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index,
*p_col_index = col_index;
}
-static uint32_t
-zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no,
- ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry)
-{
- uint32_t index = p_dump_eram_entry->index;
- uint32_t *p_data = p_dump_eram_entry->p_data;
- ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0};
- uint32_t temp_data[4] = {0};
- uint32_t row_index = 0;
- uint32_t col_index = 0;
- uint32_t rd_mode;
- uint32_t rc;
-
- rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info);
- ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get");
- rd_mode = sdt_eram_info.eram_mode;
-
- zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index);
-
- switch (rd_mode) {
- case ZXDH_ERAM128_TBL_128b:
- memcpy(p_data, temp_data, (128 / 8));
- break;
- case ZXDH_ERAM128_TBL_64b:
- memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8));
- break;
- case ZXDH_ERAM128_TBL_1b:
- ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data +
- (3 - col_index / 32)), (col_index % 32), 1);
- break;
- default:
- break;
- }
- return rc;
-}
-
-int
-zxdh_np_dtb_table_entry_get(uint32_t dev_id,
- uint32_t queue_id,
- ZXDH_DTB_USER_ENTRY_T *get_entry,
- uint32_t srh_mode)
-{
- ZXDH_SDT_TBL_DATA_T sdt_tbl = {0};
- uint32_t tbl_type = 0;
- uint32_t rc;
- uint32_t sdt_no;
-
- sdt_no = get_entry->sdt_no;
- zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl);
-
- ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32,
- ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN);
- switch (tbl_type) {
- case ZXDH_SDT_TBLT_ERAM:
- rc = zxdh_np_dtb_eram_data_get(dev_id,
- queue_id,
- sdt_no,
- (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data);
- ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get");
- break;
- default:
- PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type);
- return 1;
- }
-
- return 0;
-}
-
static void
zxdh_np_stat_cfg_soft_get(uint32_t dev_id,
ZXDH_PPU_STAT_CFG_T *p_stat_cfg)
@@ -3882,6 +4197,181 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id,
return rc;
}
+static uint32_t
+zxdh_np_dtb_tab_up_data_get(uint32_t dev_id,
+ uint32_t queue_id,
+ uint32_t item_index,
+ uint32_t data_len,
+ uint32_t *p_data)
+{
+ uint32_t rc = 0;
+
+ if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) {
+ PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id);
+ return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT;
+ }
+
+ rc = zxdh_np_dtb_item_buff_rd(dev_id,
+ queue_id,
+ ZXDH_DTB_DIR_UP_TYPE,
+ item_index,
+ 0,
+ data_len,
+ p_data);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_rd");
+
+ rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE,
+ item_index, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr");
+
+ return rc;
+}
+
+static uint32_t
+zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id,
+ uint32_t queue_id,
+ uint32_t item_index,
+ uint32_t *p_phy_haddr,
+ uint32_t *p_phy_laddr)
+{
+ uint32_t rc = 0;
+ uint64_t addr;
+
+ if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) {
+ PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id);
+ return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT;
+ }
+
+ if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) ==
+ ZXDH_DTB_TAB_UP_USER_ADDR_TYPE)
+ addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index);
+ else
+ addr = ZXDH_DTB_ITEM_ACK_SIZE;
+
+ *p_phy_haddr = (addr >> 32) & 0xffffffff;
+ *p_phy_laddr = addr & 0xffffffff;
+
+ return rc;
+}
+
+static uint32_t
+zxdh_np_dtb_dump_table_element_addr_get(uint32_t dev_id,
+ uint32_t queue_id,
+ uint32_t element_id,
+ uint32_t *p_element_start_addr_h,
+ uint32_t *p_element_start_addr_l,
+ uint32_t *p_element_dump_addr_h,
+ uint32_t *p_element_dump_addr_l,
+ uint32_t *p_element_table_info_addr_h,
+ uint32_t *p_element_table_info_addr_l)
+{
+ uint32_t rc = ZXDH_OK;
+ uint32_t addr_h = 0;
+ uint32_t addr_l = 0;
+
+ addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) >> 32) & 0xffffffff;
+ addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id)) & 0xffffffff;
+
+ *p_element_start_addr_h = addr_h;
+ *p_element_start_addr_l = addr_l;
+
+ addr_h = ((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) +
+ ZXDH_DTB_ITEM_ACK_SIZE) >> 32) & 0xffffffff;
+ addr_l = (ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, element_id) +
+ ZXDH_DTB_ITEM_ACK_SIZE) & 0xffffffff;
+
+ *p_element_dump_addr_h = addr_h;
+ *p_element_dump_addr_l = addr_l;
+
+ rc = zxdh_np_dtb_tab_up_item_addr_get(dev_id, queue_id, element_id,
+ p_element_table_info_addr_h, p_element_table_info_addr_l);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_item_addr_get");
+
+ return rc;
+}
+
+static uint32_t
+zxdh_np_dtb_dump_table_element_info_prt(uint32_t dev_id,
+ uint32_t queue_id,
+ uint32_t element_id)
+{
+ uint32_t rc = 0;
+
+ uint32_t element_start_addr_h = 0;
+ uint32_t element_start_addr_l = 0;
+ uint32_t element_dump_addr_h = 0;
+ uint32_t element_dump_addr_l = 0;
+ uint32_t element_table_info_addr_h = 0;
+ uint32_t element_table_info_addr_l = 0;
+
+ zxdh_np_dtb_dump_table_element_addr_get(dev_id,
+ queue_id,
+ element_id,
+ &element_start_addr_h,
+ &element_start_addr_l,
+ &element_dump_addr_h,
+ &element_dump_addr_l,
+ &element_table_info_addr_h,
+ &element_table_info_addr_l);
+ PMD_DRV_LOG(INFO, "queue_id %d.", queue_id);
+ PMD_DRV_LOG(INFO, "element_id %d.", element_id);
+ PMD_DRV_LOG(INFO, "element_start_addr_h 0x%x.", element_start_addr_h);
+ PMD_DRV_LOG(INFO, "element_start_addr_l 0x%x.", element_start_addr_l);
+ PMD_DRV_LOG(INFO, "element_dump_addr_h 0x%x.", element_dump_addr_h);
+ PMD_DRV_LOG(INFO, "element_dump_addr_l 0x%x.", element_dump_addr_l);
+ PMD_DRV_LOG(INFO, "element_table_info_addr_h 0x%x.", element_table_info_addr_h);
+ PMD_DRV_LOG(INFO, "element_table_info_addr_l 0x%x.", element_table_info_addr_l);
+
+ rc = zxdh_np_dtb_item_ack_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt");
+
+ rc = zxdh_np_dtb_item_buff_prt(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE, element_id, 32);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_buff_prt");
+
+ return rc;
+}
+
+static uint32_t
+zxdh_np_dtb_tab_up_success_status_check(uint32_t dev_id,
+ uint32_t queue_id,
+ uint32_t element_id)
+{
+ uint32_t rc = 0;
+ uint32_t rd_cnt = 0;
+ uint32_t ack_value = 0;
+ uint32_t success_flag = 0;
+
+ while (!success_flag) {
+ rc = zxdh_np_dtb_item_ack_rd(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE,
+ element_id, 0, &ack_value);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_rd");
+
+ if ((((ack_value >> 8) & 0xffffff) == ZXDH_DTB_TAB_UP_ACK_VLD_MASK) &&
+ ((ack_value & 0xff) == ZXDH_DTB_TAB_ACK_SUCCESS_MASK)) {
+ success_flag = 1;
+ break;
+ }
+
+ if (rd_cnt > ZXDH_DTB_DUMP_OVER_TIME) {
+ PMD_DRV_LOG(ERR, "dump queue %d item %d overtime!", queue_id, element_id);
+
+ rc = zxdh_np_dtb_dump_table_element_info_prt(dev_id, queue_id, element_id);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_dump_table_element_info_prt");
+
+ rc = zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE,
+ element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_item_ack_wr");
+
+ return ZXDH_ERR;
+ }
+
+ rd_cnt++;
+ rte_delay_us(ZXDH_DTB_DELAY_TIME);
+ }
+
+ return rc;
+}
+
static uint32_t
zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id,
uint32_t queue_id,
@@ -3909,6 +4399,16 @@ zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id,
queue_element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK);
}
+ rc = zxdh_np_dtb_tab_up_success_status_check(dev_id,
+ queue_id, queue_element_id);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_success_status_check");
+
+ rc = zxdh_np_dtb_tab_up_data_get(dev_id, queue_id, queue_element_id,
+ data_len, p_dump_data);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_tab_up_data_get");
+
+ PMD_DRV_LOG(DEBUG, "queue %d element %d dump done.", queue_id, queue_element_id);
+
return rc;
}
@@ -3967,33 +4467,6 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id,
return 0;
}
-static uint32_t
-zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id,
- uint32_t queue_id,
- uint32_t item_index,
- uint32_t *p_phy_haddr,
- uint32_t *p_phy_laddr)
-{
- uint32_t rc = 0;
- uint64_t addr;
-
- if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) {
- PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id);
- return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT;
- }
-
- if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) ==
- ZXDH_DTB_TAB_UP_USER_ADDR_TYPE)
- addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index);
- else
- addr = ZXDH_DTB_ITEM_ACK_SIZE;
-
- *p_phy_haddr = (addr >> 32) & 0xffffffff;
- *p_phy_laddr = addr & 0xffffffff;
-
- return rc;
-}
-
static uint32_t
zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id,
uint32_t queue_id,
@@ -4022,6 +4495,14 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id,
&dump_dst_phy_haddr, &dump_dst_phy_laddr);
ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_tab_up_item_addr_get");
+ rc = zxdh_np_dtb_smmu0_dump_info_write(dev_id,
+ base_addr,
+ depth,
+ dump_dst_phy_haddr,
+ dump_dst_phy_laddr,
+ (uint32_t *)form_buff);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_smmu0_dump_info_write");
+
data_len = depth * 128 / 32;
desc_len = ZXDH_DTB_LEN_POS_SETP / 4;
@@ -4032,6 +4513,87 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id,
return rc;
}
+static uint32_t
+zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no,
+ ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry)
+{
+ uint32_t index = p_dump_eram_entry->index;
+ uint32_t *p_data = p_dump_eram_entry->p_data;
+ ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0};
+ uint32_t temp_data[4] = {0};
+ uint32_t row_index = 0;
+ uint32_t col_index = 0;
+ uint32_t rd_mode;
+ uint32_t rc;
+ uint32_t eram_dump_base_addr = 0;
+ uint32_t eram_base_addr = 0;
+ uint32_t element_id = 0;
+
+ rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get");
+ rd_mode = sdt_eram_info.eram_mode;
+
+ zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index);
+
+ eram_dump_base_addr = eram_base_addr + row_index;
+
+ rc = zxdh_np_dtb_se_smmu0_dma_dump(dev_id,
+ queue_id,
+ eram_dump_base_addr,
+ 1,
+ temp_data,
+ &element_id);
+ ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_dma_dump");
+
+ switch (rd_mode) {
+ case ZXDH_ERAM128_TBL_128b:
+ memcpy(p_data, temp_data, (128 / 8));
+ break;
+ case ZXDH_ERAM128_TBL_64b:
+ memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8));
+ break;
+ case ZXDH_ERAM128_TBL_1b:
+ ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data +
+ (3 - col_index / 32)), (col_index % 32), 1);
+ break;
+ default:
+ break;
+ }
+ return rc;
+}
+
+int
+zxdh_np_dtb_table_entry_get(uint32_t dev_id,
+ uint32_t queue_id,
+ ZXDH_DTB_USER_ENTRY_T *get_entry,
+ uint32_t srh_mode)
+{
+ ZXDH_SDT_TBL_DATA_T sdt_tbl = {0};
+ uint32_t tbl_type = 0;
+ uint32_t rc;
+ uint32_t sdt_no;
+
+ sdt_no = get_entry->sdt_no;
+ zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl);
+
+ ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32,
+ ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN);
+ switch (tbl_type) {
+ case ZXDH_SDT_TBLT_ERAM:
+ rc = zxdh_np_dtb_eram_data_get(dev_id,
+ queue_id,
+ sdt_no,
+ (ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data);
+ ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get");
+ break;
+ default:
+ PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type);
+ return 1;
+ }
+
+ return 0;
+}
+
static uint32_t
zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id,
uint32_t queue_id,
diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h
index d0388f3447..8ece4c160f 100644
--- a/drivers/net/zxdh/zxdh_np.h
+++ b/drivers/net/zxdh/zxdh_np.h
@@ -175,6 +175,13 @@
#define ZXDH_DTB_TABLE_MODE_ETCAM (3)
#define ZXDH_DTB_TABLE_MODE_MC_HASH (4)
#define ZXDH_DTB_TABLE_VALID (1)
+#define ZXDH_DTB_DUMP_MODE_ERAM (0)
+#define ZXDH_DTB_DUMP_MODE_ZCAM (2)
+#define ZXDH_DTB_DUMP_MODE_ETCAM (3)
+
+#define ZXDH_DTB_DELAY_TIME (50)
+#define ZXDH_DTB_DOWN_OVER_TIME (2000)
+#define ZXDH_DTB_DUMP_OVER_TIME (0x4c4b40)
/* DTB module error code */
#define ZXDH_RC_DTB_BASE (0xd00)
@@ -611,6 +618,14 @@ typedef enum zxdh_dtb_table_info_e {
ZXDH_DTB_TABLE_ENUM_MAX
} ZXDH_DTB_TABLE_INFO_E;
+typedef enum zxdh_dtb_dump_info_e {
+ ZXDH_DTB_DUMP_ERAM = 0,
+ ZXDH_DTB_DUMP_DDR = 1,
+ ZXDH_DTB_DUMP_ZCAM = 2,
+ ZXDH_DTB_DUMP_ETCAM = 3,
+ ZXDH_DTB_DUMP_ENUM_MAX
+} ZXDH_DTB_DUMP_INFO_E;
+
typedef enum zxdh_sdt_table_type_e {
ZXDH_SDT_TBLT_INVALID = 0,
ZXDH_SDT_TBLT_ERAM = 1,
--
2.27.0
[-- Attachment #1.1.2: Type: text/html , Size: 80323 bytes --]
next prev parent reply other threads:[~2025-02-22 7:36 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-10 1:44 [PATCH v1 01/14] net/zxdh: add network processor registers ops Bingbin Chen
2025-02-10 1:46 ` [PATCH v1 02/14] net/zxdh: support compatibility check Bingbin Chen
2025-02-10 17:25 ` Stephen Hemminger
2025-02-10 1:47 ` [PATCH v1 03/14] net/zxdh: add agent channel Bingbin Chen
2025-02-10 17:28 ` Stephen Hemminger
2025-02-10 17:30 ` Stephen Hemminger
2025-02-10 17:31 ` Stephen Hemminger
2025-02-10 18:23 ` Stephen Hemminger
2025-02-10 1:47 ` [PATCH v1 04/14] net/zxdh: modify dtb queue ops Bingbin Chen
2025-02-10 17:31 ` Stephen Hemminger
2025-02-10 1:48 ` [PATCH v1 05/14] net/zxdh: add tables dump address ops Bingbin Chen
2025-02-10 17:33 ` Stephen Hemminger
2025-02-10 1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen
2025-02-10 1:50 ` [PATCH v1 07/14] net/zxdh: get flow tables resources Bingbin Chen
2025-02-10 17:35 ` Stephen Hemminger
2025-02-10 17:35 ` Stephen Hemminger
2025-02-10 1:50 ` [PATCH v1 08/14] net/zxdh: support hash resources configuration Bingbin Chen
2025-02-10 17:36 ` Stephen Hemminger
2025-02-10 1:50 ` [PATCH v1 09/14] net/zxdh: implement tables initialization Bingbin Chen
2025-02-10 17:40 ` Stephen Hemminger
2025-02-10 17:43 ` Stephen Hemminger
2025-02-10 1:50 ` [PATCH v1 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen
2025-02-10 17:45 ` Stephen Hemminger
2025-02-10 1:50 ` [PATCH v1 11/14] net/zxdh: get hash table entry result Bingbin Chen
2025-02-10 17:46 ` Stephen Hemminger
2025-02-10 1:50 ` [PATCH v1 12/14] net/zxdh: delete all hash entries Bingbin Chen
2025-02-10 17:47 ` Stephen Hemminger
2025-02-10 1:50 ` [PATCH v1 13/14] net/zxdh: add acl tables ops Bingbin Chen
2025-02-10 1:50 ` [PATCH v1 14/14] net/zxdh: clean stat values Bingbin Chen
2025-02-10 17:50 ` Stephen Hemminger
2025-02-10 17:50 ` Stephen Hemminger
2025-02-10 18:19 ` Stephen Hemminger
2025-02-22 7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 01/14] net/zxdh: add network processor registers ops Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 02/14] net/zxdh: support compatibility check Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 03/14] net/zxdh: add agent channel Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 04/14] net/zxdh: modify dtb queue ops Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 05/14] net/zxdh: add tables dump address ops Bingbin Chen
2025-02-22 7:22 ` Bingbin Chen [this message]
2025-02-22 7:22 ` [PATCH v2 07/14] net/zxdh: get flow tables resources Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 08/14] net/zxdh: support hash resources configuration Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 09/14] net/zxdh: implement tables initialization Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 11/14] net/zxdh: get hash table entry result Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 12/14] net/zxdh: delete all hash entries Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 13/14] net/zxdh: add acl tables ops Bingbin Chen
2025-02-22 7:22 ` [PATCH v2 14/14] net/zxdh: clean stat values Bingbin Chen
2025-02-22 17:34 ` Stephen Hemminger
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