From: Andre Muezerie <andremue@linux.microsoft.com>
To: Bruce Richardson <bruce.richardson@intel.com>
Cc: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>, dev@dpdk.org
Subject: Re: [PATCH 5/6] acl: make compatible with instruction set updates for MSVC
Date: Tue, 25 Feb 2025 08:37:27 -0800 [thread overview]
Message-ID: <20250225163727.GA16121@linuxonhyperv3.guj3yctzbm1etfxqx2vob5hsef.xx.internal.cloudapp.net> (raw)
In-Reply-To: <Z72HaaPEhxfIk2QV@bricha3-mobl1.ger.corp.intel.com>
On Tue, Feb 25, 2025 at 09:03:37AM +0000, Bruce Richardson wrote:
> On Mon, Feb 24, 2025 at 01:01:18PM -0800, Andre Muezerie wrote:
> > Top level 'cc_avx2_flags' was created and holds the correct flags
> > depending on the compiler used.
> >
> > File meson.build was updated to handle the correct AVX512 flags
> > depending on compiler used.
> >
> > Signed-off-by: Andre Muezerie <andremue@linux.microsoft.com>
> > ---
> > lib/acl/meson.build | 16 +++++++++-------
> > 1 file changed, 9 insertions(+), 7 deletions(-)
> >
> > diff --git a/lib/acl/meson.build b/lib/acl/meson.build
> > index fefe131a48..24e47b6cc1 100644
> > --- a/lib/acl/meson.build
> > +++ b/lib/acl/meson.build
> > @@ -19,7 +19,7 @@ if dpdk_conf.has('RTE_ARCH_X86')
> > avx2_tmplib = static_library('avx2_tmp',
> > 'acl_run_avx2.c',
> > dependencies: static_rte_eal,
> > - c_args: cflags + ['-mavx2'])
> > + c_args: [cflags, cc_avx2_flags])
> > objs += avx2_tmplib.extract_objects('acl_run_avx2.c')
> >
> > # compile AVX512 version if:
> > @@ -38,6 +38,12 @@ if dpdk_conf.has('RTE_ARCH_X86')
> > # compiler flags, and then have the .o file from static lib
> > # linked into main lib.
> >
> > + if is_ms_compiler
> > + acl_avx512_args = cc_avx512_flags
> > + else
> > + acl_avx512_args = ['-mavx512f', '-mavx512vl', '-mavx512cd', '-mavx512bw']
> > + endif
> > +
>
> in the non-msvc case are these flags not the same as cc_avx512_flags too?
> If so, let's just get rid of the acl_avx512_args variable generally.
>
> /Bruce
It's not an exact match. I did not look further to see if this was intentional or result
of a typo. TBH I'm not even sure if it would be possible to deduct this from the code.
Also, all the CPUs I have looked at bring all these 5 instruction sets together, but we
know this might not hold true in the future as each one of them has an independent CPUID flag.
cc_avx512_flags = ['-mavx512f', '-mavx512vl', '-mavx512dq', '-mavx512bw']
My choice was to keep the flags that were used initially, but I can change that if the
maintainers tell me this was a mistake.
next prev parent reply other threads:[~2025-02-25 16:37 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-24 21:01 [PATCH 0/6] allow faster instruction sets to be used with MSVC Andre Muezerie
2025-02-24 21:01 ` [PATCH 1/6] eal: make compatible with instruction set updates for MSVC Andre Muezerie
2025-02-24 21:01 ` [PATCH 2/6] eal: only use numbers as align parameters " Andre Muezerie
2025-02-24 21:01 ` [PATCH 3/6] config: allow faster instruction sets to be used with MSVC Andre Muezerie
2025-02-25 14:28 ` Bruce Richardson
2025-02-24 21:01 ` [PATCH 4/6] drivers/net: make compatible with instruction set updates for MSVC Andre Muezerie
2025-02-25 9:06 ` Bruce Richardson
2025-02-25 16:44 ` Andre Muezerie
2025-02-24 21:01 ` [PATCH 5/6] acl: " Andre Muezerie
2025-02-25 9:03 ` Bruce Richardson
2025-02-25 16:37 ` Andre Muezerie [this message]
2025-02-25 17:21 ` Bruce Richardson
2025-02-25 17:23 ` Andre Muezerie
2025-02-24 21:01 ` [PATCH 6/6] member: " Andre Muezerie
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