From: Nawal Kishor <nkishor@marvell.com>
To: <dev@dpdk.org>, Nithin Kumar Dabilpuram <ndabilpuram@marvell.com>,
"Kiran Kumar K" <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>,
Harman Kalra <hkalra@marvell.com>,
"Ashwin Sekhar T K" <asekhar@marvell.com>
Cc: <jerinj@marvell.com>, Nawal Kishor <nkishor@marvell.com>
Subject: [PATCH] common/cnxk: fix aura offset
Date: Tue, 4 Mar 2025 10:52:17 +0530 [thread overview]
Message-ID: <20250304052217.796506-1-nkishor@marvell.com> (raw)
Fix aura offset in NPA_LF_POOL_OP_INT.
Fixes: 620fc02bf7eb ("common/cnxk: accommodate change in aura field width")
Signed-off-by: Nawal Kishor <nkishor@marvell.com>
---
drivers/common/cnxk/roc_npa_irq.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/common/cnxk/roc_npa_irq.c b/drivers/common/cnxk/roc_npa_irq.c
index 0a19319ebf..9505194207 100644
--- a/drivers/common/cnxk/roc_npa_irq.c
+++ b/drivers/common/cnxk/roc_npa_irq.c
@@ -104,14 +104,15 @@ static inline uint8_t
npa_q_irq_get_and_clear(struct npa_lf *lf, uint32_t q, uint32_t off,
uint64_t mask)
{
- uint64_t reg, wdata;
+ uint64_t reg, wdata, shift;
uint8_t qint;
- wdata = (uint64_t)q << 44;
+ shift = roc_model_is_cn20k() ? 47 : 44;
+ wdata = (uint64_t)q << shift;
reg = roc_atomic64_add_nosync(wdata, (int64_t *)(lf->base + off));
if (reg & BIT_ULL(42) /* OP_ERR */) {
- plt_err("Failed execute irq get off=0x%x", off);
+ plt_err("Failed execute irq get off=0x%x reg=0x%lx", off, reg);
return 0;
}
--
2.34.1
reply other threads:[~2025-03-04 5:22 UTC|newest]
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