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From: Bingbin Chen <chen.bingbin@zte.com.cn>
To: stephen@networkplumber.org, wang.junlong1@zte.com.cn,
	yang.yonggang@zte.com.cn
Cc: dev@dpdk.org, Bingbin Chen <chen.bingbin@zte.com.cn>
Subject: [PATCH v4 01/14] net/zxdh: add network processor registers ops
Date: Mon, 17 Mar 2025 22:57:49 +0800	[thread overview]
Message-ID: <20250317145802.1819809-2-chen.bingbin@zte.com.cn> (raw)
In-Reply-To: <20250317145802.1819809-1-chen.bingbin@zte.com.cn>


[-- Attachment #1.1.1: Type: text/plain, Size: 100114 bytes --]

Add (np)network processor registers read/write interfaces.

Signed-off-by: Bingbin Chen <chen.bingbin@zte.com.cn>
---
 drivers/net/zxdh/zxdh_np.c | 1877 ++++++++++++++++++++++++++----------
 drivers/net/zxdh/zxdh_np.h |  226 +++--
 2 files changed, 1511 insertions(+), 592 deletions(-)

diff --git a/drivers/net/zxdh/zxdh_np.c b/drivers/net/zxdh/zxdh_np.c
index 28c9e4c1c1..1534cb2709 100644
--- a/drivers/net/zxdh/zxdh_np.c
+++ b/drivers/net/zxdh/zxdh_np.c
@@ -15,7 +15,6 @@
 #include "zxdh_logs.h"
 #include "zxdh_msg.h"
 
-static uint64_t g_np_bar_offset;
 static ZXDH_DEV_MGR_T g_dev_mgr;
 static ZXDH_SDT_MGR_T g_sdt_mgr;
 static uint32_t g_dpp_dtb_int_enable;
@@ -23,32 +22,209 @@ static uint32_t g_table_type[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX];
 static ZXDH_PPU_CLS_BITMAP_T g_ppu_cls_bit_map[ZXDH_DEV_CHANNEL_MAX];
 static ZXDH_DTB_MGR_T *p_dpp_dtb_mgr[ZXDH_DEV_CHANNEL_MAX];
 static ZXDH_RISCV_DTB_MGR *p_riscv_dtb_queue_mgr[ZXDH_DEV_CHANNEL_MAX];
-static ZXDH_TLB_MGR_T *g_p_dpp_tlb_mgr[ZXDH_DEV_CHANNEL_MAX];
-static ZXDH_REG_T g_dpp_reg_info[4];
-static ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[4];
 static ZXDH_SDT_TBL_DATA_T g_sdt_info[ZXDH_DEV_CHANNEL_MAX][ZXDH_DEV_SDT_ID_MAX];
-static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg;
+static ZXDH_PPU_STAT_CFG_T g_ppu_stat_cfg[ZXDH_DEV_CHANNEL_MAX];
+
+static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_cmd_reg[] = {
+	{"cpu_ind_rw", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
+	{"cpu_ind_rd_mode", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
+	{"cpu_req_mode", ZXDH_FIELD_FLAG_RW, 27, 2, 0x0, 0x0},
+	{"cpu_ind_addr", ZXDH_FIELD_FLAG_RW, 25, 26, 0x0, 0x0},
+};
+
+static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rd_done_reg[] = {
+	{"cpu_ind_rd_done", ZXDH_FIELD_FLAG_RO, 0, 1, 0x0, 0x0},
+};
+
+static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat0_reg[] = {
+	{"cpu_ind_rdat0", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
+};
+
+static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat1_reg[] = {
+	{"cpu_ind_rdat1", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
+};
+
+static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat2_reg[] = {
+	{"cpu_ind_rdat2", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
+};
+
+static const ZXDH_FIELD_T g_smmu0_smmu0_cpu_ind_rdat3_reg[] = {
+	{"cpu_ind_rdat3", ZXDH_FIELD_FLAG_RO, 31, 32, 0x0, 0x0},
+};
+
+static const ZXDH_FIELD_T g_smmu0_smmu0_wr_arb_cpu_rdy_reg[] = {
+	{"wr_arb_cpu_rdy", ZXDH_FIELD_FLAG_RO, 0, 1, 0x1, 0x0},
+};
+
+static const ZXDH_FIELD_T g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg[] = {
+	{"info_queue_buf_space_left", ZXDH_FIELD_FLAG_RO, 5, 6, 0x20, 0x0},
+};
+
+static const ZXDH_FIELD_T g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg[] = {
+	{"dbi_en", ZXDH_FIELD_FLAG_RW, 31, 1, 0x0, 0x0},
+	{"queue_en", ZXDH_FIELD_FLAG_RW, 30, 1, 0x0, 0x0},
+	{"cfg_epid", ZXDH_FIELD_FLAG_RW, 27, 4, 0x0, 0x0},
+	{"cfg_vfunc_num", ZXDH_FIELD_FLAG_RW, 23, 8, 0x0, 0x0},
+	{"cfg_vector", ZXDH_FIELD_FLAG_RW, 14, 7, 0x0, 0x0},
+	{"cfg_func_num", ZXDH_FIELD_FLAG_RW, 7, 3, 0x0, 0x0},
+	{"cfg_vfunc_active", ZXDH_FIELD_FLAG_RW, 0, 1, 0x0, 0x0},
+};
+
+static const ZXDH_DTB_FIELD_T g_dtb_ddr_table_cmd_info[] = {
+	{"valid", 127, 1},
+	{"type_mode", 126, 3},
+	{"rw_len", 123, 2},
+	{"v46_flag", 121, 1},
+	{"lpm_wr_vld", 120, 1},
+	{"baddr", 119, 20},
+	{"ecc_en", 99, 1},
+	{"rw_addr", 29, 30},
+};
+
+static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_1_info[] = {
+	{"valid", 127, 1},
+	{"type_mode", 126, 3},
+	{"data_mode", 123, 2},
+	{"cpu_wr", 121, 1},
+	{"cpu_rd", 120, 1},
+	{"cpu_rd_mode", 119, 1},
+	{"addr", 113, 26},
+	{"data_h", 0, 1},
+};
+
+static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_64_info[] = {
+	{"valid", 127, 1},
+	{"type_mode", 126, 3},
+	{"data_mode", 123, 2},
+	{"cpu_wr", 121, 1},
+	{"cpu_rd", 120, 1},
+	{"cpu_rd_mode", 119, 1},
+	{"addr", 113, 26},
+	{"data_h", 63, 32},
+	{"data_l", 31, 32},
+};
+
+static const ZXDH_DTB_FIELD_T g_dtb_eram_table_cmd_128_info[] = {
+	{"valid", 127, 1},
+	{"type_mode", 126, 3},
+	{"data_mode", 123, 2},
+	{"cpu_wr", 121, 1},
+	{"cpu_rd", 120, 1},
+	{"cpu_rd_mode", 119, 1},
+	{"addr", 113, 26},
+};
+
+static const ZXDH_DTB_FIELD_T g_dtb_zcam_table_cmd_info[] = {
+	{"valid", 127, 1},
+	{"type_mode", 126, 3},
+	{"ram_reg_flag", 123, 1},
+	{"zgroup_id", 122, 2},
+	{"zblock_id", 120, 3},
+	{"zcell_id", 117, 2},
+	{"mask", 115, 4},
+	{"sram_addr", 111, 9},
+};
+
+static const ZXDH_DTB_FIELD_T g_dtb_etcam_table_cmd_info[] = {
+	{"valid", 127, 1},
+	{"type_mode", 126, 3},
+	{"block_sel", 123, 3},
+	{"init_en", 120, 1},
+	{"row_or_col_msk", 119, 1},
+	{"vben", 118, 1},
+	{"reg_tcam_flag", 117, 1},
+	{"uload", 116, 8},
+	{"rd_wr", 108, 1},
+	{"wr_mode", 107, 8},
+	{"data_or_mask", 99, 1},
+	{"addr", 98, 9},
+	{"vbit", 89, 8},
+};
+
+static const ZXDH_DTB_FIELD_T g_dtb_mc_hash_table_cmd_info[] = {
+	{"valid", 127, 1},
+	{"type_mode", 126, 3},
+	{"std_h", 63, 32},
+	{"std_l", 31, 32},
+};
+
+static const ZXDH_DTB_TABLE_T g_dpp_dtb_table_info[] = {
+	{
+		"ddr",
+		ZXDH_DTB_TABLE_DDR,
+		8,
+		g_dtb_ddr_table_cmd_info,
+	},
+	{
+		"eram 1 bit",
+		ZXDH_DTB_TABLE_ERAM_1,
+		8,
+		g_dtb_eram_table_cmd_1_info,
+	},
+	{
+		"eram 64 bit",
+		ZXDH_DTB_TABLE_ERAM_64,
+		9,
+		g_dtb_eram_table_cmd_64_info,
+	},
+	{
+		"eram 128 bit",
+		ZXDH_DTB_TABLE_ERAM_128,
+		7,
+		g_dtb_eram_table_cmd_128_info,
+	},
+	{
+		"zcam",
+		ZXDH_DTB_TABLE_ZCAM,
+		8,
+		g_dtb_zcam_table_cmd_info,
+	},
+	{
+		"etcam",
+		ZXDH_DTB_TABLE_ETCAM,
+		13,
+		g_dtb_etcam_table_cmd_info,
+	},
+	{
+		"mc_hash",
+		ZXDH_DTB_TABLE_MC_HASH,
+		4,
+		g_dtb_mc_hash_table_cmd_info
+	},
+};
 
 #define ZXDH_SDT_MGR_PTR_GET()    (&g_sdt_mgr)
 #define ZXDH_SDT_SOFT_TBL_GET(id) (g_sdt_mgr.sdt_tbl_array[id])
+#define ZXDH_DEV_INFO_GET(id) (g_dev_mgr.p_dev_array[id])
+
+#define ZXDH_DTB_LEN(cmd_type, int_en, data_len) \
+	(((data_len) & 0x3ff) | \
+	((int_en) << 29) | \
+	((cmd_type) << 30))
 
-#define ZXDH_COMM_MASK_BIT(_bitnum_)\
-	(0x1U << (_bitnum_))
+static inline uint32_t
+zxdh_np_comm_mask_bit(uint32_t bitnum) {
+	return (uint32_t)(0x1U << bitnum);
+}
 
-#define ZXDH_COMM_GET_BIT_MASK(_inttype_, _bitqnt_)\
-	((_inttype_)(((_bitqnt_) < 32)))
+static inline uint32_t
+zxdh_np_comm_get_bit_mask(uint32_t bit_quantity) {
+	if (bit_quantity < 32)
+		return zxdh_np_comm_mask_bit(bit_quantity & 0x1F) - 1;
+	else
+		return 0xFFFFFFFF;
+}
 
 #define ZXDH_COMM_UINT32_GET_BITS(_uidst_, _uisrc_, _uistartpos_, _uilen_)\
 	((_uidst_) = (((_uisrc_) >> (_uistartpos_)) & \
-	(ZXDH_COMM_GET_BIT_MASK(uint32_t, (_uilen_)))))
+	(zxdh_np_comm_get_bit_mask((_uilen_)))))
 
 #define ZXDH_REG_DATA_MAX      (128)
 
 #define ZXDH_COMM_CHECK_DEV_POINT(dev_id, point)\
 do {\
 	if (NULL == (point)) {\
-		PMD_DRV_LOG(ERR, "dev: %d ZXIC %s:%d[Error:POINT NULL] !"\
-			"FUNCTION : %s!", (dev_id), __FILE__, __LINE__, __func__);\
+		PMD_DRV_LOG(ERR, "dev: %u [POINT NULL]", (dev_id));\
 		RTE_ASSERT(0);\
 	} \
 } while (0)
@@ -56,33 +232,22 @@ do {\
 #define ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, becall)\
 do {\
 	if ((rc) != 0) {\
-		PMD_DRV_LOG(ERR, "dev: %d ZXIC  %s:%d !"\
-		"-- %s Call %s Fail!", (dev_id), __FILE__, __LINE__, __func__, becall);\
+		PMD_DRV_LOG(ERR, "dev: %u, %s failed!", (dev_id), becall);\
 		RTE_ASSERT(0);\
 	} \
 } while (0)
 
-#define ZXDH_COMM_CHECK_POINT_NO_ASSERT(point)\
-do {\
-	if ((point) == NULL) {\
-		PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\
-		__FILE__, __LINE__, __func__);\
-	} \
-} while (0)
-
 #define ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, becall)\
 do {\
 	if ((rc) != 0) {\
-		PMD_DRV_LOG(ERR, "ZXIC  %s:%d !-- %s Call %s"\
-		" Fail!", __FILE__, __LINE__, __func__, becall);\
+		PMD_DRV_LOG(ERR, "%s failed!", becall);\
 	} \
 } while (0)
 
 #define ZXDH_COMM_CHECK_RC(rc, becall)\
 do {\
 	if ((rc) != 0) {\
-		PMD_DRV_LOG(ERR, "ZXIC  %s:%d!-- %s Call %s "\
-		"Fail!", __FILE__, __LINE__, __func__, becall);\
+		PMD_DRV_LOG(ERR, "%s failed!", becall);\
 		RTE_ASSERT(0);\
 	} \
 } while (0)
@@ -90,34 +255,28 @@ do {\
 #define ZXDH_COMM_CHECK_POINT(point)\
 do {\
 	if ((point) == NULL) {\
-		PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] ! FUNCTION : %s!",\
-		__FILE__, __LINE__, __func__);\
+		PMD_DRV_LOG(ERR, "[POINT NULL]");\
 		RTE_ASSERT(0);\
 	} \
 } while (0)
 
+static inline uint16_t zxdh_np_comm_convert16(uint16_t w_data)
+{
+	return ((w_data) & 0xff) << 8 | ((w_data) & 0xff00) >> 8;
+}
 
-#define ZXDH_COMM_CHECK_POINT_MEMORY_FREE(point, ptr)\
-do {\
-	if ((point) == NULL) {\
-		PMD_DRV_LOG(ERR, "ZXIC %s:%d[Error:POINT NULL] !"\
-		"FUNCTION : %s!", __FILE__, __LINE__, __func__);\
-		rte_free(ptr);\
-		RTE_ASSERT(0);\
-	} \
-} while (0)
-
-#define ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc, becall, ptr)\
-do {\
-	if ((rc) != 0) {\
-		PMD_DRV_LOG(ERR, "ZXICP  %s:%d, %s Call"\
-		" %s Fail!", __FILE__, __LINE__, __func__, becall);\
-		rte_free(ptr);\
-	} \
-} while (0)
+static inline uint32_t
+zxdh_np_comm_convert32(uint32_t dw_data)
+{
+	return ((dw_data) & 0xff) << 24 | ((dw_data) & 0xff00) << 8 |
+		((dw_data) & 0xff0000) >> 8 | ((dw_data) & 0xff000000) >> 24;
+}
 
 #define ZXDH_COMM_CONVERT16(w_data) \
-			(((w_data) & 0xff) << 8)
+			zxdh_np_comm_convert16(w_data)
+
+#define ZXDH_COMM_CONVERT32(w_data) \
+			zxdh_np_comm_convert32(w_data)
 
 #define ZXDH_DTB_TAB_UP_WR_INDEX_GET(DEV_ID, QUEUE_ID)       \
 		(p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.wr_index)
@@ -132,10 +291,12 @@ do {\
 		(p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.data_len[(INDEX)])
 
 #define ZXDH_DTB_TAB_UP_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX)     \
-		((INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.item_size)
+		(p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.start_vir_addr + \
+		(INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_up.item_size)
 
 #define ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX)   \
-		((INDEX) * p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_down.item_size)
+		(p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.start_vir_addr + \
+		INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_down.item_size)
 
 #define ZXDH_DTB_TAB_DOWN_WR_INDEX_GET(DEV_ID, QUEUE_ID)       \
 		(p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].tab_down.wr_index)
@@ -143,7 +304,25 @@ do {\
 #define ZXDH_DTB_QUEUE_INIT_FLAG_GET(DEV_ID, QUEUE_ID)       \
 		(p_dpp_dtb_mgr[(DEV_ID)]->queue_info[(QUEUE_ID)].init_flag)
 
-ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = {
+#define ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(DEV_ID, QUEUE_ID, INDEX)     \
+		(p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].vir_addr)
+
+#define ZXDH_DTB_TAB_UP_USER_ADDR_FLAG_SET(DEV_ID, QUEUE_ID, INDEX, VAL)     \
+		(p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.user_addr[INDEX].user_flag = \
+		VAL)
+
+static inline uint64_t
+zxdh_np_dtb_tab_up_phy_addr_get(uint32_t DEV_ID, uint32_t QUEUE_ID,
+	uint32_t INDEX)
+{
+	return p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.start_phy_addr +
+		INDEX * p_dpp_dtb_mgr[DEV_ID]->queue_info[QUEUE_ID].tab_up.item_size;
+}
+
+#define ZXDH_DTB_TAB_UP_PHY_ADDR_GET(DEV_ID, QUEUE_ID, INDEX)	 \
+	zxdh_np_dtb_tab_up_phy_addr_get(DEV_ID, QUEUE_ID, INDEX)
+
+static ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = {
 	{"cara_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0},
 	{"cara_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0},
 	{"cara_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0},
@@ -155,7 +334,7 @@ ZXDH_FIELD_T g_stat_car0_cara_queue_ram0_159_0_reg[] = {
 	{"cara_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0},
 };
 
-ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = {
+static ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = {
 	{"carb_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0},
 	{"carb_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0},
 	{"carb_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0},
@@ -167,7 +346,7 @@ ZXDH_FIELD_T g_stat_car0_carb_queue_ram0_159_0_reg[] = {
 	{"carb_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0},
 };
 
-ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = {
+static ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = {
 	{"carc_drop", ZXDH_FIELD_FLAG_RW, 147, 1, 0x0, 0x0},
 	{"carc_plcr_en", ZXDH_FIELD_FLAG_RW, 146, 1, 0x0, 0x0},
 	{"carc_profile_id", ZXDH_FIELD_FLAG_RW, 145, 9, 0x0, 0x0},
@@ -179,10 +358,69 @@ ZXDH_FIELD_T g_stat_car0_carc_queue_ram0_159_0_reg[] = {
 	{"carc_tci", ZXDH_FIELD_FLAG_RO, 26, 27, 0x0, 0x0},
 };
 
-ZXDH_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = {
+static ZXDH_FIELD_T g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg[] = {
 	{"pktrx_glbal_cfg_0", ZXDH_FIELD_FLAG_RW, 31, 32, 0x0, 0x0},
 };
 
+static uint32_t zxdh_dtb_info_print(uint32_t dev_id,
+						uint32_t queue_id,
+						uint32_t item_index,
+						ZXDH_DTB_QUEUE_ITEM_INFO_T *item_info)
+{
+	uint64_t element_start_addr = 0;
+	uint64_t ack_start_addr = 0;
+	uint64_t data_addr = 0;
+	uint32_t data = 0;
+	uint32_t i = 0;
+	uint32_t j = 0;
+
+	PMD_DRV_LOG(DEBUG, "queue: %u, element:%u,  %s table info is:",
+				queue_id, item_index, (item_info->cmd_type) ? "up" : "down");
+	PMD_DRV_LOG(DEBUG, "cmd_vld    : %u", item_info->cmd_vld);
+	PMD_DRV_LOG(DEBUG, "cmd_type   : %s", (item_info->cmd_type) ? "up" : "down");
+	PMD_DRV_LOG(DEBUG, "int_en     : %u", item_info->int_en);
+	PMD_DRV_LOG(DEBUG, "data_len   : %u", item_info->data_len);
+	PMD_DRV_LOG(DEBUG, "data_hddr  : 0x%x", item_info->data_hddr);
+	PMD_DRV_LOG(DEBUG, "data_laddr : 0x%x", item_info->data_laddr);
+
+	if (item_info->cmd_type == ZXDH_DTB_DIR_UP_TYPE) {
+		if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) ==
+		ZXDH_DTB_TAB_UP_USER_ADDR_TYPE) {
+			ack_start_addr =
+			ZXDH_DTB_TAB_UP_USER_VIR_ADDR_GET(dev_id, queue_id, item_index);
+		}
+		ack_start_addr = ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, item_index);
+		element_start_addr =
+		ZXDH_DTB_TAB_UP_VIR_ADDR_GET(dev_id, queue_id, item_index) + ZXDH_DTB_ITEM_ACK_SIZE;
+	} else {
+		ack_start_addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, item_index);
+		element_start_addr =
+		ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, item_index)
+		+ ZXDH_DTB_ITEM_ACK_SIZE;
+	}
+	PMD_DRV_LOG(DEBUG, "dtb data:");
+
+	PMD_DRV_LOG(DEBUG, "ack info:");
+	for (j = 0; j < 4; j++) {
+		data  = ZXDH_COMM_CONVERT32(*((uint32_t *)(ack_start_addr + 4 * j)));
+		PMD_DRV_LOG(DEBUG, "0x%08x  ", data);
+	}
+
+	for (i = 0; i < item_info->data_len; i++) {
+		data_addr = element_start_addr + 16 * i;
+
+		PMD_DRV_LOG(DEBUG, "row_%u:", i);
+
+		for (j = 0; j < 4; j++) {
+			data  = ZXDH_COMM_CONVERT32(*((uint32_t *)(data_addr + 4 * j)));
+			PMD_DRV_LOG(DEBUG, "0x%08x  ", data);
+		}
+	}
+
+	PMD_DRV_LOG(DEBUG, "zxdh dtb info print end.");
+	return ZXDH_OK;
+}
+
 static uint32_t
 zxdh_np_comm_is_big_endian(void)
 {
@@ -215,7 +453,7 @@ zxdh_np_comm_swap(uint8_t *p_uc_data, uint32_t dw_byte_len)
 	uc_byte_mode = dw_byte_len % 4 & 0xff;
 
 	for (i = 0; i < dw_byte_num; i++) {
-		(*p_dw_tmp) = ZXDH_COMM_CONVERT16(*p_dw_tmp);
+		(*p_dw_tmp) = ZXDH_COMM_CONVERT32(*p_dw_tmp);
 		p_dw_tmp++;
 	}
 
@@ -239,6 +477,392 @@ zxdh_np_dev_init(void)
 	return 0;
 }
 
+static uint32_t
+zxdh_np_dev_read_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data)
+{
+	ZXDH_DEV_CFG_T *p_dev_info = NULL;
+
+	p_dev_info = ZXDH_DEV_INFO_GET(dev_id);
+
+	if (p_dev_info == NULL) {
+		PMD_DRV_LOG(ERR, "Error: Channel[%u] dev is not exist",
+			dev_id);
+		return ZXDH_ERR;
+	}
+	if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) {
+		p_dev_info->p_pcie_read_fun(dev_id, addr, size, p_data);
+	} else {
+		PMD_DRV_LOG(ERR, "Dev access type[ %u ] is invalid",
+			p_dev_info->access_type);
+		return ZXDH_ERR;
+	}
+
+	return ZXDH_OK;
+}
+
+static uint32_t
+zxdh_np_dev_write_channel(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data)
+{
+	ZXDH_DEV_CFG_T *p_dev_info = NULL;
+
+	p_dev_info = ZXDH_DEV_INFO_GET(dev_id);
+
+	if (p_dev_info == NULL) {
+		PMD_DRV_LOG(ERR, "Error: Channel[%u] dev is not exist", dev_id);
+		return ZXDH_ERR;
+	}
+	if (p_dev_info->access_type == ZXDH_DEV_ACCESS_TYPE_PCIE) {
+		p_dev_info->p_pcie_write_fun(dev_id, addr, size, p_data);
+	} else {
+		PMD_DRV_LOG(ERR, "Dev access type[ %u ] is invalid", p_dev_info->access_type);
+		return ZXDH_ERR;
+	}
+
+	return ZXDH_OK;
+}
+
+static void
+zxdh_np_pci_write32(uint64_t abs_addr, uint32_t *p_data)
+{
+	uint32_t data = 0;
+	uint64_t addr = 0;
+
+	data = *p_data;
+
+	if (zxdh_np_comm_is_big_endian())
+		data = ZXDH_COMM_CONVERT32(data);
+
+	addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET;
+	*((volatile uint32_t *)addr) = data;
+}
+
+static void
+zxdh_np_pci_read32(uint64_t abs_addr, uint32_t *p_data)
+{
+	uint32_t data = 0;
+	uint64_t addr = 0;
+
+	addr = abs_addr + ZXDH_SYS_VF_NP_BASE_OFFSET;
+	data = *((volatile uint32_t *)addr);
+
+	if (zxdh_np_comm_is_big_endian())
+		data = ZXDH_COMM_CONVERT32(data);
+
+	*p_data = data;
+}
+
+static uint64_t
+zxdh_np_dev_get_pcie_addr(uint32_t dev_id)
+{
+	ZXDH_DEV_MGR_T *p_dev_mgr = NULL;
+	ZXDH_DEV_CFG_T *p_dev_info = NULL;
+
+	p_dev_mgr = &g_dev_mgr;
+	p_dev_info = p_dev_mgr->p_dev_array[dev_id];
+
+	if (p_dev_info == NULL)
+		return ZXDH_DEV_TYPE_INVALID;
+
+	return p_dev_info->pcie_addr;
+}
+
+static void
+zxdh_np_dev_pcie_default_write(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data)
+{
+	uint32_t i;
+	uint64_t abs_addr = 0;
+
+	abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr;
+
+	for (i = 0; i < size; i++)
+		zxdh_np_pci_write32(abs_addr + 4 * i, p_data + i);
+}
+
+static void
+zxdh_np_dev_pcie_default_read(uint32_t dev_id, uint32_t addr, uint32_t size, uint32_t *p_data)
+{
+	uint32_t i;
+	uint64_t abs_addr = 0;
+
+	abs_addr = zxdh_np_dev_get_pcie_addr(dev_id) + addr;
+
+	for (i = 0; i < size; i++)
+		zxdh_np_pci_read32(abs_addr + 4 * i, p_data + i);
+}
+
+static uint32_t
+zxdh_np_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data)
+{
+	return zxdh_np_dev_read_channel(dev_id, addr, 1, p_data);
+}
+
+static uint32_t
+zxdh_np_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data)
+{
+	return zxdh_np_dev_write_channel(dev_id, addr, 1, p_data);
+}
+
+static uint32_t
+zxdh_np_se_smmu0_write(uint32_t dev_id, uint32_t addr, uint32_t *p_data)
+{
+	return zxdh_np_write(dev_id, addr, p_data);
+}
+
+static uint32_t
+zxdh_np_se_smmu0_read(uint32_t dev_id, uint32_t addr, uint32_t *p_data)
+{
+	return zxdh_np_read(dev_id, addr, p_data);
+}
+
+static ZXDH_REG_T g_dpp_reg_info[] = {
+	{
+		.reg_name = "cpu_ind_cmd",
+		.reg_no = 669,
+		.module_no = SMMU0,
+		.flags = ZXDH_REG_FLAG_DIRECT,
+		.array_type = ZXDH_REG_NUL_ARRAY,
+		.addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x14,
+		.width = (32 / 8),
+		.m_size = 0,
+		.n_size = 0,
+		.m_step = 0,
+		.n_step = 0,
+		.field_num = 4,
+		.p_fields = g_smmu0_smmu0_cpu_ind_cmd_reg,
+		.p_write_fun = zxdh_np_se_smmu0_write,
+		.p_read_fun = zxdh_np_se_smmu0_read,
+	},
+	{
+		.reg_name = "cpu_ind_rd_done",
+		.reg_no = 670,
+		.module_no = SMMU0,
+		.flags = ZXDH_REG_FLAG_DIRECT,
+		.array_type = ZXDH_REG_NUL_ARRAY,
+		.addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x40,
+		.width = (32 / 8),
+		.m_size = 0,
+		.n_size = 0,
+		.m_step = 0,
+		.n_step = 0,
+		.field_num = 1,
+		.p_fields = g_smmu0_smmu0_cpu_ind_rd_done_reg,
+		.p_write_fun = zxdh_np_se_smmu0_write,
+		.p_read_fun = zxdh_np_se_smmu0_read,
+	},
+	{
+		.reg_name = "cpu_ind_rdat0",
+		.reg_no = 671,
+		.module_no = SMMU0,
+		.flags = ZXDH_REG_FLAG_DIRECT,
+		.array_type = ZXDH_REG_NUL_ARRAY,
+		.addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x44,
+		.width = (32 / 8),
+		.m_size = 0,
+		.n_size = 0,
+		.m_step = 0,
+		.n_step = 0,
+		.field_num = 1,
+		.p_fields = g_smmu0_smmu0_cpu_ind_rdat0_reg,
+		.p_write_fun = zxdh_np_se_smmu0_write,
+		.p_read_fun = zxdh_np_se_smmu0_read,
+	},
+	{
+		.reg_name = "cpu_ind_rdat1",
+		.reg_no = 672,
+		.module_no = SMMU0,
+		.flags = ZXDH_REG_FLAG_DIRECT,
+		.array_type = ZXDH_REG_NUL_ARRAY,
+		.addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x48,
+		.width = (32 / 8),
+		.m_size = 0,
+		.n_size = 0,
+		.m_step = 0,
+		.n_step = 0,
+		.field_num = 1,
+		.p_fields = g_smmu0_smmu0_cpu_ind_rdat1_reg,
+		.p_write_fun = zxdh_np_se_smmu0_write,
+		.p_read_fun = zxdh_np_se_smmu0_read,
+	},
+	{
+		.reg_name = "cpu_ind_rdat2",
+		.reg_no = 673,
+		.module_no = SMMU0,
+		.flags = ZXDH_REG_FLAG_DIRECT,
+		.array_type = ZXDH_REG_NUL_ARRAY,
+		.addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x4c,
+		.width = (32 / 8),
+		.m_size = 0,
+		.n_size = 0,
+		.m_step = 0,
+		.n_step = 0,
+		.field_num = 1,
+		.p_fields = g_smmu0_smmu0_cpu_ind_rdat2_reg,
+		.p_write_fun = zxdh_np_se_smmu0_write,
+		.p_read_fun = zxdh_np_se_smmu0_read,
+	},
+	{
+		.reg_name = "cpu_ind_rdat3",
+		.reg_no = 674,
+		.module_no = SMMU0,
+		.flags = ZXDH_REG_FLAG_DIRECT,
+		.array_type = ZXDH_REG_NUL_ARRAY,
+		.addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x50,
+		.width = (32 / 8),
+		.m_size = 0,
+		.n_size = 0,
+		.m_step = 0,
+		.n_step = 0,
+		.field_num = 1,
+		.p_fields = g_smmu0_smmu0_cpu_ind_rdat3_reg,
+		.p_write_fun = zxdh_np_se_smmu0_write,
+		.p_read_fun = zxdh_np_se_smmu0_read,
+	},
+	{
+		.reg_name = "wr_arb_cpu_rdy",
+		.reg_no = 676,
+		.module_no = SMMU0,
+		.flags = ZXDH_REG_FLAG_DIRECT,
+		.array_type = ZXDH_REG_NUL_ARRAY,
+		.addr = ZXDH_SYS_SE_SMMU0_BASE_ADDR + ZXDH_MODULE_SE_SMMU0_BASE_ADDR + 0x10c,
+		.width = (32 / 8),
+		.m_size = 0,
+		.n_size = 0,
+		.m_step = 0,
+		.n_step = 0,
+		.field_num = 1,
+		.p_fields = g_smmu0_smmu0_wr_arb_cpu_rdy_reg,
+		.p_write_fun = zxdh_np_se_smmu0_write,
+		.p_read_fun = zxdh_np_se_smmu0_read,
+	},
+	{
+		.reg_name = "info_queue_buf_space_left_0_127",
+		.reg_no = 820,
+		.module_no = DTB4K,
+		.flags = ZXDH_REG_FLAG_DIRECT,
+		.array_type = ZXDH_REG_UNI_ARRAY,
+		.addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0xc,
+		.width = (32 / 8),
+		.m_size = 0,
+		.n_size = 127 + 1,
+		.m_step = 0,
+		.n_step = 32,
+		.field_num = 1,
+		.p_fields = g_dtb4k_dtb_enq_info_queue_buf_space_left_0_127_reg,
+		.p_write_fun = zxdh_np_write,
+		.p_read_fun = zxdh_np_read,
+	},
+	{
+		.reg_name = "cfg_epid_v_func_num_0_127",
+		.reg_no = 821,
+		.module_no = DTB4K,
+		.flags = ZXDH_REG_FLAG_DIRECT,
+		.array_type = ZXDH_REG_UNI_ARRAY,
+		.addr = ZXDH_SYS_DTB_BASE_ADDR + ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x10,
+		.width = (32 / 8),
+		.m_size = 0,
+		.n_size = 127 + 1,
+		.m_step = 0,
+		.n_step = 32,
+		.field_num = 7,
+		.p_fields = g_dtb4k_dtb_enq_cfg_epid_v_func_num_0_127_reg,
+		.p_write_fun = zxdh_np_write,
+		.p_read_fun = zxdh_np_read,
+	},
+	{
+		.reg_name = "cara_queue_ram0_159_0",
+		.reg_no = 721,
+		.module_no = STAT,
+		.flags = ZXDH_REG_FLAG_INDIRECT,
+		.array_type = ZXDH_REG_UNI_ARRAY,
+		.addr = 0x000000 + 0x14000000,
+		.width = (160 / 8),
+		.m_size = 0,
+		.n_size = 0x7FFF + 1,
+		.m_step = 0,
+		.n_step = 8,
+		.field_num = 9,
+		.p_fields = g_stat_car0_cara_queue_ram0_159_0_reg,
+		.p_write_fun = NULL,
+		.p_read_fun = NULL,
+	},
+	{
+		.reg_name = "carb_queue_ram0_159_0",
+		.reg_no = 738,
+		.module_no = STAT,
+		.flags = ZXDH_REG_FLAG_INDIRECT,
+		.array_type = ZXDH_REG_UNI_ARRAY,
+		.addr = 0x100000 + 0x14000000,
+		.width = (160 / 8),
+		.m_size = 0,
+		.n_size = 0xFFF + 1,
+		.m_step = 0,
+		.n_step = 8,
+		.field_num = 9,
+		.p_fields = g_stat_car0_carb_queue_ram0_159_0_reg,
+		.p_write_fun = NULL,
+		.p_read_fun = NULL,
+	},
+	{
+		.reg_name = "carc_queue_ram0_159_0",
+		.reg_no = 755,
+		.module_no = STAT,
+		.flags = ZXDH_REG_FLAG_INDIRECT,
+		.array_type = ZXDH_REG_UNI_ARRAY,
+		.addr = 0x200000 + 0x14000000,
+		.width = (160 / 8),
+		.m_size = 0,
+		.n_size = 0x3FF + 1,
+		.m_step = 0,
+		.n_step = 8,
+		.field_num = 9,
+		.p_fields = g_stat_car0_carc_queue_ram0_159_0_reg,
+		.p_write_fun = NULL,
+		.p_read_fun = NULL,
+	},
+	{
+		.reg_name = "pktrx_glbal_cfg_0",
+		.reg_no = 448,
+		.module_no = NPPU,
+		.flags = ZXDH_REG_FLAG_DIRECT,
+		.array_type = ZXDH_REG_NUL_ARRAY,
+		.addr = ZXDH_SYS_NPPU_BASE_ADDR + ZXDH_MODULE_NPPU_PKTRX_CFG_BASE_ADDR + 0x01f8,
+		.width = (32 / 8),
+		.m_size = 0,
+		.n_size = 0,
+		.m_step = 0,
+		.n_step = 0,
+		.field_num = 1,
+		.p_fields = g_nppu_pktrx_cfg_pktrx_glbal_cfg_0_reg,
+		.p_write_fun = NULL,
+		.p_read_fun = NULL,
+	},
+};
+
+static uint32_t
+zxdh_np_reg_get_reg_addr(uint32_t reg_no, uint32_t m_offset, uint32_t n_offset)
+{
+	uint32_t	 addr		= 0;
+	ZXDH_REG_T  *p_reg_info = NULL;
+
+	p_reg_info = &g_dpp_reg_info[reg_no];
+
+	addr = p_reg_info->addr;
+
+	if (p_reg_info->array_type & ZXDH_REG_UNI_ARRAY) {
+		if (n_offset > (p_reg_info->n_size - 1))
+			PMD_DRV_LOG(ERR, "reg n_offset is out of range, reg_no:%u", reg_no);
+
+		addr += n_offset * p_reg_info->n_step;
+	} else if (p_reg_info->array_type & ZXDH_REG_BIN_ARRAY) {
+		if ((n_offset > (p_reg_info->n_size - 1)) || (m_offset > (p_reg_info->m_size - 1)))
+			PMD_DRV_LOG(ERR, "reg n_offset/m_offset out of range, reg_no:%u", reg_no);
+
+		addr += m_offset * p_reg_info->m_step + n_offset * p_reg_info->n_step;
+	}
+
+	return addr;
+}
+
 static uint32_t
 zxdh_np_dev_add(uint32_t  dev_id, ZXDH_DEV_TYPE_E dev_type,
 		ZXDH_DEV_ACCESS_TYPE_E  access_type, uint64_t  pcie_addr,
@@ -262,7 +886,10 @@ zxdh_np_dev_add(uint32_t  dev_id, ZXDH_DEV_TYPE_E dev_type,
 	} else {
 		/* device is new. */
 		p_dev_info = rte_malloc(NULL, sizeof(ZXDH_DEV_CFG_T), 0);
-		ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_info);
+		if (p_dev_info == NULL) {
+			PMD_DRV_LOG(ERR, "malloc memory failed");
+			return ZXDH_PAR_CHK_POINT_NULL;
+		}
 		p_dev_mgr->p_dev_array[dev_id] = p_dev_info;
 		p_dev_mgr->device_num++;
 	}
@@ -275,7 +902,10 @@ zxdh_np_dev_add(uint32_t  dev_id, ZXDH_DEV_TYPE_E dev_type,
 	p_dev_info->dma_vir_addr = dma_vir_addr;
 	p_dev_info->dma_phy_addr = dma_phy_addr;
 
-	return 0;
+	p_dev_info->p_pcie_write_fun = zxdh_np_dev_pcie_default_write;
+	p_dev_info->p_pcie_read_fun  = zxdh_np_dev_pcie_default_read;
+
+	return ZXDH_OK;
 }
 
 static uint32_t
@@ -323,8 +953,7 @@ zxdh_np_sdt_mgr_create(uint32_t dev_id)
 
 		p_sdt_mgr->channel_num++;
 	} else {
-		PMD_DRV_LOG(ERR, "Error: %s for dev[%d]"
-			"is called repeatedly!", __func__, dev_id);
+		PMD_DRV_LOG(ERR, "called repeatedly!");
 		return 1;
 	}
 
@@ -367,6 +996,61 @@ zxdh_np_ppu_parse_cls_bitmap(uint32_t dev_id,
 	}
 }
 
+static uint32_t
+zxdh_np_agent_channel_sync_send(uint32_t dev_id,
+				ZXDH_AGENT_CHANNEL_MSG_T *p_msg,
+				uint32_t *p_data,
+				uint32_t rep_len)
+{
+	uint32_t ret = ZXDH_OK;
+	uint32_t vport = 0;
+	struct zxdh_pci_bar_msg in = {0};
+	struct zxdh_msg_recviver_mem result = {0};
+	uint32_t *recv_buffer = NULL;
+	uint8_t *reply_ptr = NULL;
+	uint16_t reply_msg_len = 0;
+	uint64_t agent_addr = 0;
+
+	PMD_DRV_LOG(DEBUG, "dev_id:0x%x", dev_id);
+
+	if (ZXDH_IS_PF(vport))
+		in.src = ZXDH_MSG_CHAN_END_PF;
+	else
+		in.src = ZXDH_MSG_CHAN_END_VF;
+
+	in.virt_addr = agent_addr;
+	in.payload_addr = p_msg->msg;
+	in.payload_len = p_msg->msg_len;
+	in.dst = ZXDH_MSG_CHAN_END_RISC;
+	in.module_id = ZXDH_BAR_MDOULE_NPSDK;
+
+	recv_buffer = rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0);
+	if (recv_buffer == NULL) {
+		PMD_DRV_LOG(ERR, "malloc memory failed");
+		return ZXDH_PAR_CHK_POINT_NULL;
+	}
+
+	result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN;
+	result.recv_buffer = recv_buffer;
+
+	ret = zxdh_bar_chan_sync_msg_send(&in, &result);
+	if (ret == ZXDH_BAR_MSG_OK) {
+		reply_ptr = (uint8_t *)(result.recv_buffer);
+		if (*reply_ptr == 0XFF) {
+			reply_msg_len = *(uint16_t *)(reply_ptr + 1);
+			memcpy(p_data, reply_ptr + 4,
+				((reply_msg_len > rep_len) ? rep_len : reply_msg_len));
+		} else {
+			PMD_DRV_LOG(ERR, "Message not replied");
+		}
+	} else {
+		PMD_DRV_LOG(ERR, "Error[0x%x], bar msg send failed!", ret);
+	}
+
+	rte_free(recv_buffer);
+	return ret;
+}
+
 static ZXDH_DTB_MGR_T *
 zxdh_np_dtb_mgr_get(uint32_t dev_id)
 {
@@ -376,6 +1060,24 @@ zxdh_np_dtb_mgr_get(uint32_t dev_id)
 		return p_dpp_dtb_mgr[dev_id];
 }
 
+static uint32_t
+zxdh_np_dtb_mgr_create(uint32_t dev_id)
+{
+	if (p_dpp_dtb_mgr[dev_id] != NULL) {
+		PMD_DRV_LOG(ERR, "ErrorCode[0x%x]: Dma Manager"
+			" is exist!!!", ZXDH_RC_DTB_MGR_EXIST);
+		return ZXDH_RC_DTB_MGR_EXIST;
+	}
+
+	p_dpp_dtb_mgr[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0);
+	if (p_dpp_dtb_mgr[dev_id] == NULL) {
+		PMD_DRV_LOG(ERR, "malloc memory failed");
+		return ZXDH_PAR_CHK_POINT_NULL;
+	}
+
+	return ZXDH_OK;
+}
+
 static uint32_t
 zxdh_np_dtb_soft_init(uint32_t dev_id)
 {
@@ -386,10 +1088,11 @@ zxdh_np_dtb_soft_init(uint32_t dev_id)
 
 	p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id);
 	if (p_dtb_mgr == NULL) {
-		p_dpp_dtb_mgr[dev_id] = rte_zmalloc(NULL, sizeof(ZXDH_DTB_MGR_T), 0);
+		zxdh_np_dtb_mgr_create(dev_id);
+
 		p_dtb_mgr = zxdh_np_dtb_mgr_get(dev_id);
 		if (p_dtb_mgr == NULL)
-			return 1;
+			return ZXDH_RC_DTB_MGR_NOT_EXIST;
 	}
 
 	return 0;
@@ -469,36 +1172,9 @@ zxdh_np_addr_calc(uint64_t pcie_vir_baddr, uint32_t bar_offset)
 
 	np_addr = ((pcie_vir_baddr + bar_offset) > ZXDH_PCIE_NP_MEM_SIZE)
 				? (pcie_vir_baddr + bar_offset - ZXDH_PCIE_NP_MEM_SIZE) : 0;
-	g_np_bar_offset = bar_offset;
-
 	return np_addr;
 }
 
-int
-zxdh_np_host_init(uint32_t dev_id,
-		ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl)
-{
-	ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0};
-	uint32_t rc;
-	uint64_t agent_addr;
-
-	ZXDH_COMM_CHECK_POINT_NO_ASSERT(p_dev_init_ctrl);
-
-	sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10);
-	sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr,
-		p_dev_init_ctrl->np_bar_offset);
-	sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP;
-	rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl);
-	ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init");
-
-	zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport);
-
-	agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr;
-	zxdh_np_dev_agent_addr_set(dev_id, agent_addr);
-
-	return 0;
-}
-
 static ZXDH_RISCV_DTB_MGR *
 zxdh_np_riscv_dtb_queue_mgr_get(uint32_t dev_id)
 {
@@ -611,24 +1287,37 @@ zxdh_np_reg_read(uint32_t dev_id, uint32_t reg_no,
 		uint32_t m_offset, uint32_t n_offset, void *p_data)
 {
 	uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0};
-	ZXDH_REG_T *p_reg_info = NULL;
-	ZXDH_FIELD_T *p_field_info = NULL;
+	ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no];
+	const ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields;
 	uint32_t rc = 0;
 	uint32_t i;
+	uint32_t addr = 0;
+	uint32_t reg_module = p_reg_info->module_no;
 
-	if (reg_no < 4) {
-		p_reg_info = &g_dpp_reg_info[reg_no];
-		p_field_info = p_reg_info->p_fields;
-		for (i = 0; i < p_reg_info->field_num; i++) {
-			rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff,
-									p_reg_info->width * 8,
-									(uint32_t *)p_data + i,
-									p_field_info[i].msb_pos,
-									p_field_info[i].len);
-			ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_read_bits_ex");
-			PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!", dev_id, m_offset, n_offset);
+	addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset);
+
+	if (reg_module == DTB4K) {
+		rc = p_reg_info->p_read_fun(dev_id, addr, p_buff);
+		ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_read_fun");
+	}
+
+	if (!zxdh_np_comm_is_big_endian()) {
+		for (i = 0; i < p_reg_info->width / 4; i++) {
+			PMD_DRV_LOG(DEBUG, "data = 0x%08x.", p_buff[i]);
+			p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]);
 		}
 	}
+
+	for (i = 0; i < p_reg_info->field_num; i++) {
+		rc = zxdh_np_comm_read_bits_ex((uint8_t *)p_buff,
+								p_reg_info->width * 8,
+								(uint32_t *)p_data + i,
+								p_field_info[i].msb_pos,
+								p_field_info[i].len);
+		ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_read_bits_ex");
+		PMD_DRV_LOG(DEBUG, "dev_id %u(%u)(%u)is ok!", dev_id, m_offset, n_offset);
+	}
+
 	return rc;
 }
 
@@ -637,20 +1326,21 @@ zxdh_np_dtb_queue_vm_info_get(uint32_t dev_id,
 		uint32_t queue_id,
 		ZXDH_DTB_QUEUE_VM_INFO_T *p_vm_info)
 {
-	ZXDH_DTB4K_DTB_ENQ_CFG_EPID_V_FUNC_NUM_0_127_T vm_info = {0};
-	uint32_t rc;
+	uint32_t rc = 0;
+	uint32_t dtb_epid_v_func_reg = ZXDH_SYS_DTB_BASE_ADDR +
+		ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0010;
+	uint32_t epid_v_func = 0;
 
-	rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_CFG_EPID_V_FUNC_NUM,
-						0, queue_id, &vm_info);
-	ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_reg_read");
+	rc = zxdh_np_dev_read_channel(dev_id, dtb_epid_v_func_reg + queue_id * 32, 1, &epid_v_func);
+	ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_read_channel");
 
-	p_vm_info->dbi_en = vm_info.dbi_en;
-	p_vm_info->queue_en = vm_info.queue_en;
-	p_vm_info->epid = vm_info.cfg_epid;
-	p_vm_info->vector = vm_info.cfg_vector;
-	p_vm_info->vfunc_num = vm_info.cfg_vfunc_num;
-	p_vm_info->func_num = vm_info.cfg_func_num;
-	p_vm_info->vfunc_active = vm_info.cfg_vfunc_active;
+	p_vm_info->dbi_en = (epid_v_func >> 31 & 0x1);
+	p_vm_info->queue_en = (epid_v_func >> 30 & 0x1);
+	p_vm_info->epid = (epid_v_func >> 24 & 0xF);
+	p_vm_info->vfunc_num = (epid_v_func >> 16 & 0xFF);
+	p_vm_info->vector = (epid_v_func >> 8 & 0x7);
+	p_vm_info->func_num = (epid_v_func >> 5 & 0x7);
+	p_vm_info->vfunc_active = (epid_v_func & 0x1);
 
 	return rc;
 }
@@ -733,32 +1423,50 @@ zxdh_np_reg_write(uint32_t dev_id, uint32_t reg_no,
 			uint32_t m_offset, uint32_t n_offset, void *p_data)
 {
 	uint32_t p_buff[ZXDH_REG_DATA_MAX] = {0};
-	ZXDH_REG_T *p_reg_info = NULL;
-	ZXDH_FIELD_T *p_field_info = NULL;
+	ZXDH_REG_T *p_reg_info = &g_dpp_reg_info[reg_no];
+	const ZXDH_FIELD_T *p_field_info = p_reg_info->p_fields;
 	uint32_t temp_data;
-	uint32_t rc;
+	uint32_t rc = ZXDH_OK;
 	uint32_t i;
+	uint32_t addr = 0;
+	uint32_t reg_module = p_reg_info->module_no;
+
+	for (i = 0; i < p_reg_info->field_num; i++) {
+		if (p_field_info[i].len <= 32) {
+			temp_data = *((uint32_t *)p_data + i) &
+				zxdh_np_comm_get_bit_mask(p_field_info[i].len);
+			rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff,
+								p_reg_info->width * 8,
+								temp_data,
+								p_field_info[i].msb_pos,
+								p_field_info[i].len);
+			ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex");
+		}
+	}
 
-	if (reg_no < 4) {
-		p_reg_info = &g_dpp_reg_info[reg_no];
-		p_field_info = p_reg_info->p_fields;
-
-		for (i = 0; i < p_reg_info->field_num; i++) {
-			if (p_field_info[i].len <= 32) {
-				temp_data = *((uint32_t *)p_data + i);
-				rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_buff,
-									p_reg_info->width * 8,
-									temp_data,
-									p_field_info[i].msb_pos,
-									p_field_info[i].len);
-				ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_comm_write_bits_ex");
-				PMD_DRV_LOG(ERR, "dev_id %d(%d)(%d)is ok!",
-						dev_id, m_offset, n_offset);
-			}
+	PMD_DRV_LOG(DEBUG, "zxdh_np_comm_write_bits_ex data = 0x%08x.", p_buff[0]);
+
+	if (!zxdh_np_comm_is_big_endian()) {
+		for (i = 0; i < p_reg_info->width / 4; i++) {
+			p_buff[i] = ZXDH_COMM_CONVERT32(p_buff[i]);
+
+			PMD_DRV_LOG(DEBUG, "ZXDH_COMM_CONVERT32 data = 0x%08x.",
+				p_buff[i]);
 		}
 	}
 
-	return 0;
+	addr = zxdh_np_reg_get_reg_addr(reg_no, m_offset, n_offset);
+
+	PMD_DRV_LOG(DEBUG, "reg_no = %u. m_offset = %u n_offset = %u",
+		reg_no, m_offset, n_offset);
+	PMD_DRV_LOG(DEBUG, "baseaddr = 0x%08x.", addr);
+
+	if (reg_module == DTB4K) {
+		rc = p_reg_info->p_write_fun(dev_id, addr, p_buff);
+		ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "p_reg_info->p_write_fun");
+	}
+
+	return rc;
 }
 
 static uint32_t
@@ -837,11 +1545,6 @@ zxdh_np_dtb_queue_unused_item_num_get(uint32_t dev_id,
 {
 	uint32_t rc;
 
-	if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM) {
-		*p_item_num = 32;
-		return 0;
-	}
-
 	rc = zxdh_np_reg_read(dev_id, ZXDH_DTB_INFO_QUEUE_BUF_SPACE,
 		0, queue_id, p_item_num);
 	ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_read");
@@ -874,7 +1577,7 @@ zxdh_np_dtb_queue_release(uint32_t devid,
 		char pname[32],
 		uint32_t queueid)
 {
-	uint32_t rc;
+	uint32_t rc = ZXDH_OK;
 
 	ZXDH_COMM_CHECK_DEV_POINT(devid, pname);
 
@@ -891,20 +1594,11 @@ static void
 zxdh_np_dtb_mgr_destroy(uint32_t dev_id)
 {
 	if (p_dpp_dtb_mgr[dev_id] != NULL) {
-		free(p_dpp_dtb_mgr[dev_id]);
+		rte_free(p_dpp_dtb_mgr[dev_id]);
 		p_dpp_dtb_mgr[dev_id] = NULL;
 	}
 }
 
-static void
-zxdh_np_tlb_mgr_destroy(uint32_t dev_id)
-{
-	if (g_p_dpp_tlb_mgr[dev_id] != NULL) {
-		free(g_p_dpp_tlb_mgr[dev_id]);
-		g_p_dpp_tlb_mgr[dev_id] = NULL;
-	}
-}
-
 static void
 zxdh_np_sdt_mgr_destroy(uint32_t dev_id)
 {
@@ -914,7 +1608,7 @@ zxdh_np_sdt_mgr_destroy(uint32_t dev_id)
 	p_sdt_tbl_temp = ZXDH_SDT_SOFT_TBL_GET(dev_id);
 	p_sdt_mgr = ZXDH_SDT_MGR_PTR_GET();
 
-	free(p_sdt_tbl_temp);
+	rte_free(p_sdt_tbl_temp);
 
 	ZXDH_SDT_SOFT_TBL_GET(dev_id) = NULL;
 
@@ -931,7 +1625,7 @@ zxdh_np_dev_del(uint32_t dev_id)
 	p_dev_info = p_dev_mgr->p_dev_array[dev_id];
 
 	if (p_dev_info != NULL) {
-		free(p_dev_info);
+		rte_free(p_dev_info);
 		p_dev_mgr->p_dev_array[dev_id] = NULL;
 		p_dev_mgr->device_num--;
 	}
@@ -946,11 +1640,9 @@ zxdh_np_online_uninit(uint32_t dev_id,
 
 	rc = zxdh_np_dtb_queue_release(dev_id, port_name, queue_id);
 	if (rc != 0)
-		PMD_DRV_LOG(ERR, "%s:dtb release error,"
-			"port name %s queue id %d", __func__, port_name, queue_id);
+		PMD_DRV_LOG(ERR, "dtb release port name %s queue id %u", port_name, queue_id);
 
 	zxdh_np_dtb_mgr_destroy(dev_id);
-	zxdh_np_tlb_mgr_destroy(dev_id);
 	zxdh_np_sdt_mgr_destroy(dev_id);
 	zxdh_np_dev_del(dev_id);
 
@@ -964,8 +1656,8 @@ zxdh_np_sdt_tbl_type_get(uint32_t dev_id, uint32_t sdt_no)
 }
 
 
-static ZXDH_DTB_TABLE_T *
-zxdh_np_table_info_get(uint32_t table_type)
+static const ZXDH_DTB_TABLE_T *
+zxdh_np_dtb_table_info_get(uint32_t table_type)
 {
 	return &g_dpp_dtb_table_info[table_type];
 }
@@ -977,20 +1669,20 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id,
 			void *p_cmd_buff)
 {
 	uint32_t         field_cnt;
-	ZXDH_DTB_TABLE_T     *p_table_info = NULL;
-	ZXDH_DTB_FIELD_T     *p_field_info = NULL;
+	const ZXDH_DTB_TABLE_T     *p_table_info = NULL;
+	const ZXDH_DTB_FIELD_T     *p_field_info = NULL;
 	uint32_t         temp_data;
 	uint32_t         rc = 0;
 
 	ZXDH_COMM_CHECK_POINT(p_cmd_data);
 	ZXDH_COMM_CHECK_POINT(p_cmd_buff);
-	p_table_info = zxdh_np_table_info_get(table_type);
+	p_table_info = zxdh_np_dtb_table_info_get(table_type);
 	p_field_info = p_table_info->p_fields;
 	ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_table_info);
 
 	for (field_cnt = 0; field_cnt < p_table_info->field_num; field_cnt++) {
-		temp_data = *((uint32_t *)p_cmd_data + field_cnt) & ZXDH_COMM_GET_BIT_MASK(uint32_t,
-			p_field_info[field_cnt].len);
+		temp_data = *((uint32_t *)p_cmd_data + field_cnt) &
+					zxdh_np_comm_get_bit_mask(p_field_info[field_cnt].len);
 
 		rc = zxdh_np_comm_write_bits_ex((uint8_t *)p_cmd_buff,
 					ZXDH_DTB_TABLE_CMD_SIZE_BIT,
@@ -998,7 +1690,7 @@ zxdh_np_dtb_write_table_cmd(uint32_t dev_id,
 					p_field_info[field_cnt].lsb_pos,
 					p_field_info[field_cnt].len);
 
-		ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxic_comm_write_bits");
+		ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_np_comm_write_bits_ex");
 	}
 
 	return rc;
@@ -1062,17 +1754,14 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id,
 		uint32_t *p_data,
 		ZXDH_DTB_ENTRY_T *p_entry)
 {
-	uint32_t temp_idx;
+	uint32_t temp_idx = 0;
 	uint32_t dtb_ind_addr;
 	uint32_t rc = 0;
 
 	switch (wrt_mode) {
 	case ZXDH_ERAM128_OPR_128b:
 		if ((0xFFFFFFFF - (base_addr)) < (index)) {
-			PMD_DRV_LOG(ERR, "ICM %s:%d[Error:VALUE[val0=0x%x]"
-				"INVALID] [val1=0x%x] FUNCTION :%s", __FILE__, __LINE__,
-				base_addr, index, __func__);
-
+			PMD_DRV_LOG(ERR, "base addr:0x%x, index:0x%x invalid", base_addr, index);
 			return ZXDH_PAR_CHK_INVALID_INDEX;
 		}
 		if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
@@ -1095,11 +1784,14 @@ zxdh_np_dtb_se_smmu0_ind_write(uint32_t dev_id,
 		}
 
 		temp_idx = index;
+		break;
+	default:
+		break;
 	}
 
 	dtb_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + temp_idx;
 
-	PMD_DRV_LOG(INFO, "dtb eram item 1bit addr: 0x%x", dtb_ind_addr);
+	PMD_DRV_LOG(DEBUG, "dtb eram item 1bit addr: 0x%x", dtb_ind_addr);
 
 	rc = zxdh_np_dtb_smmu0_write_entry_data(dev_id,
 						  wrt_mode,
@@ -1131,6 +1823,126 @@ zxdh_np_eram_dtb_len_get(uint32_t mode)
 	return dtb_len;
 }
 
+static void
+zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data)
+{
+	p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32;
+	p_sdt_data->data_low32  = g_sdt_info[dev_id][sdt_no].data_low32;
+}
+
+static uint32_t
+zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info)
+{
+	uint32_t tbl_type = 0;
+	uint32_t clutch_en = 0;
+	uint32_t tmp = 0;
+
+	ZXDH_SDT_TBL_ERAM_T *p_sdt_eram = NULL;
+	ZXDH_SDT_TBL_HASH_T *p_sdt_hash = NULL;
+	ZXDH_SDT_TBL_ETCAM_T *p_sdt_etcam = NULL;
+	ZXDH_SDT_TBL_PORTTBL_T *p_sdt_porttbl = NULL;
+
+	ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32,
+		ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN);
+	ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1);
+
+	switch (tbl_type) {
+	case ZXDH_SDT_TBLT_ERAM:
+		p_sdt_eram = (ZXDH_SDT_TBL_ERAM_T *)p_sdt_info;
+		p_sdt_eram->table_type = tbl_type;
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_mode, sdt_hig32,
+			ZXDH_SDT_H_ERAM_MODE_BT_POS, ZXDH_SDT_H_ERAM_MODE_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_base_addr, sdt_hig32,
+			ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS, ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_eram->eram_table_depth, sdt_low32,
+			ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS, ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN);
+		p_sdt_eram->eram_clutch_en = clutch_en;
+		break;
+	case ZXDH_SDT_TBLT_HASH:
+		p_sdt_hash = (ZXDH_SDT_TBL_HASH_T *)p_sdt_info;
+		p_sdt_hash->table_type = tbl_type;
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_id, sdt_hig32,
+			ZXDH_SDT_H_HASH_ID_BT_POS, ZXDH_SDT_H_HASH_ID_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_width, sdt_hig32,
+			ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS, ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->key_size, sdt_hig32,
+			ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS, ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->hash_table_id, sdt_hig32,
+			ZXDH_SDT_H_HASH_TABLE_ID_BT_POS, ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->learn_en, sdt_hig32,
+			ZXDH_SDT_H_LEARN_EN_BT_POS, ZXDH_SDT_H_LEARN_EN_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive, sdt_hig32,
+			ZXDH_SDT_H_KEEP_ALIVE_BT_POS, ZXDH_SDT_H_KEEP_ALIVE_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(tmp, sdt_hig32,
+			ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS, ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->keep_alive_baddr, sdt_low32,
+			ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS, ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN);
+		p_sdt_hash->keep_alive_baddr += (tmp << ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_hash->rsp_mode, sdt_low32,
+			ZXDH_SDT_L_RSP_MODE_BT_POS, ZXDH_SDT_L_RSP_MODE_BT_LEN);
+		p_sdt_hash->hash_clutch_en = clutch_en;
+		break;
+
+	case ZXDH_SDT_TBLT_ETCAM:
+		p_sdt_etcam = (ZXDH_SDT_TBL_ETCAM_T *)p_sdt_info;
+		p_sdt_etcam->table_type = tbl_type;
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_id, sdt_hig32,
+			ZXDH_SDT_H_ETCAM_ID_BT_POS, ZXDH_SDT_H_ETCAM_ID_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_key_mode, sdt_hig32,
+			ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS, ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_id, sdt_hig32,
+			ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS, ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->no_as_rsp_mode, sdt_hig32,
+			ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS,
+			ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_en, sdt_hig32,
+			ZXDH_SDT_H_ETCAM_AS_EN_BT_POS, ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(tmp, sdt_hig32, ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS,
+			ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_eram_baddr, sdt_low32,
+			ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS,
+			ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN);
+		p_sdt_etcam->as_eram_baddr += (tmp << ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->as_rsp_mode, sdt_low32,
+			ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS, ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN);
+		ZXDH_COMM_UINT32_GET_BITS(p_sdt_etcam->etcam_table_depth, sdt_low32,
+			ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS, ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN);
+		p_sdt_etcam->etcam_clutch_en = clutch_en;
+		break;
+
+	case ZXDH_SDT_TBLT_PORTTBL:
+		p_sdt_porttbl = (ZXDH_SDT_TBL_PORTTBL_T *)p_sdt_info;
+		p_sdt_porttbl->table_type = tbl_type;
+		p_sdt_porttbl->porttbl_clutch_en = clutch_en;
+		break;
+	default:
+		PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type);
+		return 1;
+	}
+
+	return 0;
+}
+
+static uint32_t
+zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info)
+{
+	ZXDH_SDT_TBL_DATA_T sdt_tbl = {0};
+	uint32_t rc;
+
+	if (sdt_no > ZXDH_DEV_SDT_ID_MAX - 1) {
+		PMD_DRV_LOG(ERR, "SDT NO [ %u ] is invalid!", sdt_no);
+		return ZXDH_PAR_CHK_INVALID_PARA;
+	}
+
+	zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl);
+
+	rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info);
+	if (rc != 0)
+		PMD_DRV_LOG(ERR, "dpp sdt [%u] tbl_data_parser error.", sdt_no);
+
+	return rc;
+}
+
 static uint32_t
 zxdh_np_dtb_eram_one_entry(uint32_t dev_id,
 		uint32_t sdt_no,
@@ -1140,17 +1952,21 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id,
 		ZXDH_DTB_ENTRY_T *p_dtb_one_entry)
 {
 	uint32_t buff[ZXDH_SMMU0_READ_REG_MAX_NUM]      = {0};
-	ZXDH_SDTTBL_ERAM_T sdt_eram           = {0};
+	ZXDH_SDT_TBL_ERAM_T sdt_eram           = {0};
 	ZXDH_DTB_ERAM_ENTRY_INFO_T *peramdata = NULL;
 	uint32_t base_addr;
 	uint32_t index;
 	uint32_t opr_mode;
-	uint32_t rc;
+	uint32_t rc = ZXDH_OK;
 
 	ZXDH_COMM_CHECK_POINT(pdata);
 	ZXDH_COMM_CHECK_POINT(p_dtb_one_entry);
 	ZXDH_COMM_CHECK_POINT(p_dtb_len);
 
+	PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no);
+	rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram);
+	ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get");
+
 	peramdata = (ZXDH_DTB_ERAM_ENTRY_INFO_T *)pdata;
 	index = peramdata->index;
 	base_addr = sdt_eram.eram_base_addr;
@@ -1166,8 +1982,19 @@ zxdh_np_dtb_eram_one_entry(uint32_t dev_id,
 	case ZXDH_ERAM128_TBL_1b:
 		opr_mode = ZXDH_ERAM128_OPR_1b;
 		break;
+	default:
+		break;
 	}
 
+	PMD_DRV_LOG(DEBUG, "std no:0x%x, index:0x%x, base addr:0x%x", sdt_no, index, base_addr);
+	if (opr_mode == ZXDH_ERAM128_OPR_128b)
+		PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x 0x%08x 0x%08x]",
+		peramdata->p_data[0], peramdata->p_data[1],
+		peramdata->p_data[2], peramdata->p_data[3]);
+	else if (opr_mode == ZXDH_ERAM128_OPR_64b)
+		PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x]",
+		peramdata->p_data[0], peramdata->p_data[1]);
+
 	if (del_en) {
 		memset((uint8_t *)buff, 0, sizeof(buff));
 		rc = zxdh_np_dtb_se_smmu0_ind_write(dev_id,
@@ -1274,6 +2101,9 @@ zxdh_np_dtb_item_ack_rd(uint32_t dev_id,
 
 	val = *((volatile uint32_t *)(addr));
 
+	if (!zxdh_np_comm_is_big_endian())
+		val = ZXDH_COMM_CONVERT32(val);
+
 	*p_data = val;
 
 	return 0;
@@ -1294,7 +2124,10 @@ zxdh_np_dtb_item_ack_wr(uint32_t dev_id,
 	else
 		addr = ZXDH_DTB_TAB_DOWN_VIR_ADDR_GET(dev_id, queue_id, index) + pos * 4;
 
-	*((volatile uint32_t *)(addr)) = data;
+	if (!zxdh_np_comm_is_big_endian())
+		data = ZXDH_COMM_CONVERT32(data);
+
+	*((volatile uint32_t *)addr) = data;
 
 	return 0;
 }
@@ -1304,16 +2137,26 @@ zxdh_np_dtb_queue_item_info_set(uint32_t dev_id,
 		uint32_t queue_id,
 		ZXDH_DTB_QUEUE_ITEM_INFO_T *p_item_info)
 {
-	ZXDH_DTB_QUEUE_LEN_T dtb_len = {0};
 	uint32_t rc;
 
-	dtb_len.cfg_dtb_cmd_type = p_item_info->cmd_type;
-	dtb_len.cfg_dtb_cmd_int_en = p_item_info->int_en;
-	dtb_len.cfg_queue_dtb_len = p_item_info->data_len;
+	uint32_t dtb_addr_h_reg = ZXDH_SYS_DTB_BASE_ADDR +
+		ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0000;
+	uint32_t dtb_addr_l_reg = ZXDH_SYS_DTB_BASE_ADDR +
+		ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0004;
+	uint32_t dtb_len_reg = ZXDH_SYS_DTB_BASE_ADDR +
+		ZXDH_MODULE_DTB_ENQ_BASE_ADDR + 0x0008;
+	uint32_t dtb_len = 0;
+
+	rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_h_reg + queue_id * 32,
+		1, &p_item_info->data_hddr);
+	ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail");
+	rc = zxdh_np_dev_write_channel(dev_id, dtb_addr_l_reg + queue_id * 32,
+		1, &p_item_info->data_laddr);
+	ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail");
+	dtb_len = ZXDH_DTB_LEN(p_item_info->cmd_type, p_item_info->int_en, p_item_info->data_len);
+	rc = zxdh_np_dev_write_channel(dev_id, dtb_len_reg + queue_id * 32, 1, &dtb_len);
+	ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dev_write_channel Fail");
 
-	rc = zxdh_np_reg_write(dev_id, ZXDH_DTB_CFG_QUEUE_DTB_LEN,
-						0, queue_id, (void *)&dtb_len);
-	ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_reg_write");
 	return rc;
 }
 
@@ -1335,7 +2178,7 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id,
 	uint32_t rc;
 
 	if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) {
-		PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id);
+		PMD_DRV_LOG(ERR, "dtb queue %u is not init.", queue_id);
 		return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT;
 	}
 
@@ -1344,7 +2187,7 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id,
 
 	rc = zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en);
 	if (!queue_en) {
-		PMD_DRV_LOG(ERR, "the queue %d is not enable!,rc=%d", queue_id, rc);
+		PMD_DRV_LOG(ERR, "the queue %u is not enable!,rc=%u", queue_id, rc);
 		return ZXDH_RC_DTB_QUEUE_NOT_ENABLE;
 	}
 
@@ -1383,6 +2226,8 @@ zxdh_np_dtb_tab_down_info_set(uint32_t dev_id,
 	item_info.data_hddr = ((phy_addr >> 4) >> 32) & 0xffffffff;
 	item_info.data_laddr = (phy_addr >> 4) & 0xffffffff;
 
+	zxdh_dtb_info_print(dev_id, queue_id, item_index, &item_info);
+
 	rc = zxdh_np_dtb_queue_item_info_set(dev_id, queue_id, &item_info);
 	*p_item_index = item_index;
 
@@ -1421,7 +2266,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id,
 	uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT] = {0};
 	uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX] = {0};
 	uint8_t *p_data_buff;
-	uint8_t *p_data_buff_ex;
 	uint32_t element_id = 0xff;
 	uint32_t one_dtb_len = 0;
 	uint32_t dtb_len = 0;
@@ -1435,9 +2279,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id,
 	p_data_buff = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0);
 	ZXDH_COMM_CHECK_POINT(p_data_buff);
 
-	p_data_buff_ex = rte_zmalloc(NULL, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0);
-	ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff);
-
 	dtb_one_entry.cmd = entry_cmd;
 	dtb_one_entry.data = entry_data;
 
@@ -1446,6 +2287,7 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id,
 	for (entry_index = 0; entry_index < entrynum; entry_index++) {
 		pentry = down_entries + entry_index;
 		sdt_no = pentry->sdt_no;
+		PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no);
 		tbl_type = zxdh_np_sdt_tbl_type_get(dev_id, sdt_no);
 		switch (tbl_type) {
 		case ZXDH_SDT_TBLT_ERAM:
@@ -1453,9 +2295,8 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id,
 				pentry->p_entry_data, &one_dtb_len, &dtb_one_entry);
 			break;
 		default:
-			PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type);
+			PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type);
 			rte_free(p_data_buff);
-			rte_free(p_data_buff_ex);
 			return 1;
 		}
 
@@ -1463,9 +2304,7 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id,
 		dtb_len += one_dtb_len;
 		if (dtb_len > max_size) {
 			rte_free(p_data_buff);
-			rte_free(p_data_buff_ex);
-			PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__,
-				max_size);
+			PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size);
 			return ZXDH_RC_DTB_DOWN_LEN_INVALID;
 		}
 		rc = zxdh_np_dtb_data_write(p_data_buff, addr_offset, &dtb_one_entry);
@@ -1475,7 +2314,6 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id,
 
 	if (dtb_len == 0) {
 		rte_free(p_data_buff);
-		rte_free(p_data_buff_ex);
 		return ZXDH_RC_DTB_DOWN_LEN_INVALID;
 	}
 
@@ -1485,18 +2323,10 @@ zxdh_np_dtb_table_entry_write(uint32_t dev_id,
 					p_data_buff,
 					&element_id);
 	rte_free(p_data_buff);
-	rte_free(p_data_buff_ex);
 
 	return rc;
 }
 
-static void
-zxdh_np_sdt_tbl_data_get(uint32_t dev_id, uint32_t sdt_no, ZXDH_SDT_TBL_DATA_T *p_sdt_data)
-{
-	p_sdt_data->data_high32 = g_sdt_info[dev_id][sdt_no].data_high32;
-	p_sdt_data->data_low32  = g_sdt_info[dev_id][sdt_no].data_low32;
-}
-
 int
 zxdh_np_dtb_table_entry_delete(uint32_t dev_id,
 			 uint32_t queue_id,
@@ -1509,7 +2339,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id,
 	uint8_t entry_cmd[ZXDH_DTB_TABLE_CMD_SIZE_BIT / 8] = {0};
 	uint8_t entry_data[ZXDH_ETCAM_WIDTH_MAX / 8] = {0};
 	uint8_t *p_data_buff = NULL;
-	uint8_t *p_data_buff_ex = NULL;
 	uint32_t tbl_type = 0;
 	uint32_t element_id = 0xff;
 	uint32_t one_dtb_len = 0;
@@ -1525,9 +2354,6 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id,
 	p_data_buff = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0);
 	ZXDH_COMM_CHECK_POINT(p_data_buff);
 
-	p_data_buff_ex = rte_calloc(NULL, 1, ZXDH_DTB_TABLE_DATA_BUFF_SIZE, 0);
-	ZXDH_COMM_CHECK_POINT_MEMORY_FREE(p_data_buff_ex, p_data_buff);
-
 	dtb_one_entry.cmd = entry_cmd;
 	dtb_one_entry.data = entry_data;
 
@@ -1537,16 +2363,17 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id,
 		pentry = delete_entries + entry_index;
 
 		sdt_no = pentry->sdt_no;
+		PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no);
 		zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl);
+		tbl_type = zxdh_np_sdt_tbl_type_get(dev_id, sdt_no);
 		switch (tbl_type) {
 		case ZXDH_SDT_TBLT_ERAM:
 			rc = zxdh_np_dtb_eram_one_entry(dev_id, sdt_no, ZXDH_DTB_ITEM_DELETE,
 				pentry->p_entry_data, &one_dtb_len, &dtb_one_entry);
 			break;
 		default:
-			PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type);
+			PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type);
 			rte_free(p_data_buff);
-			rte_free(p_data_buff_ex);
 			return 1;
 		}
 
@@ -1554,9 +2381,7 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id,
 		dtb_len += one_dtb_len;
 		if (dtb_len > max_size) {
 			rte_free(p_data_buff);
-			rte_free(p_data_buff_ex);
-			PMD_DRV_LOG(ERR, "%s error dtb_len>%u!", __func__,
-				max_size);
+			PMD_DRV_LOG(ERR, "error dtb_len>%u!", max_size);
 			return ZXDH_RC_DTB_DOWN_LEN_INVALID;
 		}
 
@@ -1567,158 +2392,43 @@ zxdh_np_dtb_table_entry_delete(uint32_t dev_id,
 
 	if (dtb_len == 0) {
 		rte_free(p_data_buff);
-		rte_free(p_data_buff_ex);
 		return ZXDH_RC_DTB_DOWN_LEN_INVALID;
 	}
 
 	rc = zxdh_np_dtb_write_down_table_data(dev_id,
 				queue_id,
 				dtb_len * 16,
-				p_data_buff_ex,
+				p_data_buff,
 				&element_id);
 	rte_free(p_data_buff);
-	ZXDH_COMM_CHECK_RC_MEMORY_FREE_NO_ASSERT(rc,
-		"dpp_dtb_write_down_table_data", p_data_buff_ex);
-
-	rte_free(p_data_buff_ex);
-	return 0;
-}
-
-static uint32_t
-zxdh_np_sdt_tbl_data_parser(uint32_t sdt_hig32, uint32_t sdt_low32, void *p_sdt_info)
-{
-	uint32_t tbl_type = 0;
-	uint32_t clutch_en = 0;
-
-	ZXDH_SDTTBL_ERAM_T *p_sdt_eram = NULL;
-	ZXDH_SDTTBL_PORTTBL_T *p_sdt_porttbl = NULL;
-
-	ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_hig32,
-		ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN);
-	ZXDH_COMM_UINT32_GET_BITS(clutch_en, sdt_low32, 0, 1);
-
-	switch (tbl_type) {
-	case ZXDH_SDT_TBLT_ERAM:
-		p_sdt_eram = (ZXDH_SDTTBL_ERAM_T *)p_sdt_info;
-		p_sdt_eram->table_type = tbl_type;
-		p_sdt_eram->eram_clutch_en = clutch_en;
-		break;
-	case ZXDH_SDT_TBLT_PORTTBL:
-		p_sdt_porttbl = (ZXDH_SDTTBL_PORTTBL_T *)p_sdt_info;
-		p_sdt_porttbl->table_type = tbl_type;
-		p_sdt_porttbl->porttbl_clutch_en = clutch_en;
-		break;
-	default:
-		PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type);
-		return 1;
-	}
-
-	return 0;
-}
-
-static uint32_t
-zxdh_np_soft_sdt_tbl_get(uint32_t dev_id, uint32_t sdt_no, void *p_sdt_info)
-{
-	ZXDH_SDT_TBL_DATA_T sdt_tbl = {0};
-	uint32_t rc;
-
-	zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl);
-
-	rc = zxdh_np_sdt_tbl_data_parser(sdt_tbl.data_high32, sdt_tbl.data_low32, p_sdt_info);
-	if (rc != 0)
-		PMD_DRV_LOG(ERR, "dpp sdt [%d] tbl_data_parser error", sdt_no);
-
-	return rc;
-}
-
-static void
-zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index,
-		uint32_t *p_row_index, uint32_t *p_col_index)
-{
-	uint32_t row_index = 0;
-	uint32_t col_index = 0;
-
-	switch (eram_mode) {
-	case ZXDH_ERAM128_TBL_128b:
-		row_index = index;
-		break;
-	case ZXDH_ERAM128_TBL_64b:
-		row_index = (index >> 1);
-		col_index = index & 0x1;
-		break;
-	case ZXDH_ERAM128_TBL_1b:
-		row_index = (index >> 7);
-		col_index = index & 0x7F;
-		break;
-	}
-	*p_row_index = row_index;
-	*p_col_index = col_index;
-}
 
-static uint32_t
-zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no,
-		ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry)
-{
-	uint32_t index = p_dump_eram_entry->index;
-	uint32_t *p_data = p_dump_eram_entry->p_data;
-	ZXDH_SDTTBL_ERAM_T sdt_eram_info = {0};
-	uint32_t temp_data[4] = {0};
-	uint32_t row_index = 0;
-	uint32_t col_index = 0;
-	uint32_t rd_mode;
-	uint32_t rc;
-
-	rc = zxdh_np_soft_sdt_tbl_get(queue_id, sdt_no, &sdt_eram_info);
-	ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get");
-	rd_mode = sdt_eram_info.eram_mode;
-
-	zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index);
-
-	switch (rd_mode) {
-	case ZXDH_ERAM128_TBL_128b:
-		memcpy(p_data, temp_data, (128 / 8));
-		break;
-	case ZXDH_ERAM128_TBL_64b:
-		memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8));
-		break;
-	case ZXDH_ERAM128_TBL_1b:
-		ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data +
-			(3 - col_index / 32)), (col_index % 32), 1);
-		break;
-	}
 	return rc;
 }
-
-int
-zxdh_np_dtb_table_entry_get(uint32_t dev_id,
-		 uint32_t queue_id,
-		 ZXDH_DTB_USER_ENTRY_T *get_entry,
-		 uint32_t srh_mode)
-{
-	ZXDH_SDT_TBL_DATA_T sdt_tbl = {0};
-	uint32_t tbl_type = 0;
-	uint32_t rc = 0;
-	uint32_t sdt_no;
-
-	sdt_no = get_entry->sdt_no;
-	zxdh_np_sdt_tbl_data_get(srh_mode, sdt_no, &sdt_tbl);
-
-	ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32,
-			ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN);
-	switch (tbl_type) {
-	case ZXDH_SDT_TBLT_ERAM:
-		rc = zxdh_np_dtb_eram_data_get(dev_id,
-				queue_id,
-				sdt_no,
-				(ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data);
-		ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get");
+
+static void
+zxdh_np_eram_index_cal(uint32_t eram_mode, uint32_t index,
+		uint32_t *p_row_index, uint32_t *p_col_index)
+{
+	uint32_t row_index = 0;
+	uint32_t col_index = 0;
+
+	switch (eram_mode) {
+	case ZXDH_ERAM128_TBL_128b:
+		row_index = index;
+		break;
+	case ZXDH_ERAM128_TBL_64b:
+		row_index = (index >> 1);
+		col_index = index & 0x1;
+		break;
+	case ZXDH_ERAM128_TBL_1b:
+		row_index = (index >> 7);
+		col_index = index & 0x7F;
 		break;
 	default:
-		PMD_DRV_LOG(ERR, "SDT table_type[ %d ] is invalid!", tbl_type);
-		return 1;
+		break;
 	}
-
-	return 0;
+	*p_row_index = row_index;
+	*p_col_index = col_index;
 }
 
 static void
@@ -1727,10 +2437,10 @@ zxdh_np_stat_cfg_soft_get(uint32_t dev_id,
 {
 	ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_stat_cfg);
 
-	p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg.ddr_base_addr;
-	p_stat_cfg->eram_baddr = g_ppu_stat_cfg.eram_baddr;
-	p_stat_cfg->eram_depth = g_ppu_stat_cfg.eram_depth;
-	p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg.ppu_addr_offset;
+	p_stat_cfg->ddr_base_addr = g_ppu_stat_cfg[dev_id].ddr_base_addr;
+	p_stat_cfg->eram_baddr = g_ppu_stat_cfg[dev_id].eram_baddr;
+	p_stat_cfg->eram_depth = g_ppu_stat_cfg[dev_id].eram_depth;
+	p_stat_cfg->ppu_addr_offset = g_ppu_stat_cfg[dev_id].ppu_addr_offset;
 }
 
 static uint32_t
@@ -1748,12 +2458,12 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id,
 
 	zxdh_np_dtb_queue_enable_get(dev_id, queue_id, &queue_en);
 	if (!queue_en) {
-		PMD_DRV_LOG(ERR, "the queue %d is not enable!", queue_id);
+		PMD_DRV_LOG(ERR, "the queue %u is not enable!", queue_id);
 		return ZXDH_RC_DTB_QUEUE_NOT_ENABLE;
 	}
 
 	if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) {
-		PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id);
+		PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id);
 		return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT;
 	}
 
@@ -1769,6 +2479,11 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id,
 	item_info.cmd_type = ZXDH_DTB_DIR_UP_TYPE;
 	item_info.int_en = int_flag;
 	item_info.data_len = desc_len / 4;
+	item_info.data_hddr =
+	((ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) >> 4) >> 32) & 0xffffffff;
+	item_info.data_laddr =
+		(ZXDH_DTB_TAB_UP_PHY_ADDR_GET(dev_id, queue_id, item_index) >> 4) & 0xffffffff;
+	zxdh_dtb_info_print(dev_id, queue_id, item_index,  &item_info);
 
 	if (zxdh_np_dev_get_dev_type(dev_id) == ZXDH_DEV_TYPE_SIM)
 		return 0;
@@ -1778,6 +2493,33 @@ zxdh_np_dtb_tab_up_info_set(uint32_t dev_id,
 	return rc;
 }
 
+static uint32_t
+zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id,
+					uint32_t queue_id,
+					uint32_t item_index,
+					uint32_t *p_phy_haddr,
+					uint32_t *p_phy_laddr)
+{
+	uint32_t rc = 0;
+	uint64_t addr;
+
+	if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) {
+		PMD_DRV_LOG(ERR, "dtb queue %d is not init.", queue_id);
+		return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT;
+	}
+
+	if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) ==
+		ZXDH_DTB_TAB_UP_USER_ADDR_TYPE)
+		addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index);
+	else
+		addr = ZXDH_DTB_ITEM_ACK_SIZE;
+
+	*p_phy_haddr = (addr >> 32) & 0xffffffff;
+	*p_phy_laddr = addr & 0xffffffff;
+
+	return rc;
+}
+
 static uint32_t
 zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id,
 		uint32_t queue_id,
@@ -1799,8 +2541,8 @@ zxdh_np_dtb_write_dump_desc_info(uint32_t dev_id,
 				desc_len,
 				p_dump_info);
 	if (rc != 0) {
-		PMD_DRV_LOG(ERR, "the queue %d element id %d dump"
-			" info set failed!", queue_id, queue_element_id);
+		PMD_DRV_LOG(ERR, "queue %u element %u dump info set failed!",
+			queue_id, queue_element_id);
 		zxdh_np_dtb_item_ack_wr(dev_id, queue_id, ZXDH_DTB_DIR_UP_TYPE,
 			queue_element_id, 0, ZXDH_DTB_TAB_ACK_UNUSED_MASK);
 	}
@@ -1819,7 +2561,7 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id,
 	uint32_t i;
 
 	if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) {
-		PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id);
+		PMD_DRV_LOG(ERR, "dtb queue %u is not init", queue_id);
 		return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT;
 	}
 
@@ -1849,37 +2591,9 @@ zxdh_np_dtb_tab_up_free_item_get(uint32_t dev_id,
 
 	*p_item_index = item_index;
 
-
 	return 0;
 }
 
-static uint32_t
-zxdh_np_dtb_tab_up_item_addr_get(uint32_t dev_id,
-					uint32_t queue_id,
-					uint32_t item_index,
-					uint32_t *p_phy_haddr,
-					uint32_t *p_phy_laddr)
-{
-	uint32_t rc = 0;
-	uint64_t addr;
-
-	if (ZXDH_DTB_QUEUE_INIT_FLAG_GET(dev_id, queue_id) == 0) {
-		PMD_DRV_LOG(ERR, "dtb queue %d is not init", queue_id);
-		return ZXDH_RC_DTB_QUEUE_IS_NOT_INIT;
-	}
-
-	if (ZXDH_DTB_TAB_UP_USER_PHY_ADDR_FLAG_GET(dev_id, queue_id, item_index) ==
-		ZXDH_DTB_TAB_UP_USER_ADDR_TYPE)
-		addr = ZXDH_DTB_TAB_UP_USER_PHY_ADDR_GET(dev_id, queue_id, item_index);
-	else
-		addr = ZXDH_DTB_ITEM_ACK_SIZE;
-
-	*p_phy_haddr = (addr >> 32) & 0xffffffff;
-	*p_phy_laddr = addr & 0xffffffff;
-
-	return rc;
-}
-
 static uint32_t
 zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id,
 		uint32_t queue_id,
@@ -1898,7 +2612,7 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id,
 
 	rc = zxdh_np_dtb_tab_up_free_item_get(dev_id, queue_id, &queue_item_index);
 	if (rc != 0) {
-		PMD_DRV_LOG(ERR, "dpp_dtb_tab_up_free_item_get failed = %d!", base_addr);
+		PMD_DRV_LOG(ERR, "dpp_dtb_tab_up_free_item_get failed = %u!", base_addr);
 		return ZXDH_RC_DTB_QUEUE_ITEM_SW_EMPTY;
 	}
 
@@ -1918,6 +2632,103 @@ zxdh_np_dtb_se_smmu0_dma_dump(uint32_t dev_id,
 	return rc;
 }
 
+static uint32_t
+zxdh_np_dtb_eram_data_get(uint32_t dev_id, uint32_t queue_id, uint32_t sdt_no,
+		ZXDH_DTB_ERAM_ENTRY_INFO_T *p_dump_eram_entry)
+{
+	uint32_t index = p_dump_eram_entry->index;
+	uint32_t *p_data = p_dump_eram_entry->p_data;
+	ZXDH_SDT_TBL_ERAM_T sdt_eram_info = {0};
+	uint32_t temp_data[4] = {0};
+	uint32_t row_index = 0;
+	uint32_t col_index = 0;
+	uint32_t rd_mode;
+	uint32_t rc;
+	uint32_t eram_dump_base_addr = 0;
+	uint32_t eram_base_addr = 0;
+	uint32_t element_id = 0;
+
+	PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no);
+	rc = zxdh_np_soft_sdt_tbl_get(dev_id, sdt_no, &sdt_eram_info);
+	ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "dpp_soft_sdt_tbl_get");
+	eram_base_addr = sdt_eram_info.eram_base_addr;
+	rd_mode = sdt_eram_info.eram_mode;
+
+	zxdh_np_eram_index_cal(rd_mode, index, &row_index, &col_index);
+
+	eram_dump_base_addr = eram_base_addr + row_index;
+
+	rc = zxdh_np_dtb_se_smmu0_dma_dump(dev_id,
+								queue_id,
+								eram_dump_base_addr,
+								1,
+								temp_data,
+								&element_id);
+	ZXDH_COMM_CHECK_DEV_RC(dev_id, rc, "zxdh_np_dtb_se_smmu0_dma_dump");
+
+	switch (rd_mode) {
+	case ZXDH_ERAM128_TBL_128b:
+		memcpy(p_data, temp_data, (128 / 8));
+		break;
+	case ZXDH_ERAM128_TBL_64b:
+		memcpy(p_data, temp_data + ((1 - col_index) << 1), (64 / 8));
+		break;
+	case ZXDH_ERAM128_TBL_1b:
+		ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data +
+			(3 - col_index / 32)), (col_index % 32), 1);
+		break;
+	default:
+		break;
+	}
+
+	PMD_DRV_LOG(DEBUG, "[eram_dump]std no:0x%x, index:0x%x, base addr:0x%x",
+				sdt_no, p_dump_eram_entry->index, eram_dump_base_addr);
+	if (rd_mode == ZXDH_ERAM128_TBL_128b)
+		PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x 0x%08x 0x%08x]",
+		p_dump_eram_entry->p_data[0], p_dump_eram_entry->p_data[1],
+		p_dump_eram_entry->p_data[2], p_dump_eram_entry->p_data[3]);
+	else if (rd_mode == ZXDH_ERAM128_TBL_64b)
+		PMD_DRV_LOG(DEBUG, "value[0x%08x 0x%08x]",
+		p_dump_eram_entry->p_data[0], p_dump_eram_entry->p_data[1]);
+
+	return rc;
+}
+
+int
+zxdh_np_dtb_table_entry_get(uint32_t dev_id,
+		 uint32_t queue_id,
+		 ZXDH_DTB_USER_ENTRY_T *get_entry,
+		 uint32_t srh_mode)
+{
+	ZXDH_SDT_TBL_DATA_T sdt_tbl = {0};
+	uint32_t tbl_type = 0;
+	uint32_t rc;
+	uint32_t sdt_no;
+
+	sdt_no = get_entry->sdt_no;
+	PMD_DRV_LOG(DEBUG, "sdt_no:%u", sdt_no);
+	PMD_DRV_LOG(DEBUG, "srh_mode:%u", srh_mode);
+
+	zxdh_np_sdt_tbl_data_get(dev_id, sdt_no, &sdt_tbl);
+
+	ZXDH_COMM_UINT32_GET_BITS(tbl_type, sdt_tbl.data_high32,
+			ZXDH_SDT_H_TBL_TYPE_BT_POS, ZXDH_SDT_H_TBL_TYPE_BT_LEN);
+	switch (tbl_type) {
+	case ZXDH_SDT_TBLT_ERAM:
+		rc = zxdh_np_dtb_eram_data_get(dev_id,
+				queue_id,
+				sdt_no,
+				(ZXDH_DTB_ERAM_ENTRY_INFO_T *)get_entry->p_entry_data);
+		ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "dpp_dtb_eram_data_get");
+		break;
+	default:
+		PMD_DRV_LOG(ERR, "SDT table_type[ %u ] is invalid!", tbl_type);
+		return 1;
+	}
+
+	return 0;
+}
+
 static uint32_t
 zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id,
 		uint32_t queue_id,
@@ -1945,6 +2756,8 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id,
 		row_index = (index >> 7);
 		col_index = index & 0x7F;
 		break;
+	default:
+		break;
 	}
 
 	eram_dump_base_addr = base_addr + row_index;
@@ -1967,6 +2780,8 @@ zxdh_np_dtb_se_smmu0_ind_read(uint32_t dev_id,
 		ZXDH_COMM_UINT32_GET_BITS(p_data[0], *(temp_data +
 			(3 - col_index / 32)), (col_index % 32), 1);
 		break;
+	default:
+		break;
 	}
 
 	return rc;
@@ -2035,6 +2850,32 @@ zxdh_np_dtb_stats_get(uint32_t dev_id,
 	return rc;
 }
 
+int
+zxdh_np_host_init(uint32_t dev_id,
+		ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl)
+{
+	ZXDH_SYS_INIT_CTRL_T sys_init_ctrl = {0};
+	uint32_t rc;
+	uint64_t agent_addr;
+
+	ZXDH_COMM_CHECK_DEV_POINT(dev_id, p_dev_init_ctrl);
+
+	sys_init_ctrl.flags = (ZXDH_DEV_ACCESS_TYPE_PCIE << 0) | (ZXDH_DEV_AGENT_ENABLE << 10);
+	sys_init_ctrl.pcie_vir_baddr = zxdh_np_addr_calc(p_dev_init_ctrl->pcie_vir_addr,
+		p_dev_init_ctrl->np_bar_offset);
+	sys_init_ctrl.device_type = ZXDH_DEV_TYPE_CHIP;
+
+	rc = zxdh_np_base_soft_init(dev_id, &sys_init_ctrl);
+	ZXDH_COMM_CHECK_RC_NO_ASSERT(rc, "zxdh_base_soft_init");
+
+	zxdh_np_dev_vport_set(dev_id, p_dev_init_ctrl->vport);
+
+	agent_addr = ZXDH_PCIE_AGENT_ADDR_OFFSET + p_dev_init_ctrl->pcie_vir_addr;
+	zxdh_np_dev_agent_addr_set(dev_id, agent_addr);
+
+	return 0;
+}
+
 static uint32_t
 zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos)
 {
@@ -2047,7 +2888,7 @@ zxdh_np_se_done_status_check(uint32_t dev_id, uint32_t reg_no, uint32_t pos)
 	while (!done_flag) {
 		rc = zxdh_np_reg_read(dev_id, reg_no, 0, 0, &data);
 		if (rc != 0) {
-			PMD_DRV_LOG(ERR, " [ErrorCode:0x%x] !-- zxdh_np_reg_read Fail!", rc);
+			PMD_DRV_LOG(ERR, "reg_read fail!");
 			return rc;
 		}
 
@@ -2073,7 +2914,7 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id,
 						uint32_t rd_clr_mode,
 						uint32_t *p_data)
 {
-	uint32_t rc = 0;
+	uint32_t rc = ZXDH_OK;
 	uint32_t i = 0;
 	uint32_t row_index = 0;
 	uint32_t col_index = 0;
@@ -2082,6 +2923,10 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id,
 	ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T cpu_ind_cmd = {0};
 
 	rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR, 0);
+	if (rc != ZXDH_OK) {
+		PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc);
+		return ZXDH_ERR;
+	}
 
 	if (rd_clr_mode == ZXDH_RD_MODE_HOLD) {
 		cpu_ind_cmd.cpu_ind_rw = ZXDH_SE_OPR_RD;
@@ -2090,42 +2935,42 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id,
 
 		switch (rd_mode) {
 		case ZXDH_ERAM128_OPR_128b:
-			if ((0xFFFFFFFF - (base_addr)) < (index))
+			if ((0xFFFFFFFF - (base_addr)) < (index)) {
+				PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index);
 				return ZXDH_PAR_CHK_INVALID_INDEX;
-
+			}
 			if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
-				PMD_DRV_LOG(ERR, "%s : index out of range !", __func__);
-				return -1;
+				PMD_DRV_LOG(ERR, "index out of range!");
+				return ZXDH_ERR;
 			}
-
 			row_index = (index << 7) & ZXDH_ERAM128_BADDR_MASK;
 			break;
 		case ZXDH_ERAM128_OPR_64b:
 			if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
-				PMD_DRV_LOG(ERR, "%s : index out of range !", __func__);
-				return -1;
+				PMD_DRV_LOG(ERR, "index out of range!");
+				return ZXDH_ERR;
 			}
-
 			row_index = (index << 6) & ZXDH_ERAM128_BADDR_MASK;
 			col_index = index & 0x1;
 			break;
 		case ZXDH_ERAM128_OPR_32b:
 			if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
-				PMD_DRV_LOG(ERR, "%s : index out of range !", __func__);
-				return -1;
+				PMD_DRV_LOG(ERR, "index out of range!");
+				return ZXDH_ERR;
 			}
-
 			row_index = (index << 5) & ZXDH_ERAM128_BADDR_MASK;
 			col_index = index & 0x3;
 			break;
 		case ZXDH_ERAM128_OPR_1b:
 			if ((base_addr + (index >> 7)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
-				PMD_DRV_LOG(ERR, "%s : index out of range !", __func__);
-				return -1;
+				PMD_DRV_LOG(ERR, "index out of range!");
+				return ZXDH_ERR;
 			}
 			row_index = index & ZXDH_ERAM128_BADDR_MASK;
 			col_index = index & 0x7F;
 			break;
+		default:
+			break;
 		}
 
 		cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index;
@@ -2136,56 +2981,69 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id,
 		switch (rd_mode) {
 		case ZXDH_ERAM128_OPR_128b:
 			if ((0xFFFFFFFF - (base_addr)) < (index)) {
-				PMD_DRV_LOG(ERR, "%s : index 0x%x is invalid!", __func__, index);
+				PMD_DRV_LOG(ERR, "index 0x%x is invalid!", index);
 				return ZXDH_PAR_CHK_INVALID_INDEX;
 			}
 			if (base_addr + index > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
-				PMD_DRV_LOG(ERR, "%s : index out of range !", __func__);
-				return -1;
+				PMD_DRV_LOG(ERR, "index out of range!");
+				return ZXDH_ERR;
 			}
 			row_index = (index << 7);
 			cpu_ind_cmd.cpu_req_mode = ZXDH_ERAM128_OPR_128b;
 			break;
 		case ZXDH_ERAM128_OPR_64b:
 			if ((base_addr + (index >> 1)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
-				PMD_DRV_LOG(ERR, "%s : index out of range !", __func__);
-				return -1;
+				PMD_DRV_LOG(ERR, "index out of range!");
+				return ZXDH_ERR;
 			}
-
 			row_index = (index << 6);
 			cpu_ind_cmd.cpu_req_mode = 2;
 			break;
 		case ZXDH_ERAM128_OPR_32b:
 			if ((base_addr + (index >> 2)) > ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL - 1) {
-				PMD_DRV_LOG(ERR, "%s : index out of range !", __func__);
-				return -1;
+				PMD_DRV_LOG(ERR, "index out of range!");
+				return ZXDH_ERR;
 			}
 			row_index = (index << 5);
 			cpu_ind_cmd.cpu_req_mode = 1;
 			break;
 		case ZXDH_ERAM128_OPR_1b:
-			PMD_DRV_LOG(ERR, "rd_clr_mode[%d] or rd_mode[%d] error! ",
-				rd_clr_mode, rd_mode);
-			return -1;
+			PMD_DRV_LOG(ERR, "rd_clr_mode[%u] or rd_mode[%u] error!",
+			rd_clr_mode, rd_mode);
+			return ZXDH_ERR;
+		default:
+			break;
 		}
 		cpu_ind_cmd.cpu_ind_addr = ((base_addr << 7) & ZXDH_ERAM128_BADDR_MASK) + row_index;
 	}
 
 	rc = zxdh_np_reg_write(dev_id,
-						ZXDH_SMMU0_SMMU0_CPU_IND_CMDR,
-						0,
-						0,
-						&cpu_ind_cmd);
+			ZXDH_SMMU0_SMMU0_CPU_IND_CMDR,
+			0,
+			0,
+			&cpu_ind_cmd);
+	if (rc != ZXDH_OK) {
+		PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc);
+		return ZXDH_ERR;
+	}
 
-	rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_RD_CPU_IND_DONER, 0);
+	rc = zxdh_np_se_done_status_check(dev_id, ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER, 0);
+	if (rc != ZXDH_OK) {
+		PMD_DRV_LOG(ERR, "se done status check failed, rc=0x%x.", rc);
+		return ZXDH_ERR;
+	}
 
 	p_temp_data = temp_data;
 	for (i = 0; i < 4; i++) {
 		rc = zxdh_np_reg_read(dev_id,
-							ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i,
-							0,
-							0,
-							p_temp_data + 3 - i);
+			ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R + i,
+			0,
+			0,
+			p_temp_data + 3 - i);
+		if (rc != ZXDH_OK) {
+			PMD_DRV_LOG(ERR, "zxdh_np_reg_write failed, rc=0x%x.", rc);
+			return ZXDH_ERR;
+		}
 	}
 
 	if (rd_clr_mode == ZXDH_RD_MODE_HOLD) {
@@ -2203,6 +3061,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id,
 			ZXDH_COMM_UINT32_GET_BITS(p_data[0],
 				*(p_temp_data + (3 - col_index / 32)), (col_index % 32), 1);
 			break;
+		default:
+			break;
 		}
 	} else {
 		switch (rd_mode) {
@@ -2215,6 +3075,8 @@ zxdh_np_se_smmu0_ind_read(uint32_t dev_id,
 		case ZXDH_ERAM128_OPR_32b:
 			memcpy(p_data, p_temp_data, (64 / 8));
 			break;
+		default:
+			break;
 		}
 	}
 
@@ -2266,70 +3128,18 @@ zxdh_np_stat_ppu_cnt_get_ex(uint32_t dev_id,
 }
 
 static uint32_t
-zxdh_np_agent_channel_sync_send(ZXDH_AGENT_CHANNEL_MSG_T *p_msg,
-				uint32_t *p_data,
-				uint32_t rep_len)
-{
-	uint32_t ret = 0;
-	uint32_t vport = 0;
-	struct zxdh_pci_bar_msg in = {0};
-	struct zxdh_msg_recviver_mem result = {0};
-	uint32_t *recv_buffer;
-	uint8_t *reply_ptr = NULL;
-	uint16_t reply_msg_len = 0;
-	uint64_t agent_addr = 0;
-
-	if (ZXDH_IS_PF(vport))
-		in.src = ZXDH_MSG_CHAN_END_PF;
-	else
-		in.src = ZXDH_MSG_CHAN_END_VF;
-
-	in.virt_addr = agent_addr;
-	in.payload_addr = p_msg->msg;
-	in.payload_len = p_msg->msg_len;
-	in.dst = ZXDH_MSG_CHAN_END_RISC;
-	in.module_id = ZXDH_BAR_MDOULE_NPSDK;
-
-	recv_buffer = (uint32_t *)rte_zmalloc(NULL, rep_len + ZXDH_CHANNEL_REPS_LEN, 0);
-	if (recv_buffer == NULL) {
-		PMD_DRV_LOG(ERR, "%s point null!", __func__);
-		return ZXDH_PAR_CHK_POINT_NULL;
-	}
-
-	result.buffer_len = rep_len + ZXDH_CHANNEL_REPS_LEN;
-	result.recv_buffer = recv_buffer;
-
-	ret = zxdh_bar_chan_sync_msg_send(&in, &result);
-	if (ret == ZXDH_BAR_MSG_OK) {
-		reply_ptr = (uint8_t *)(result.recv_buffer);
-		if (*reply_ptr == 0XFF) {
-			reply_msg_len = *(uint16_t *)(reply_ptr + 1);
-			memcpy(p_data, reply_ptr + 4,
-				((reply_msg_len > rep_len) ? rep_len : reply_msg_len));
-		} else {
-			PMD_DRV_LOG(ERR, "Message not replied");
-		}
-	} else {
-		PMD_DRV_LOG(ERR, "Error[0x%x], %s failed!", ret, __func__);
-	}
-
-	rte_free(recv_buffer);
-	return ret;
-}
-
-static uint32_t
-zxdh_np_agent_channel_plcr_sync_send(ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg,
+zxdh_np_agent_channel_plcr_sync_send(uint32_t dev_id, ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg,
 		uint32_t *p_data, uint32_t rep_len)
 {
 	uint32_t ret = 0;
-	ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {0};
+	ZXDH_AGENT_CHANNEL_MSG_T agent_msg = {
+		.msg = (void *)&p_msg,
+		.msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T),
+	};
 
-	agent_msg.msg = (void *)p_msg;
-	agent_msg.msg_len = sizeof(ZXDH_AGENT_CHANNEL_PLCR_MSG_T);
-
-	ret = zxdh_np_agent_channel_sync_send(&agent_msg, p_data, rep_len);
+	ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, p_data, rep_len);
 	if (ret != 0)	{
-		PMD_DRV_LOG(ERR, "%s: agent_channel_sync_send failed.", __func__);
+		PMD_DRV_LOG(ERR, "agent_channel_sync_send failed.");
 		return 1;
 	}
 
@@ -2337,25 +3147,25 @@ zxdh_np_agent_channel_plcr_sync_send(ZXDH_AGENT_CHANNEL_PLCR_MSG_T *p_msg,
 }
 
 static uint32_t
-zxdh_np_agent_channel_plcr_profileid_request(uint32_t vport,
+zxdh_np_agent_channel_plcr_profileid_request(uint32_t dev_id, uint32_t vport,
 	uint32_t car_type, uint32_t *p_profileid)
 {
 	uint32_t ret = 0;
 	uint32_t resp_buffer[2] = {0};
 
-	ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0};
-
-	msgcfg.dev_id = 0;
-	msgcfg.type = ZXDH_PLCR_MSG;
-	msgcfg.oper = ZXDH_PROFILEID_REQUEST;
-	msgcfg.vport = vport;
-	msgcfg.car_type = car_type;
-	msgcfg.profile_id = 0xFFFF;
+	ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {
+		.dev_id = 0,
+		.type = ZXDH_PLCR_MSG,
+		.oper = ZXDH_PROFILEID_REQUEST,
+		.vport = vport,
+		.car_type = car_type,
+		.profile_id = 0xFFFF,
+	};
 
-	ret = zxdh_np_agent_channel_plcr_sync_send(&msgcfg,
+	ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg,
 		resp_buffer, sizeof(resp_buffer));
 	if (ret != 0)	{
-		PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__);
+		PMD_DRV_LOG(ERR, "agent_channel_plcr_sync_send failed.");
 		return 1;
 	}
 
@@ -2365,7 +3175,8 @@ zxdh_np_agent_channel_plcr_profileid_request(uint32_t vport,
 }
 
 static uint32_t
-zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type,
+zxdh_np_agent_channel_plcr_car_rate(uint32_t dev_id,
+		uint32_t car_type,
 		uint32_t pkt_sign,
 		uint32_t profile_id __rte_unused,
 		void *p_car_profile_cfg)
@@ -2395,9 +3206,9 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type,
 		agent_msg.msg = (void *)&msgpktcfg;
 		agent_msg.msg_len = sizeof(ZXDH_AGENT_CAR_PKT_PROFILE_MSG_T);
 
-		ret = zxdh_np_agent_channel_sync_send(&agent_msg, resp_buffer, resp_len);
+		ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len);
 		if (ret != 0)	{
-			PMD_DRV_LOG(ERR, "%s: stat_car_a_type failed.", __func__);
+			PMD_DRV_LOG(ERR, "stat_car_a_type failed.");
 			return 1;
 		}
 
@@ -2429,9 +3240,9 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type,
 		agent_msg.msg = (void *)&msgcfg;
 		agent_msg.msg_len = sizeof(ZXDH_AGENT_CAR_PROFILE_MSG_T);
 
-		ret = zxdh_np_agent_channel_sync_send(&agent_msg, resp_buffer, resp_len);
+		ret = zxdh_np_agent_channel_sync_send(dev_id, &agent_msg, resp_buffer, resp_len);
 		if (ret != 0)	{
-			PMD_DRV_LOG(ERR, "%s: stat_car_b_type failed.", __func__);
+			PMD_DRV_LOG(ERR, "stat_car_b_type failed.");
 			return 1;
 		}
 
@@ -2442,25 +3253,25 @@ zxdh_np_agent_channel_plcr_car_rate(uint32_t car_type,
 }
 
 static uint32_t
-zxdh_np_agent_channel_plcr_profileid_release(uint32_t vport,
+zxdh_np_agent_channel_plcr_profileid_release(uint32_t dev_id, uint32_t vport,
 		uint32_t car_type __rte_unused,
 		uint32_t profileid)
 {
 	uint32_t ret = 0;
 	uint32_t resp_buffer[2] = {0};
 
-	ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {0};
-
-	msgcfg.dev_id = 0;
-	msgcfg.type = ZXDH_PLCR_MSG;
-	msgcfg.oper = ZXDH_PROFILEID_RELEASE;
-	msgcfg.vport = vport;
-	msgcfg.profile_id = profileid;
+	ZXDH_AGENT_CHANNEL_PLCR_MSG_T msgcfg = {
+		.dev_id = 0,
+		.type = ZXDH_PLCR_MSG,
+		.oper = ZXDH_PROFILEID_RELEASE,
+		.vport = vport,
+		.profile_id = profileid,
+	};
 
-	ret = zxdh_np_agent_channel_plcr_sync_send(&msgcfg,
+	ret = zxdh_np_agent_channel_plcr_sync_send(dev_id, &msgcfg,
 		resp_buffer, sizeof(resp_buffer));
 	if (ret != 0)	{
-		PMD_DRV_LOG(ERR, "%s: agent_channel_plcr_sync_send failed.", __func__);
+		PMD_DRV_LOG(ERR, "agent_channel_plcr_sync_send failed.");
 		return 1;
 	}
 
@@ -2478,11 +3289,12 @@ zxdh_np_stat_cara_queue_cfg_set(uint32_t dev_id,
 {
 	uint32_t rc = 0;
 
-	ZXDH_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = {0};
+	ZXDH_STAT_CAR0_CARA_QUEUE_RAM0_159_0_T queue_cfg = {
+		.cara_drop = drop_flag,
+		.cara_plcr_en = plcr_en,
+		.cara_profile_id = profile_id,
+	};
 
-	queue_cfg.cara_drop = drop_flag;
-	queue_cfg.cara_plcr_en = plcr_en;
-	queue_cfg.cara_profile_id = profile_id;
 	rc = zxdh_np_reg_write(dev_id,
 				ZXDH_STAT_CAR0_CARA_QUEUE_RAM0,
 				0,
@@ -2502,11 +3314,11 @@ zxdh_np_stat_carb_queue_cfg_set(uint32_t dev_id,
 {
 	uint32_t rc = 0;
 
-	ZXDH_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = {0};
-
-	queue_cfg.carb_drop = drop_flag;
-	queue_cfg.carb_plcr_en = plcr_en;
-	queue_cfg.carb_profile_id = profile_id;
+	ZXDH_STAT_CAR0_CARB_QUEUE_RAM0_159_0_T queue_cfg = {
+		.carb_drop = drop_flag,
+		.carb_plcr_en = plcr_en,
+		.carb_profile_id = profile_id,
+	};
 
 	rc = zxdh_np_reg_write(dev_id,
 				ZXDH_STAT_CAR0_CARB_QUEUE_RAM0,
@@ -2527,10 +3339,11 @@ zxdh_np_stat_carc_queue_cfg_set(uint32_t dev_id,
 {
 	uint32_t rc = 0;
 
-	ZXDH_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = {0};
-	queue_cfg.carc_drop = drop_flag;
-	queue_cfg.carc_plcr_en = plcr_en;
-	queue_cfg.carc_profile_id = profile_id;
+	ZXDH_STAT_CAR0_CARC_QUEUE_RAM0_159_0_T queue_cfg = {
+		.carc_drop = drop_flag,
+		.carc_plcr_en = plcr_en,
+		.carc_profile_id = profile_id,
+	};
 
 	rc = zxdh_np_reg_write(dev_id,
 						ZXDH_STAT_CAR0_CARC_QUEUE_RAM0,
@@ -2553,12 +3366,12 @@ zxdh_np_car_profile_id_add(uint32_t vport_id,
 	uint32_t profile_id_l = 0;
 	uint64_t temp_profile_id = 0;
 
-	profile_id = (uint32_t *)rte_zmalloc(NULL, ZXDH_G_PROFILE_ID_LEN, 0);
+	profile_id = rte_zmalloc(NULL, ZXDH_G_PROFILE_ID_LEN, 0);
 	if (profile_id == NULL) {
-		PMD_DRV_LOG(ERR, "%s: profile_id point null!", __func__);
+		PMD_DRV_LOG(ERR, "profile_id point null!");
 		return ZXDH_PAR_CHK_POINT_NULL;
 	}
-	ret = zxdh_np_agent_channel_plcr_profileid_request(vport_id, flags, profile_id);
+	ret = zxdh_np_agent_channel_plcr_profileid_request(0, vport_id, flags, profile_id);
 
 	profile_id_h = *(profile_id + 1);
 	profile_id_l = *profile_id;
@@ -2566,7 +3379,7 @@ zxdh_np_car_profile_id_add(uint32_t vport_id,
 
 	temp_profile_id = (((uint64_t)profile_id_l) << 32) | ((uint64_t)profile_id_h);
 	if (0 != (uint32_t)(temp_profile_id >> 56)) {
-		PMD_DRV_LOG(ERR, "%s: profile_id is overflow!", __func__);
+		PMD_DRV_LOG(ERR, "profile_id is overflow!");
 		return 1;
 	}
 
@@ -2583,11 +3396,12 @@ zxdh_np_car_profile_cfg_set(uint32_t vport_id __rte_unused,
 		void *p_car_profile_cfg)
 {
 	uint32_t ret = 0;
+	uint32_t dev_id = 0;
 
-	ret = zxdh_np_agent_channel_plcr_car_rate(car_type,
+	ret = zxdh_np_agent_channel_plcr_car_rate(dev_id, car_type,
 		pkt_sign, profile_id, p_car_profile_cfg);
 	if (ret != 0) {
-		PMD_DRV_LOG(ERR, "%s: plcr_car_rate set failed!", __func__);
+		PMD_DRV_LOG(ERR, "plcr_car_rate set failed!");
 		return 1;
 	}
 
@@ -2599,13 +3413,12 @@ zxdh_np_car_profile_id_delete(uint32_t vport_id,
 	uint32_t flags, uint64_t profile_id)
 {
 	uint32_t ret = 0;
-	uint32_t profileid = 0;
-
-	profileid = profile_id & 0xFFFF;
+	uint32_t dev_id = 0;
+	uint32_t profileid = profile_id & 0xFFFF;
 
-	ret = zxdh_np_agent_channel_plcr_profileid_release(vport_id, flags, profileid);
+	ret = zxdh_np_agent_channel_plcr_profileid_release(dev_id, vport_id, flags, profileid);
 	if (ret != 0) {
-		PMD_DRV_LOG(ERR, "%s: plcr profiled id release failed!", __func__);
+		PMD_DRV_LOG(ERR, "plcr profiled id release failed!");
 		return 1;
 	}
 
@@ -2624,32 +3437,32 @@ zxdh_np_stat_car_queue_cfg_set(uint32_t dev_id,
 
 	if (car_type == ZXDH_STAT_CAR_A_TYPE) {
 		if (flow_id > ZXDH_CAR_A_FLOW_ID_MAX) {
-			PMD_DRV_LOG(ERR, "%s: stat car a type flow_id invalid!", __func__);
+			PMD_DRV_LOG(ERR, "stat car a type flow_id invalid!");
 			return ZXDH_PAR_CHK_INVALID_INDEX;
 		}
 
 		if (profile_id > ZXDH_CAR_A_PROFILE_ID_MAX) {
-			PMD_DRV_LOG(ERR, "%s: stat car a type profile_id invalid!", __func__);
+			PMD_DRV_LOG(ERR, "stat car a type profile_id invalid!");
 			return ZXDH_PAR_CHK_INVALID_INDEX;
 		}
 	} else if (car_type == ZXDH_STAT_CAR_B_TYPE) {
 		if (flow_id > ZXDH_CAR_B_FLOW_ID_MAX) {
-			PMD_DRV_LOG(ERR, "%s: stat car b type flow_id invalid!", __func__);
+			PMD_DRV_LOG(ERR, "stat car b type flow_id invalid!");
 			return ZXDH_PAR_CHK_INVALID_INDEX;
 		}
 
 		if (profile_id > ZXDH_CAR_B_PROFILE_ID_MAX) {
-			PMD_DRV_LOG(ERR, "%s: stat car b type profile_id invalid!", __func__);
+			PMD_DRV_LOG(ERR, "stat car b type profile_id invalid!");
 			return ZXDH_PAR_CHK_INVALID_INDEX;
 		}
 	} else {
 		if (flow_id > ZXDH_CAR_C_FLOW_ID_MAX) {
-			PMD_DRV_LOG(ERR, "%s: stat car c type flow_id invalid!", __func__);
+			PMD_DRV_LOG(ERR, "stat car c type flow_id invalid!");
 			return ZXDH_PAR_CHK_INVALID_INDEX;
 		}
 
 		if (profile_id > ZXDH_CAR_C_PROFILE_ID_MAX) {
-			PMD_DRV_LOG(ERR, "%s: stat car c type profile_id invalid!", __func__);
+			PMD_DRV_LOG(ERR, "stat car c type profile_id invalid!");
 			return ZXDH_PAR_CHK_INVALID_INDEX;
 		}
 	}
diff --git a/drivers/net/zxdh/zxdh_np.h b/drivers/net/zxdh/zxdh_np.h
index 7ff5c34c73..6d2c7aa976 100644
--- a/drivers/net/zxdh/zxdh_np.h
+++ b/drivers/net/zxdh/zxdh_np.h
@@ -6,14 +6,16 @@
 #define ZXDH_NP_H
 
 #include <stdint.h>
+#include <rte_spinlock.h>
 
+#define ZXDH_OK                               (0)
+#define ZXDH_ERR                              (1)
 #define ZXDH_DISABLE                          (0)
 #define ZXDH_ENABLE                           (1)
 #define ZXDH_PORT_NAME_MAX                    (32)
 #define ZXDH_DEV_CHANNEL_MAX                  (2)
 #define ZXDH_DEV_SDT_ID_MAX                   (256U)
 
-#define ZXDH_RD_CNT_MAX                       (128)
 
 /*DTB*/
 #define ZXDH_DTB_QUEUE_ITEM_NUM_MAX           (32)
@@ -54,11 +56,23 @@
 #define ZXDH_INIT_FLAG_TM_IMEM_FLAG     (1 << 9)
 #define ZXDH_INIT_FLAG_AGENT_FLAG       (1 << 10)
 
+#define ZXDH_REG_NUL_ARRAY              (0 << 0)
+#define ZXDH_REG_UNI_ARRAY              (1 << 0)
+#define ZXDH_REG_BIN_ARRAY              (1 << 1)
+#define ZXDH_REG_FLAG_INDIRECT          (1 << 0)
+#define ZXDH_REG_FLAG_DIRECT            (0 << 0)
+#define ZXDH_FIELD_FLAG_RO              (1 << 0)
+#define ZXDH_FIELD_FLAG_RW              (1 << 1)
+
+#define ZXDH_SYS_NP_BASE_ADDR0          (0x00000000)
+#define ZXDH_SYS_NP_BASE_ADDR1          (0x02000000)
+
 #define ZXDH_ACL_TBL_ID_MIN             (0)
 #define ZXDH_ACL_TBL_ID_MAX             (7)
 #define ZXDH_ACL_TBL_ID_NUM             (8U)
 #define ZXDH_ACL_BLOCK_NUM              (8U)
 
+#define ZXDH_RD_CNT_MAX                          (100)
 #define ZXDH_SMMU0_READ_REG_MAX_NUM              (4)
 
 #define ZXDH_DTB_ITEM_ACK_SIZE                   (16)
@@ -98,6 +112,57 @@
 #define ZXDH_SE_SMMU0_ERAM_ADDR_NUM_TOTAL  \
 		(ZXDH_SE_SMMU0_ERAM_BLOCK_NUM * ZXDH_SE_SMMU0_ERAM_ADDR_NUM_PER_BLOCK)
 
+#define ZXDH_SDT_CFG_LEN                        (2)
+#define ZXDH_SDT_VALID                          (1)
+#define ZXDH_SDT_INVALID                        (0)
+#define ZXDH_SDT_OPER_ADD                       (0)
+#define ZXDH_SDT_H_TBL_TYPE_BT_POS              (29)
+#define ZXDH_SDT_H_TBL_TYPE_BT_LEN              (3)
+#define ZXDH_SDT_H_ERAM_MODE_BT_POS             (26)
+#define ZXDH_SDT_H_ERAM_MODE_BT_LEN             (3)
+#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_POS        (7)
+#define ZXDH_SDT_H_ERAM_BASE_ADDR_BT_LEN        (19)
+#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_POS      (1)
+#define ZXDH_SDT_L_ERAM_TABLE_DEPTH_BT_LEN      (22)
+#define ZXDH_SDT_H_HASH_ID_BT_POS               (27)
+#define ZXDH_SDT_H_HASH_ID_BT_LEN               (2)
+#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_POS      (25)
+#define ZXDH_SDT_H_HASH_TABLE_WIDTH_BT_LEN      (2)
+#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_POS         (19)
+#define ZXDH_SDT_H_HASH_KEY_SIZE_BT_LEN         (6)
+#define ZXDH_SDT_H_HASH_TABLE_ID_BT_POS         (14)
+#define ZXDH_SDT_H_HASH_TABLE_ID_BT_LEN         (5)
+#define ZXDH_SDT_H_LEARN_EN_BT_POS              (13)
+#define ZXDH_SDT_H_LEARN_EN_BT_LEN              (1)
+#define ZXDH_SDT_H_KEEP_ALIVE_BT_POS            (12)
+#define ZXDH_SDT_H_KEEP_ALIVE_BT_LEN            (1)
+#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_POS      (0)
+#define ZXDH_SDT_H_KEEP_ALIVE_BADDR_BT_LEN      (12)
+#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_POS      (25)
+#define ZXDH_SDT_L_KEEP_ALIVE_BADDR_BT_LEN      (7)
+#define ZXDH_SDT_L_RSP_MODE_BT_POS              (23)
+#define ZXDH_SDT_L_RSP_MODE_BT_LEN              (2)
+#define ZXDH_SDT_H_ETCAM_ID_BT_POS              (27)
+#define ZXDH_SDT_H_ETCAM_ID_BT_LEN              (1)
+#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_POS        (25)
+#define ZXDH_SDT_H_ETCAM_KEY_MODE_BT_LEN        (2)
+#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_POS        (21)
+#define ZXDH_SDT_H_ETCAM_TABLE_ID_BT_LEN        (4)
+#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_POS   (19)
+#define ZXDH_SDT_H_ETCAM_NOAS_RSP_MODE_BT_LEN   (2)
+#define ZXDH_SDT_H_ETCAM_AS_EN_BT_POS           (18)
+#define ZXDH_SDT_H_ETCAM_AS_EN_BT_LEN           (1)
+#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_POS   (0)
+#define ZXDH_SDT_H_ETCAM_AS_ERAM_BADDR_BT_LEN   (18)
+#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_POS   (31)
+#define ZXDH_SDT_L_ETCAM_AS_ERAM_BADDR_BT_LEN   (1)
+#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_POS     (28)
+#define ZXDH_SDT_L_ETCAM_AS_RSP_MODE_BT_LEN     (3)
+#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_POS     (1)
+#define ZXDH_SDT_L_ETCAM_TABLE_DEPTH_BT_LEN     (20)
+#define ZXDH_SDT_L_CLUTCH_EN_BT_POS             (0)
+#define ZXDH_SDT_L_CLUTCH_EN_BT_LEN             (1)
+
 /**errco code */
 #define ZXDH_RC_BASE                            (0x1000U)
 #define ZXDH_PARAMETER_CHK_BASE                 (ZXDH_RC_BASE            | 0x200)
@@ -206,11 +271,15 @@ typedef enum zxdh_dev_type_e {
 } ZXDH_DEV_TYPE_E;
 
 typedef enum zxdh_reg_info_e {
-	ZXDH_DTB_CFG_QUEUE_DTB_HADDR   = 0,
-	ZXDH_DTB_CFG_QUEUE_DTB_LADDR   = 1,
-	ZXDH_DTB_CFG_QUEUE_DTB_LEN    = 2,
-	ZXDH_DTB_INFO_QUEUE_BUF_SPACE = 3,
-	ZXDH_DTB_CFG_EPID_V_FUNC_NUM  = 4,
+	ZXDH_SMMU0_SMMU0_CPU_IND_CMDR        = 0,
+	ZXDH_SMMU0_SMMU0_CPU_IND_RD_DONER    = 1,
+	ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R      = 2,
+	ZXDH_SMMU0_SMMU0_CPU_IND_RDAT1R      = 3,
+	ZXDH_SMMU0_SMMU0_CPU_IND_RDAT2R      = 4,
+	ZXDH_SMMU0_SMMU0_CPU_IND_RDAT3R      = 5,
+	ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR     = 6,
+	ZXDH_DTB_INFO_QUEUE_BUF_SPACE        = 7,
+	ZXDH_DTB_CFG_EPID_V_FUNC_NUM         = 8,
 	ZXDH_STAT_CAR0_CARA_QUEUE_RAM0       = 9,
 	ZXDH_STAT_CAR0_CARB_QUEUE_RAM0       = 10,
 	ZXDH_STAT_CAR0_CARC_QUEUE_RAM0       = 11,
@@ -218,6 +287,12 @@ typedef enum zxdh_reg_info_e {
 	ZXDH_REG_ENUM_MAX_VALUE
 } ZXDH_REG_INFO_E;
 
+typedef enum zxdh_dev_spinlock_type_e {
+	ZXDH_DEV_SPINLOCK_T_SMMU0     = 0,
+	ZXDH_DEV_SPINLOCK_T_DTB       = 1,
+	ZXDH_DEV_SPINLOCK_T_MAX
+} ZXDH_DEV_SPINLOCK_TYPE_E;
+
 typedef enum zxdh_dev_access_type_e {
 	ZXDH_DEV_ACCESS_TYPE_PCIE = 0,
 	ZXDH_DEV_ACCESS_TYPE_RISCV = 1,
@@ -237,6 +312,29 @@ typedef enum zxdh_acl_pri_mode_e {
 	ZXDH_ACL_PRI_INVALID,
 } ZXDH_ACL_PRI_MODE_E;
 
+typedef enum zxdh_module_e {
+	CFG = 1,
+	NPPU,
+	PPU,
+	ETM,
+	STAT,
+	CAR,
+	SE,
+	SMMU0 = SE,
+	SMMU1 = SE,
+	DTB,
+	TRPG,
+	TSN,
+	AXI,
+	PTPTM,
+	DTB4K,
+	STAT4K,
+	PPU4K,
+	SE4K,
+	SMMU14K,
+	MODULE_MAX
+} ZXDH_MODULE_E;
+
 typedef struct zxdh_d_node {
 	void *data;
 	struct zxdh_d_node *prev;
@@ -301,6 +399,49 @@ typedef struct dpp_sdt_soft_table_t {
 	ZXDH_SDT_ITEM_T  sdt_array[ZXDH_DEV_SDT_ID_MAX];
 } ZXDH_SDT_SOFT_TABLE_T;
 
+typedef struct zxdh_sdt_tbl_eram_t {
+	uint32_t table_type;
+	uint32_t eram_mode;
+	uint32_t eram_base_addr;
+	uint32_t eram_table_depth;
+	uint32_t eram_clutch_en;
+} ZXDH_SDT_TBL_ERAM_T;
+
+typedef struct zxdh_sdt_tbl_etcam_t {
+	uint32_t table_type;
+	uint32_t etcam_id;
+	uint32_t etcam_key_mode;
+	uint32_t etcam_table_id;
+	uint32_t no_as_rsp_mode;
+	uint32_t as_en;
+	uint32_t as_eram_baddr;
+	uint32_t as_rsp_mode;
+	uint32_t etcam_table_depth;
+	uint32_t etcam_clutch_en;
+} ZXDH_SDT_TBL_ETCAM_T;
+
+typedef struct zxdh_sdt_tbl_hash_t {
+	uint32_t table_type;
+	uint32_t hash_id;
+	uint32_t hash_table_width;
+	uint32_t key_size;
+	uint32_t hash_table_id;
+	uint32_t learn_en;
+	uint32_t keep_alive;
+	uint32_t keep_alive_baddr;
+	uint32_t rsp_mode;
+	uint32_t hash_clutch_en;
+} ZXDH_SDT_TBL_HASH_T;
+
+typedef struct zxdh_spin_lock_t {
+	rte_spinlock_t spinlock;
+} ZXDH_SPINLOCK_T;
+
+typedef void (*ZXDH_DEV_WRITE_FUNC)(uint32_t dev_id,
+		uint32_t addr, uint32_t size, uint32_t *p_data);
+typedef void (*ZXDH_DEV_READ_FUNC)(uint32_t dev_id,
+		uint32_t addr, uint32_t size, uint32_t *p_data);
+
 typedef struct zxdh_sys_init_ctrl_t {
 	ZXDH_DEV_TYPE_E device_type;
 	uint32_t flags;
@@ -327,6 +468,8 @@ typedef struct dpp_dev_cfg_t {
 	uint64_t dma_phy_addr;
 	uint64_t agent_addr;
 	uint32_t init_flags[ZXDH_MODULE_INIT_MAX];
+	ZXDH_DEV_WRITE_FUNC p_pcie_write_fun;
+	ZXDH_DEV_READ_FUNC  p_pcie_read_fun;
 } ZXDH_DEV_CFG_T;
 
 typedef struct zxdh_dev_mngr_t {
@@ -338,8 +481,8 @@ typedef struct zxdh_dev_mngr_t {
 typedef struct zxdh_dtb_addr_info_t {
 	uint32_t sdt_no;
 	uint32_t size;
-	uint32_t phy_addr;
-	uint32_t vir_addr;
+	uint64_t phy_addr;
+	uint64_t vir_addr;
 } ZXDH_DTB_ADDR_INFO_T;
 
 typedef struct zxdh_dev_init_ctrl_t {
@@ -349,12 +492,12 @@ typedef struct zxdh_dev_init_ctrl_t {
 	uint32_t queue_id;
 	uint32_t np_bar_offset;
 	uint32_t np_bar_len;
-	uint32_t pcie_vir_addr;
-	uint32_t down_phy_addr;
-	uint32_t down_vir_addr;
-	uint32_t dump_phy_addr;
-	uint32_t dump_vir_addr;
-	uint32_t dump_sdt_num;
+	uint64_t pcie_vir_addr;
+	uint64_t down_phy_addr;
+	uint64_t down_vir_addr;
+	uint64_t dump_phy_addr;
+	uint64_t dump_vir_addr;
+	uint64_t dump_sdt_num;
 	ZXDH_DTB_ADDR_INFO_T dump_addr_info[];
 } ZXDH_DEV_INIT_CTRL_T;
 
@@ -424,7 +567,7 @@ typedef struct zxdh_reg_t {
 	uint32_t  m_step;
 	uint32_t  n_step;
 	uint32_t  field_num;
-	ZXDH_FIELD_T *p_fields;
+	const ZXDH_FIELD_T *p_fields;
 
 	ZXDH_REG_WRITE      p_write_fun;
 	ZXDH_REG_READ       p_read_fun;
@@ -515,14 +658,6 @@ typedef struct zxdh_dtb_eram_table_form_t {
 	uint32_t data_l;
 } ZXDH_DTB_ERAM_TABLE_FORM_T;
 
-typedef struct zxdh_sdt_tbl_eram_t {
-	uint32_t table_type;
-	uint32_t eram_mode;
-	uint32_t eram_base_addr;
-	uint32_t eram_table_depth;
-	uint32_t eram_clutch_en;
-} ZXDH_SDTTBL_ERAM_T;
-
 typedef union zxdh_endian_u {
 	unsigned int     a;
 	unsigned char    b;
@@ -538,7 +673,7 @@ typedef struct zxdh_dtb_table_t {
 	const char    *table_type;
 	uint32_t  table_no;
 	uint32_t  field_num;
-	ZXDH_DTB_FIELD_T *p_fields;
+	const ZXDH_DTB_FIELD_T *p_fields;
 } ZXDH_DTB_TABLE_T;
 
 typedef struct zxdh_dtb_queue_item_info_t {
@@ -550,12 +685,6 @@ typedef struct zxdh_dtb_queue_item_info_t {
 	uint32_t data_hddr;
 } ZXDH_DTB_QUEUE_ITEM_INFO_T;
 
-typedef struct zxdh_dtb_queue_len_t {
-	uint32_t cfg_dtb_cmd_type;
-	uint32_t cfg_dtb_cmd_int_en;
-	uint32_t cfg_queue_dtb_len;
-} ZXDH_DTB_QUEUE_LEN_T;
-
 typedef struct zxdh_dtb_eram_entry_info_t {
 	uint32_t index;
 	uint32_t *p_data;
@@ -571,23 +700,10 @@ typedef struct zxdh_sdt_tbl_data_t {
 	uint32_t data_low32;
 } ZXDH_SDT_TBL_DATA_T;
 
-typedef struct zxdh_sdt_tbl_etcam_t {
-	uint32_t table_type;
-	uint32_t etcam_id;
-	uint32_t etcam_key_mode;
-	uint32_t etcam_table_id;
-	uint32_t no_as_rsp_mode;
-	uint32_t as_en;
-	uint32_t as_eram_baddr;
-	uint32_t as_rsp_mode;
-	uint32_t etcam_table_depth;
-	uint32_t etcam_clutch_en;
-} ZXDH_SDTTBL_ETCAM_T;
-
 typedef struct zxdh_sdt_tbl_porttbl_t {
 	uint32_t table_type;
 	uint32_t porttbl_clutch_en;
-} ZXDH_SDTTBL_PORTTBL_T;
+} ZXDH_SDT_TBL_PORTTBL_T;
 
 typedef struct zxdh_dtb_hash_entry_info_t {
 	uint8_t *p_actu_key;
@@ -614,15 +730,6 @@ typedef struct zxdh_smmu0_smmu0_cpu_ind_cmd_t {
 	uint32_t cpu_ind_addr;
 } ZXDH_SMMU0_SMMU0_CPU_IND_CMD_T;
 
-typedef enum zxdh_smmu0_smmu0_type_e {
-	ZXDH_DEV_MUTEX_T_SMMU0             = 0,
-	ZXDH_SMMU0_SMMU0_CPU_IND_CMDR      = 1,
-	ZXDH_SMMU0_SMMU0_CPU_IND_RDAT0R    = 2,
-	ZXDH_SMMU0_SMMU0_RD_CPU_IND_DONER  = 3,
-	ZXDH_SMMU0_SMMU0_WR_ARB_CPU_RDYR   = 4,
-	ZXDH_SMMU0_SMMU0_ED_ARB_CPU_RDYR   = 5,
-} ZXDH_SEMMU0_SEMMU0_TYPE_E;
-
 typedef enum zxdh_stat_rd_clr_mode_e {
 	ZXDH_STAT_RD_CLR_MODE_UNCLR = 0,
 	ZXDH_STAT_RD_CLR_MODE_CLR   = 1,
@@ -635,8 +742,8 @@ typedef enum zxdh_eram128_rd_clr_mode_e {
 } ZXDH_ERAM128_RD_CLR_MODE_E;
 
 typedef enum zxdh_se_opr_mode_e {
-	ZXDH_SE_OPR_RD      = 0,
-	ZXDH_SE_OPR_WR      = 1,
+	ZXDH_SE_OPR_WR      = 0,
+	ZXDH_SE_OPR_RD      = 1,
 } ZXDH_SE_OPR_MODE_E;
 
 typedef enum zxdh_stat_car_type_e {
@@ -730,11 +837,6 @@ typedef struct dpp_agent_car_pkt_profile_msg {
 	uint32_t pri[ZXDH_CAR_PRI_MAX];
 } ZXDH_AGENT_CAR_PKT_PROFILE_MSG_T;
 
-typedef struct zxdh_agent_channel_msg_t {
-	uint32_t msg_len;
-	void *msg;
-} ZXDH_AGENT_CHANNEL_MSG_T;
-
 typedef struct zxdh_agent_channel_plcr_msg {
 	uint8_t dev_id;
 	uint8_t type;
@@ -803,6 +905,10 @@ typedef enum zxdh_profile_type {
 	CAR_MAX
 } ZXDH_PROFILE_TYPE;
 
+typedef struct __rte_aligned(2) zxdh_agent_channel_msg_t {
+	uint32_t msg_len;
+	void *msg;
+} ZXDH_AGENT_CHANNEL_MSG_T;
 
 int zxdh_np_host_init(uint32_t dev_id, ZXDH_DEV_INIT_CTRL_T *p_dev_init_ctrl);
 int zxdh_np_online_uninit(uint32_t dev_id, char *port_name, uint32_t queue_id);
-- 
2.27.0

[-- Attachment #1.1.2: Type: text/html , Size: 244256 bytes --]

  reply	other threads:[~2025-03-17 15:14 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-10  1:44 [PATCH v1 " Bingbin Chen
2025-02-10  1:46 ` [PATCH v1 02/14] net/zxdh: support compatibility check Bingbin Chen
2025-02-10 17:25   ` Stephen Hemminger
2025-02-10  1:47 ` [PATCH v1 03/14] net/zxdh: add agent channel Bingbin Chen
2025-02-10 17:28   ` Stephen Hemminger
2025-02-10 17:30   ` Stephen Hemminger
2025-02-10 17:31   ` Stephen Hemminger
2025-02-10 18:23   ` Stephen Hemminger
2025-02-10  1:47 ` [PATCH v1 04/14] net/zxdh: modify dtb queue ops Bingbin Chen
2025-02-10 17:31   ` Stephen Hemminger
2025-02-10  1:48 ` [PATCH v1 05/14] net/zxdh: add tables dump address ops Bingbin Chen
2025-02-10 17:33   ` Stephen Hemminger
2025-02-10  1:50 ` [PATCH v1 06/14] net/zxdh: add eram tables ops Bingbin Chen
2025-02-10  1:50   ` [PATCH v1 07/14] net/zxdh: get flow tables resources Bingbin Chen
2025-02-10 17:35     ` Stephen Hemminger
2025-02-10 17:35     ` Stephen Hemminger
2025-02-10  1:50   ` [PATCH v1 08/14] net/zxdh: support hash resources configuration Bingbin Chen
2025-02-10 17:36     ` Stephen Hemminger
2025-02-10  1:50   ` [PATCH v1 09/14] net/zxdh: implement tables initialization Bingbin Chen
2025-02-10 17:40     ` Stephen Hemminger
2025-02-10 17:43     ` Stephen Hemminger
2025-02-10  1:50   ` [PATCH v1 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen
2025-02-10 17:45     ` Stephen Hemminger
2025-02-10  1:50   ` [PATCH v1 11/14] net/zxdh: get hash table entry result Bingbin Chen
2025-02-10 17:46     ` Stephen Hemminger
2025-02-10  1:50   ` [PATCH v1 12/14] net/zxdh: delete all hash entries Bingbin Chen
2025-02-10 17:47     ` Stephen Hemminger
2025-02-10  1:50   ` [PATCH v1 13/14] net/zxdh: add acl tables ops Bingbin Chen
2025-02-10  1:50   ` [PATCH v1 14/14] net/zxdh: clean stat values Bingbin Chen
2025-02-10 17:50     ` Stephen Hemminger
2025-02-10 17:50     ` Stephen Hemminger
2025-02-10 18:19     ` Stephen Hemminger
2025-02-22  7:22 ` [PATCH v2 00/14] add network processor ops Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 01/14] net/zxdh: add network processor registers ops Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 02/14] net/zxdh: support compatibility check Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 03/14] net/zxdh: add agent channel Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 04/14] net/zxdh: modify dtb queue ops Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 05/14] net/zxdh: add tables dump address ops Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 06/14] net/zxdh: add eram tables ops Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 07/14] net/zxdh: get flow tables resources Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 08/14] net/zxdh: support hash resources configuration Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 09/14] net/zxdh: implement tables initialization Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 11/14] net/zxdh: get hash table entry result Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 12/14] net/zxdh: delete all hash entries Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 13/14] net/zxdh: add acl tables ops Bingbin Chen
2025-02-22  7:22   ` [PATCH v2 14/14] net/zxdh: clean stat values Bingbin Chen
2025-02-22 17:34     ` Stephen Hemminger
2025-03-05  8:13 ` [PATCH v3 00/14] net/zxdh: add network processor ops Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 01/14] net/zxdh: add network processor registers ops Bingbin Chen
2025-03-17 14:57     ` [PATCH v4 00/14] net/zxdh: add network processor ops Bingbin Chen
2025-03-17 14:57       ` Bingbin Chen [this message]
2025-03-17 14:57       ` [PATCH v4 02/14] net/zxdh: support compatibility check Bingbin Chen
2025-03-17 14:57       ` [PATCH v4 03/14] net/zxdh: add agent channel Bingbin Chen
2025-03-17 14:57       ` [PATCH v4 04/14] net/zxdh: modify dtb queue ops Bingbin Chen
2025-03-17 14:57       ` [PATCH v4 05/14] net/zxdh: add tables dump address ops Bingbin Chen
2025-03-17 14:57       ` [PATCH v4 06/14] net/zxdh: add eram tables ops Bingbin Chen
2025-03-17 14:57       ` [PATCH v4 07/14] net/zxdh: get flow tables resources Bingbin Chen
2025-03-17 14:57       ` [PATCH v4 08/14] net/zxdh: support hash resources configuration Bingbin Chen
2025-03-17 14:57       ` [PATCH v4 09/14] net/zxdh: implement tables initialization Bingbin Chen
2025-03-17 14:57       ` [PATCH v4 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen
2025-03-17 14:57       ` [PATCH v4 11/14] net/zxdh: get hash table entry result Bingbin Chen
2025-03-17 14:58       ` [PATCH v4 12/14] net/zxdh: delete all hash entries Bingbin Chen
2025-03-17 14:58       ` [PATCH v4 13/14] net/zxdh: add acl tables ops Bingbin Chen
2025-03-17 14:58       ` [PATCH v4 14/14] net/zxdh: fix debugging errors Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 02/14] net/zxdh: support compatibility check Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 03/14] net/zxdh: add agent channel Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 04/14] net/zxdh: modify dtb queue ops Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 05/14] net/zxdh: add tables dump address ops Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 06/14] net/zxdh: add eram tables ops Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 07/14] net/zxdh: get flow tables resources Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 08/14] net/zxdh: support hash resources configuration Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 09/14] net/zxdh: implement tables initialization Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 10/14] net/zxdh: support hash tables write and delete ops Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 11/14] net/zxdh: get hash table entry result Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 12/14] net/zxdh: delete all hash entries Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 13/14] net/zxdh: add acl tables ops Bingbin Chen
2025-03-05  8:13   ` [PATCH v3 14/14] net/zxdh: modify parameters of the plcr function Bingbin Chen
2025-03-10 23:19 ` [PATCH v1 01/14] net/zxdh: add network processor registers ops Stephen Hemminger

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