From: Gregory Etelson <getelson@nvidia.com>
To: <dev@dpdk.org>
Cc: getelson@nvidia.com, <mkashani@nvidia.com>,
rasland@nvidia.com,
"Wathsala Vithanage" <wathsala.vithanage@arm.com>,
"Bruce Richardson" <bruce.richardson@intel.com>,
"Jerin Jacob" <jerinj@marvell.com>,
"Pavan Nikhilesh" <pbhagavatula@marvell.com>
Subject: [PATCH] config/arm: fix meson for native instruction set Arm CPUs
Date: Wed, 19 Mar 2025 12:25:05 +0200 [thread overview]
Message-ID: <20250319102505.596678-1-getelson@nvidia.com> (raw)
Arm meson.build unconditionally relays on the `extra_features`
member of SoC configuration.
SoC dictionary is populated for Arm CPUs with generic instruction set
only.
For Arm CPUs with native CPU instruction set the SoC dictionary is
empty.
meson setup failed for the BlueField-3 because it belongs to
the native Arm CPU instruction set.
The patch adds global definition for extra_features.
Fixes: 7829776d0abf ("config/arm: add extra -march features")
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
---
config/arm/meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/config/arm/meson.build b/config/arm/meson.build
index a97a28ebb7..f971ed3c1b 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -767,6 +767,7 @@ dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
update_flags = false
soc_flags = []
+extra_features = []
if dpdk_conf.get('RTE_ARCH_32')
# 32-bit build
dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
--
2.45.2
next reply other threads:[~2025-03-19 10:25 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-19 10:25 Gregory Etelson [this message]
2025-03-19 11:02 ` [EXTERNAL] " Pavan Nikhilesh Bhagavatula
2025-03-19 11:10 ` Pavan Nikhilesh Bhagavatula
2025-03-19 11:48 ` Thomas Monjalon
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