* [RFC PATCH 1/4] ethdev: add support to provide link type
@ 2025-04-03 7:08 Nithin Dabilpuram
2025-04-03 7:08 ` [RFC PATCH 2/4] common/cnxk: support to get speed cap from fwdata Nithin Dabilpuram
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Nithin Dabilpuram @ 2025-04-03 7:08 UTC (permalink / raw)
To: Thomas Monjalon, Ferruh Yigit, Andrew Rybchenko; +Cc: dev, Nithin Dabilpuram
Add support to provide link type as part of link status
if available from ethdev driver. Link type such as Fibre,
Twisted-Pair etc is generally available information in PMD or
lower layer software and is a useful information for DPDK
applications. Similar info is also available via ethtool
for Linux kernel netdevs.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
lib/ethdev/ethdev_trace.h | 7 +++++
lib/ethdev/ethdev_trace_points.c | 3 +++
lib/ethdev/rte_ethdev.c | 44 ++++++++++++++++++++++++++++++--
lib/ethdev/rte_ethdev.h | 28 ++++++++++++++++++++
lib/ethdev/version.map | 1 +
5 files changed, 81 insertions(+), 2 deletions(-)
diff --git a/lib/ethdev/ethdev_trace.h b/lib/ethdev/ethdev_trace.h
index c65b78590a..a060e2de03 100644
--- a/lib/ethdev/ethdev_trace.h
+++ b/lib/ethdev/ethdev_trace.h
@@ -2110,6 +2110,13 @@ RTE_TRACE_POINT_FP(
rte_trace_point_emit_string(ret);
)
+RTE_TRACE_POINT_FP(
+ rte_eth_trace_link_type_to_str,
+ RTE_TRACE_POINT_ARGS(uint8_t link_type, const char *ret),
+ rte_trace_point_emit_u8(link_type);
+ rte_trace_point_emit_string(ret);
+);
+
/* Called in loop in examples/bond and examples/ethtool */
RTE_TRACE_POINT_FP(
rte_eth_trace_macaddr_get,
diff --git a/lib/ethdev/ethdev_trace_points.c b/lib/ethdev/ethdev_trace_points.c
index cb99cf91fc..e6dee5f668 100644
--- a/lib/ethdev/ethdev_trace_points.c
+++ b/lib/ethdev/ethdev_trace_points.c
@@ -199,6 +199,9 @@ RTE_TRACE_POINT_REGISTER(rte_eth_trace_link_speed_to_str,
RTE_TRACE_POINT_REGISTER(rte_eth_trace_link_to_str,
lib.ethdev.link_to_str)
+RTE_TRACE_POINT_REGISTER(rte_eth_trace_link_type_to_str,
+ lib.ethdev.link_type_to_str)
+
RTE_TRACE_POINT_REGISTER(rte_eth_trace_stats_get,
lib.ethdev.stats_get)
diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c
index 85798d0ebc..9e993199f5 100644
--- a/lib/ethdev/rte_ethdev.c
+++ b/lib/ethdev/rte_ethdev.c
@@ -3221,18 +3221,58 @@ rte_eth_link_to_str(char *str, size_t len, const struct rte_eth_link *eth_link)
if (eth_link->link_status == RTE_ETH_LINK_DOWN)
ret = snprintf(str, len, "Link down");
else
- ret = snprintf(str, len, "Link up at %s %s %s",
+ ret = snprintf(str, len, "Link up at %s %s %s %s",
rte_eth_link_speed_to_str(eth_link->link_speed),
(eth_link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ?
"FDX" : "HDX",
(eth_link->link_autoneg == RTE_ETH_LINK_AUTONEG) ?
- "Autoneg" : "Fixed");
+ "Autoneg" : "Fixed",
+ rte_eth_link_type_to_str(eth_link->link_type));
rte_eth_trace_link_to_str(len, eth_link, str, ret);
return ret;
}
+const char *
+rte_eth_link_type_to_str(uint8_t link_type)
+{
+ const char *ret;
+
+ switch (link_type) {
+ case RTE_ETH_LINK_TYPE_NONE:
+ ret = "None";
+ break;
+ case RTE_ETH_LINK_TYPE_TP:
+ ret = "Twisted Pair";
+ break;
+ case RTE_ETH_LINK_TYPE_AUI:
+ ret = "AUI";
+ break;
+ case RTE_ETH_LINK_TYPE_MII:
+ ret = "MII";
+ break;
+ case RTE_ETH_LINK_TYPE_FIBRE:
+ ret = "Fibre";
+ break;
+ case RTE_ETH_LINK_TYPE_BNC:
+ ret = "BNC";
+ break;
+ case RTE_ETH_LINK_TYPE_DA:
+ ret = "Direct Attach Copper";
+ break;
+ case RTE_ETH_LINK_TYPE_OTHER:
+ ret = "Other";
+ break;
+ default:
+ ret = "Invalid";
+ }
+
+ rte_eth_trace_link_type_to_str(link_type, ret);
+
+ return ret;
+}
+
int
rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats)
{
diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h
index ea7f8c4a1a..ccbb657fb9 100644
--- a/lib/ethdev/rte_ethdev.h
+++ b/lib/ethdev/rte_ethdev.h
@@ -329,6 +329,19 @@ struct rte_eth_stats {
#define RTE_ETH_SPEED_NUM_UNKNOWN UINT32_MAX /**< Unknown */
/**@}*/
+/**@{@name PORT type
+ * Ethernet port type
+ */
+#define RTE_ETH_LINK_TYPE_NONE 0x00 /**< Not defined */
+#define RTE_ETH_LINK_TYPE_TP 0x01 /**< Twisted Pair */
+#define RTE_ETH_LINK_TYPE_AUI 0x02 /**< Attachment Unit Interface */
+#define RTE_ETH_LINK_TYPE_MII 0x03 /**< Media Independent Interface */
+#define RTE_ETH_LINK_TYPE_FIBRE 0x04 /**< Fibre */
+#define RTE_ETH_LINK_TYPE_BNC 0x05 /**< BNC */
+#define RTE_ETH_LINK_TYPE_DA 0x06 /**< Direct Attach copper */
+#define RTE_ETH_LINK_TYPE_OTHER 0x1F /**< Other type */
+/**@}*/
+
/**
* A structure used to retrieve link-level information of an Ethernet port.
*/
@@ -341,6 +354,7 @@ struct rte_eth_link {
uint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */
uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */
uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */
+ uint16_t link_type : 5; /**< RTE_ETH_LINK_TYPE_* */
};
};
};
@@ -3113,6 +3127,20 @@ int rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *link)
__rte_experimental
const char *rte_eth_link_speed_to_str(uint32_t link_speed);
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice.
+ *
+ * This function converts an Ethernet link type to a string.
+ *
+ * @param link_type
+ * The link type to convert.
+ * @return
+ * The string representation of the link type.
+ */
+__rte_experimental
+const char *rte_eth_link_type_to_str(uint8_t link_type);
+
/**
* @warning
* @b EXPERIMENTAL: this API may change without prior notice.
diff --git a/lib/ethdev/version.map b/lib/ethdev/version.map
index 3aacba8614..5910ed10a5 100644
--- a/lib/ethdev/version.map
+++ b/lib/ethdev/version.map
@@ -216,6 +216,7 @@ EXPERIMENTAL {
rte_eth_hairpin_unbind;
rte_eth_link_speed_to_str;
rte_eth_link_to_str;
+ rte_eth_link_type_to_str;
rte_eth_fec_get_capability;
rte_eth_fec_get;
rte_eth_fec_set;
--
2.34.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [RFC PATCH 2/4] common/cnxk: support to get speed cap from fwdata 2025-04-03 7:08 [RFC PATCH 1/4] ethdev: add support to provide link type Nithin Dabilpuram @ 2025-04-03 7:08 ` Nithin Dabilpuram 2025-04-03 7:08 ` [RFC PATCH 3/4] common/cnxk: provide port type " Nithin Dabilpuram ` (2 subsequent siblings) 3 siblings, 0 replies; 8+ messages in thread From: Nithin Dabilpuram @ 2025-04-03 7:08 UTC (permalink / raw) To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao, Harman Kalra Cc: dev Speed capability currently is updating as all speeds capable. Get it from CGX fw data supported link modes instead. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> --- drivers/common/cnxk/hw/nix.h | 54 ++++++++++++++++++++++ drivers/common/cnxk/roc_mbox.h | 24 +++++++--- drivers/common/cnxk/roc_nix.h | 8 +++- drivers/common/cnxk/roc_nix_mac.c | 28 ++++++++++++ drivers/common/cnxk/roc_nix_priv.h | 2 + drivers/common/cnxk/version.map | 1 + drivers/net/cnxk/cnxk_ethdev.c | 72 ++++++++++++++++++++++++++++-- 7 files changed, 180 insertions(+), 9 deletions(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index d16fa3b3ec..de989153ff 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2681,4 +2681,58 @@ struct nix_lso_format { */ #define NIX_CHAN_CPT_X2P_MASK (0x7ffull) +/* CGX modes defined by firmware */ +enum cgx_mode { + CGX_MODE_SGMII, + CGX_MODE_1000_BASEX, + CGX_MODE_QSGMII, + CGX_MODE_10G_C2C, + CGX_MODE_10G_C2M, + CGX_MODE_10G_KR, + CGX_MODE_20G_C2C, + CGX_MODE_25G_C2C, + CGX_MODE_25G_C2M, + CGX_MODE_25G_2_C2C, + CGX_MODE_25G_CR, + CGX_MODE_25G_KR, + CGX_MODE_40G_C2C, + CGX_MODE_40G_C2M, + CGX_MODE_40G_CR4, + CGX_MODE_40G_KR4, + CGX_MODE_40GAUI_C2C, + CGX_MODE_50G_C2C, + CGX_MODE_50G_C2M, + CGX_MODE_50G_4_C2C, + CGX_MODE_50G_CR, + CGX_MODE_50G_KR, + CGX_MODE_80GAUI_C2C, + CGX_MODE_100G_C2C, + CGX_MODE_100G_C2M, + CGX_MODE_100G_CR4, + CGX_MODE_100G_KR4, + CGX_MODE_LAUI_2_C2C_BIT, + CGX_MODE_LAUI_2_C2M_BIT, + CGX_MODE_50GBASE_CR2_C_BIT, + CGX_MODE_50GBASE_KR2_C_BIT, /* = 30 */ + CGX_MODE_100GAUI_2_C2C_BIT, + CGX_MODE_100GAUI_2_C2M_BIT, + CGX_MODE_100GBASE_CR2_BIT, + CGX_MODE_100GBASE_KR2_BIT, + CGX_MODE_SFI_1G_BIT, + CGX_MODE_25GBASE_CR_C_BIT, + CGX_MODE_25GBASE_KR_C_BIT, + ETH_MODE_SGMII_10M_BIT, + ETH_MODE_SGMII_100M_BIT, /* = 39 */ + ETH_MODE_2500_BASEX_BIT = 42, /* Mode group 1 */ + ETH_MODE_5000_BASEX_BIT, + ETH_MODE_O_USGMII_BIT, + ETH_MODE_Q_USGMII_BIT, + ETH_MODE_2_5G_USXGMII_BIT, + ETH_MODE_5G_USXGMII_BIT, + ETH_MODE_10G_SXGMII_BIT, + ETH_MODE_10G_DXGMII_BIT, + ETH_MODE_10G_QXGMII_BIT, + CGX_MODE_MAX /* = 51 */ +}; + #endif /* __NIX_HW_H__ */ diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index a82d120d1d..9038ca8fcf 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -755,8 +755,17 @@ enum fec_type { }; struct phy_s { - uint64_t __io can_change_mod_type : 1; - uint64_t __io mod_type : 1; + struct { + uint64_t __io can_change_mod_type:1; + uint64_t __io mod_type:1; + uint64_t __io has_fec_stats:1; + } misc; + struct fec_stats_s { + uint32_t __io rsfec_corr_cws; + uint32_t __io rsfec_uncorr_cws; + uint32_t __io brfec_corr_blks; + uint32_t __io brfec_uncorr_blks; + } fec_stats; }; struct cgx_lmac_fwdata_s { @@ -764,13 +773,18 @@ struct cgx_lmac_fwdata_s { uint64_t __io supported_fec; uint64_t __io supported_an; uint64_t __io supported_link_modes; - /* Only applicable if AN is supported */ + /* only applicable if AN is supported */ uint64_t __io advertised_fec; - uint64_t __io advertised_link_modes; + uint64_t __io advertised_link_modes_own : 1; /* CGX_CMD_OWN */ + uint64_t __io advertised_link_modes : 63; /* Only applicable if SFP/QSFP slot is present */ struct sfp_eeprom_s sfp_eeprom; struct phy_s phy; -#define LMAC_FWDATA_RESERVED_MEM 1023 + uint32_t __io lmac_type; + uint32_t __io portm_idx; + uint64_t __io mgmt_port : 1; + uint64_t __io advertised_an : 1; +#define LMAC_FWDATA_RESERVED_MEM 1019 uint64_t __io reserved[LMAC_FWDATA_RESERVED_MEM]; }; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index a1bd14ffc4..c438a4447c 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -413,6 +413,11 @@ struct roc_nix_link_info { uint64_t port : 8; }; +struct roc_nix_mac_fwdata { + uint64_t advertised_link_modes; + uint64_t supported_link_modes; +}; + /** Maximum name length for extended statistics counters */ #define ROC_NIX_XSTATS_NAME_SIZE 64 @@ -493,7 +498,7 @@ struct roc_nix { bool reass_ena; TAILQ_ENTRY(roc_nix) next; -#define ROC_NIX_MEM_SZ (6 * 1112) +#define ROC_NIX_MEM_SZ (6 * 1200) uint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; @@ -856,6 +861,7 @@ void __roc_api roc_nix_mac_link_info_get_cb_unregister(struct roc_nix *roc_nix); int __roc_api roc_nix_q_err_cb_register(struct roc_nix *roc_nix, q_err_get_t sq_err_handle); void __roc_api roc_nix_q_err_cb_unregister(struct roc_nix *roc_nix); int __roc_api roc_nix_mac_stats_reset(struct roc_nix *roc_nix); +int __roc_api roc_nix_mac_fwdata_get(struct roc_nix *roc_nix, struct roc_nix_mac_fwdata *fwdata); /* Ops */ int __roc_api roc_nix_switch_hdr_set(struct roc_nix *roc_nix, diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c index 54db1adf17..b99f93818a 100644 --- a/drivers/common/cnxk/roc_nix_mac.c +++ b/drivers/common/cnxk/roc_nix_mac.c @@ -412,3 +412,31 @@ roc_nix_mac_link_info_get_cb_unregister(struct roc_nix *roc_nix) dev->ops->link_status_get = NULL; } + +int +roc_nix_mac_fwdata_get(struct roc_nix *roc_nix, struct roc_nix_mac_fwdata *data) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct cgx_fw_data *fw_data; + struct dev *dev = &nix->dev; + struct mbox *mbox; + int rc; + + if (roc_nix_is_sdp(roc_nix)) + return 0; + + mbox = mbox_get(dev->mbox); + + mbox_alloc_msg_cgx_get_aux_link_info(mbox); + rc = mbox_process_msg(mbox, (void *)&fw_data); + if (rc) + goto exit; + + nix->supported_link_modes = fw_data->fwdata.supported_link_modes; + nix->advertised_link_modes = fw_data->fwdata.advertised_link_modes; + data->supported_link_modes = nix->supported_link_modes; + data->advertised_link_modes = nix->advertised_link_modes; +exit: + mbox_put(mbox); + return rc; +} diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 09a55e43ce..31e37fc356 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -130,6 +130,8 @@ struct nix { uint16_t bpid[NIX_MAX_CHAN]; struct nix_qint *qints_mem; struct nix_qint *cints_mem; + uint64_t supported_link_modes; + uint64_t advertised_link_modes; uint8_t configured_qints; uint8_t configured_cints; uint8_t exact_match_ena; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index cdbfc1d39a..93cfaa96da 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -307,6 +307,7 @@ INTERNAL { roc_nix_mac_addr_add; roc_nix_mac_addr_del; roc_nix_mac_addr_set; + roc_nix_mac_fwdata_get; roc_nix_mac_link_cb_register; roc_nix_mac_link_cb_unregister; roc_nix_mac_link_info_get_cb_register; diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 289ae96afa..4dba4968d5 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -6,6 +6,60 @@ #include <rte_eventdev.h> #include <rte_pmd_cnxk.h> +const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = { + [CGX_MODE_SGMII] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_1000_BASEX] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_QSGMII] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_10G_C2C] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_10G_C2M] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_10G_KR] = RTE_ETH_LINK_SPEED_10G, + [CGX_MODE_20G_C2C] = RTE_ETH_LINK_SPEED_20G, + [CGX_MODE_25G_C2C] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_C2M] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_2_C2C] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_CR] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25G_KR] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_40G_C2C] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_C2M] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_CR4] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40G_KR4] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_40GAUI_C2C] = RTE_ETH_LINK_SPEED_40G, + [CGX_MODE_50G_C2C] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_C2M] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_4_C2C] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_CR] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50G_KR] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_80GAUI_C2C] = 0, /* No define for 80G */ + [CGX_MODE_100G_C2C] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_C2M] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_CR4] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100G_KR4] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_LAUI_2_C2C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_LAUI_2_C2M_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50GBASE_CR2_C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_50GBASE_KR2_C_BIT] = RTE_ETH_LINK_SPEED_50G, + [CGX_MODE_100GAUI_2_C2C_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GAUI_2_C2M_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GBASE_CR2_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_100GBASE_KR2_BIT] = RTE_ETH_LINK_SPEED_100G, + [CGX_MODE_SFI_1G_BIT] = RTE_ETH_LINK_SPEED_1G, + [CGX_MODE_25GBASE_CR_C_BIT] = RTE_ETH_LINK_SPEED_25G, + [CGX_MODE_25GBASE_KR_C_BIT] = RTE_ETH_LINK_SPEED_25G, + [ETH_MODE_SGMII_10M_BIT] = RTE_ETH_LINK_SPEED_10M, + [ETH_MODE_SGMII_100M_BIT] = RTE_ETH_LINK_SPEED_100M, + [40] = 0, + [41] = 0, + [ETH_MODE_2500_BASEX_BIT] = RTE_ETH_LINK_SPEED_2_5G, + [ETH_MODE_5000_BASEX_BIT] = RTE_ETH_LINK_SPEED_5G, + [ETH_MODE_O_USGMII_BIT] = RTE_ETH_LINK_SPEED_100M, + [ETH_MODE_Q_USGMII_BIT] = RTE_ETH_LINK_SPEED_1G, + [ETH_MODE_2_5G_USXGMII_BIT] = RTE_ETH_LINK_SPEED_2_5G, + [ETH_MODE_5G_USXGMII_BIT] = RTE_ETH_LINK_SPEED_5G, + [ETH_MODE_10G_SXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, + [ETH_MODE_10G_DXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, + [ETH_MODE_10G_QXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, +}; + cnxk_ethdev_rx_offload_cb_t cnxk_ethdev_rx_offload_cb; #define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL) @@ -40,14 +94,26 @@ nix_get_tx_offload_capa(struct cnxk_eth_dev *dev) static inline uint32_t nix_get_speed_capa(struct cnxk_eth_dev *dev) { + struct roc_nix_mac_fwdata fwdata; uint32_t speed_capa; + uint8_t mode; + int rc; /* Auto negotiation disabled */ speed_capa = RTE_ETH_LINK_SPEED_FIXED; if (!roc_nix_is_vf_or_sdp(&dev->nix) && !roc_nix_is_lbk(&dev->nix)) { - speed_capa |= RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G | - RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G | - RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G; + memset(&fwdata, 0, sizeof(fwdata)); + rc = roc_nix_mac_fwdata_get(&dev->nix, &fwdata); + if (rc) { + plt_err("Failed to get MAC firmware data"); + return 0; + } + + /* Translate advertised modes to speed_capa */ + for (mode = 0; mode < CGX_MODE_MAX; mode++) { + if (fwdata.supported_link_modes & BIT_ULL(mode)) + speed_capa |= cnxk_mac_modes[mode]; + } } return speed_capa; -- 2.34.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [RFC PATCH 3/4] common/cnxk: provide port type from fwdata 2025-04-03 7:08 [RFC PATCH 1/4] ethdev: add support to provide link type Nithin Dabilpuram 2025-04-03 7:08 ` [RFC PATCH 2/4] common/cnxk: support to get speed cap from fwdata Nithin Dabilpuram @ 2025-04-03 7:08 ` Nithin Dabilpuram 2025-04-03 7:08 ` [RFC PATCH 4/4] net/cnxk: report link type along with link status Nithin Dabilpuram 2025-04-04 0:46 ` [RFC PATCH 1/4] ethdev: add support to provide link type Stephen Hemminger 3 siblings, 0 replies; 8+ messages in thread From: Nithin Dabilpuram @ 2025-04-03 7:08 UTC (permalink / raw) To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao, Harman Kalra Cc: dev Port type data is made available by firmware via CGX lmac specific firmware data. Extract the same. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> --- drivers/common/cnxk/hw/nix.h | 12 ++++++++++++ drivers/common/cnxk/roc_mbox.h | 4 ++-- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_mac.c | 1 + 4 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index de989153ff..2aa23da037 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2735,4 +2735,16 @@ enum cgx_mode { CGX_MODE_MAX /* = 51 */ }; +/* CGX Port types from kernel */ +enum cgx_port_type { + CGX_PORT_TP = 0x0, + CGX_PORT_AUI, + CGX_PORT_MII, + CGX_PORT_FIBRE, + CGX_PORT_BNC, + CGX_PORT_DA, + CGX_PORT_NONE = 0xef, + CGX_PORT_OTHER = 0xff, +}; + #endif /* __NIX_HW_H__ */ diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 9038ca8fcf..1b0bfbc186 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -783,8 +783,8 @@ struct cgx_lmac_fwdata_s { uint32_t __io lmac_type; uint32_t __io portm_idx; uint64_t __io mgmt_port : 1; - uint64_t __io advertised_an : 1; -#define LMAC_FWDATA_RESERVED_MEM 1019 + uint64_t __io port; +#define LMAC_FWDATA_RESERVED_MEM 1018 uint64_t __io reserved[LMAC_FWDATA_RESERVED_MEM]; }; diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index c438a4447c..65778933dd 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -416,6 +416,7 @@ struct roc_nix_link_info { struct roc_nix_mac_fwdata { uint64_t advertised_link_modes; uint64_t supported_link_modes; + uint64_t port_type; }; /** Maximum name length for extended statistics counters */ diff --git a/drivers/common/cnxk/roc_nix_mac.c b/drivers/common/cnxk/roc_nix_mac.c index b99f93818a..026ff41ef2 100644 --- a/drivers/common/cnxk/roc_nix_mac.c +++ b/drivers/common/cnxk/roc_nix_mac.c @@ -436,6 +436,7 @@ roc_nix_mac_fwdata_get(struct roc_nix *roc_nix, struct roc_nix_mac_fwdata *data) nix->advertised_link_modes = fw_data->fwdata.advertised_link_modes; data->supported_link_modes = nix->supported_link_modes; data->advertised_link_modes = nix->advertised_link_modes; + data->port_type = fw_data->fwdata.port; exit: mbox_put(mbox); return rc; -- 2.34.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* [RFC PATCH 4/4] net/cnxk: report link type along with link status 2025-04-03 7:08 [RFC PATCH 1/4] ethdev: add support to provide link type Nithin Dabilpuram 2025-04-03 7:08 ` [RFC PATCH 2/4] common/cnxk: support to get speed cap from fwdata Nithin Dabilpuram 2025-04-03 7:08 ` [RFC PATCH 3/4] common/cnxk: provide port type " Nithin Dabilpuram @ 2025-04-03 7:08 ` Nithin Dabilpuram 2025-04-04 0:46 ` [RFC PATCH 1/4] ethdev: add support to provide link type Stephen Hemminger 3 siblings, 0 replies; 8+ messages in thread From: Nithin Dabilpuram @ 2025-04-03 7:08 UTC (permalink / raw) To: Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori, Satha Rao, Harman Kalra Cc: dev Provide link type along with link status get. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> --- drivers/net/cnxk/cnxk_ethdev.c | 21 ++++++++++++++++++++- drivers/net/cnxk/cnxk_ethdev.h | 1 + drivers/net/cnxk/cnxk_link.c | 10 +++++++--- 3 files changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 4dba4968d5..9dc442fa6d 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -6,7 +6,7 @@ #include <rte_eventdev.h> #include <rte_pmd_cnxk.h> -const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = { +static const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = { [CGX_MODE_SGMII] = RTE_ETH_LINK_SPEED_1G, [CGX_MODE_1000_BASEX] = RTE_ETH_LINK_SPEED_1G, [CGX_MODE_QSGMII] = RTE_ETH_LINK_SPEED_1G, @@ -60,6 +60,17 @@ const uint32_t cnxk_mac_modes[CGX_MODE_MAX + 1] = { [ETH_MODE_10G_QXGMII_BIT] = RTE_ETH_LINK_SPEED_10G, }; +static const uint8_t cnxk_port_type[] = { + [CGX_PORT_TP] = RTE_ETH_LINK_TYPE_TP, + [CGX_PORT_AUI] = RTE_ETH_LINK_TYPE_AUI, + [CGX_PORT_MII] = RTE_ETH_LINK_TYPE_MII, + [CGX_PORT_FIBRE] = RTE_ETH_LINK_TYPE_FIBRE, + [CGX_PORT_BNC] = RTE_ETH_LINK_TYPE_BNC, + [CGX_PORT_DA] = RTE_ETH_LINK_TYPE_DA, + [CGX_PORT_NONE] = RTE_ETH_LINK_TYPE_NONE, + [CGX_PORT_OTHER] = RTE_ETH_LINK_TYPE_OTHER, +}; + cnxk_ethdev_rx_offload_cb_t cnxk_ethdev_rx_offload_cb; #define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL) @@ -95,6 +106,7 @@ static inline uint32_t nix_get_speed_capa(struct cnxk_eth_dev *dev) { struct roc_nix_mac_fwdata fwdata; + struct rte_eth_link link; uint32_t speed_capa; uint8_t mode; int rc; @@ -114,6 +126,12 @@ nix_get_speed_capa(struct cnxk_eth_dev *dev) if (fwdata.supported_link_modes & BIT_ULL(mode)) speed_capa |= cnxk_mac_modes[mode]; } + dev->link_type = cnxk_port_type[(uint8_t)fwdata.port_type]; + + /* Set link type at init */ + memset(&link, 0, sizeof(link)); + link.link_type = dev->link_type; + rte_eth_linkstatus_set(dev->eth_dev, &link); } return speed_capa; @@ -1757,6 +1775,7 @@ cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev) /* Bring down link status internally */ memset(&link, 0, sizeof(link)); + link.link_type = dev->link_type; rte_eth_linkstatus_set(eth_dev, &link); return 0; diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index daf80be51b..5f8df43d42 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -370,6 +370,7 @@ struct cnxk_eth_dev { uint64_t rx_offload_capa; uint64_t tx_offload_capa; uint32_t speed_capa; + uint8_t link_type; /* Configured Rx and Tx offloads */ uint64_t rx_offloads; uint64_t tx_offloads; diff --git a/drivers/net/cnxk/cnxk_link.c b/drivers/net/cnxk/cnxk_link.c index 903b44de2c..38970eddd6 100644 --- a/drivers/net/cnxk/cnxk_link.c +++ b/drivers/net/cnxk/cnxk_link.c @@ -47,14 +47,16 @@ static void nix_link_status_print(struct rte_eth_dev *eth_dev, struct rte_eth_link *link) { if (link && link->link_status) - plt_info("Port %d: Link Up - speed %u Mbps - %s", + plt_info("Port %d: Link Up - speed %u Mbps - %s - %s", (int)(eth_dev->data->port_id), (uint32_t)link->link_speed, link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX ? "full-duplex" - : "half-duplex"); + : "half-duplex", + rte_eth_link_type_to_str(link->link_type)); else - plt_info("Port %d: Link Down", (int)(eth_dev->data->port_id)); + plt_info("Port %d: Link Down - %s", (int)(eth_dev->data->port_id), + rte_eth_link_type_to_str(link->link_type)); } void @@ -103,6 +105,7 @@ cnxk_eth_dev_link_status_cb(struct roc_nix *nix, struct roc_nix_link_info *link) eth_link.link_speed = link->speed; eth_link.link_autoneg = RTE_ETH_LINK_AUTONEG; eth_link.link_duplex = link->full_duplex; + eth_link.link_type = dev->link_type; /* Print link info */ nix_link_status_print(eth_dev, ð_link); @@ -142,6 +145,7 @@ cnxk_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete) link.link_autoneg = RTE_ETH_LINK_AUTONEG; if (info.full_duplex) link.link_duplex = info.full_duplex; + link.link_type = dev->link_type; } return rte_eth_linkstatus_set(eth_dev, &link); -- 2.34.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC PATCH 1/4] ethdev: add support to provide link type 2025-04-03 7:08 [RFC PATCH 1/4] ethdev: add support to provide link type Nithin Dabilpuram ` (2 preceding siblings ...) 2025-04-03 7:08 ` [RFC PATCH 4/4] net/cnxk: report link type along with link status Nithin Dabilpuram @ 2025-04-04 0:46 ` Stephen Hemminger 2025-04-15 7:08 ` Nithin Dabilpuram 3 siblings, 1 reply; 8+ messages in thread From: Stephen Hemminger @ 2025-04-04 0:46 UTC (permalink / raw) To: Nithin Dabilpuram; +Cc: Thomas Monjalon, Ferruh Yigit, Andrew Rybchenko, dev On Thu, 3 Apr 2025 12:38:34 +0530 Nithin Dabilpuram <ndabilpuram@marvell.com> wrote: > /** > * A structure used to retrieve link-level information of an Ethernet port. > */ > @@ -341,6 +354,7 @@ struct rte_eth_link { > uint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ > uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */ > uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */ > + uint16_t link_type : 5; /**< RTE_ETH_LINK_TYPE_* */ > }; > }; > }; Seems like an ABI break, and not sure that all drivers will fill those bits with zero now. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC PATCH 1/4] ethdev: add support to provide link type 2025-04-04 0:46 ` [RFC PATCH 1/4] ethdev: add support to provide link type Stephen Hemminger @ 2025-04-15 7:08 ` Nithin Dabilpuram 2025-04-16 0:03 ` Stephen Hemminger 0 siblings, 1 reply; 8+ messages in thread From: Nithin Dabilpuram @ 2025-04-15 7:08 UTC (permalink / raw) To: Stephen Hemminger Cc: Nithin Dabilpuram, Thomas Monjalon, Ferruh Yigit, Andrew Rybchenko, dev On Fri, Apr 4, 2025 at 6:16 AM Stephen Hemminger <stephen@networkplumber.org> wrote: > > On Thu, 3 Apr 2025 12:38:34 +0530 > Nithin Dabilpuram <ndabilpuram@marvell.com> wrote: > > > /** > > * A structure used to retrieve link-level information of an Ethernet port. > > */ > > @@ -341,6 +354,7 @@ struct rte_eth_link { > > uint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ > > uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */ > > uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */ > > + uint16_t link_type : 5; /**< RTE_ETH_LINK_TYPE_* */ > > }; > > }; > > }; > > Seems like an ABI break, and not sure that all drivers will fill those bits with zero now. Generally ABI is between APP and all DPDK libraries/PMD and not between DPDK libraries and PMD ? For example: #1 App build with DPDK 24.11, DPDK libraries and PMD's based on 24.11 #2 App built with DPDK 24.11, DPDK libraries and PMD's based on 25.07 #3 App build with DPDK 24.11, DPDK libraries based on 25.07 and PMD's based on 24.11 #4 App build with DPDK 24.11, DPDK libraries based on 24.11 and PMD's based on 25.07 For scenario #2, there is no issue if my change can includes memset in ethdev library ? Scenario #3 and Scenario #4 are not really valid right ? Scenario #2 is not possible right ? ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC PATCH 1/4] ethdev: add support to provide link type 2025-04-15 7:08 ` Nithin Dabilpuram @ 2025-04-16 0:03 ` Stephen Hemminger 2025-04-16 9:08 ` Nithin Dabilpuram 0 siblings, 1 reply; 8+ messages in thread From: Stephen Hemminger @ 2025-04-16 0:03 UTC (permalink / raw) To: Nithin Dabilpuram Cc: Nithin Dabilpuram, Thomas Monjalon, Ferruh Yigit, Andrew Rybchenko, dev On Tue, 15 Apr 2025 12:38:18 +0530 Nithin Dabilpuram <nithind1988@gmail.com> wrote: > On Fri, Apr 4, 2025 at 6:16 AM Stephen Hemminger > <stephen@networkplumber.org> wrote: > > > > On Thu, 3 Apr 2025 12:38:34 +0530 > > Nithin Dabilpuram <ndabilpuram@marvell.com> wrote: > > > > > /** > > > * A structure used to retrieve link-level information of an Ethernet port. > > > */ > > > @@ -341,6 +354,7 @@ struct rte_eth_link { > > > uint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ > > > uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */ > > > uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */ > > > + uint16_t link_type : 5; /**< RTE_ETH_LINK_TYPE_* */ > > > }; > > > }; > > > }; > > > > Seems like an ABI break, and not sure that all drivers will fill those bits with zero now. > > Generally ABI is between APP and all DPDK libraries/PMD and not > between DPDK libraries and PMD ? The problem is rte_eth_link is returne by rte_eth_link_get which is exposed to the application. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC PATCH 1/4] ethdev: add support to provide link type 2025-04-16 0:03 ` Stephen Hemminger @ 2025-04-16 9:08 ` Nithin Dabilpuram 0 siblings, 0 replies; 8+ messages in thread From: Nithin Dabilpuram @ 2025-04-16 9:08 UTC (permalink / raw) To: Stephen Hemminger Cc: Nithin Dabilpuram, Thomas Monjalon, Ferruh Yigit, Andrew Rybchenko, dev On Wed, Apr 16, 2025 at 5:33 AM Stephen Hemminger <stephen@networkplumber.org> wrote: > > On Tue, 15 Apr 2025 12:38:18 +0530 > Nithin Dabilpuram <nithind1988@gmail.com> wrote: > > > On Fri, Apr 4, 2025 at 6:16 AM Stephen Hemminger > > <stephen@networkplumber.org> wrote: > > > > > > On Thu, 3 Apr 2025 12:38:34 +0530 > > > Nithin Dabilpuram <ndabilpuram@marvell.com> wrote: > > > > > > > /** > > > > * A structure used to retrieve link-level information of an Ethernet port. > > > > */ > > > > @@ -341,6 +354,7 @@ struct rte_eth_link { > > > > uint16_t link_duplex : 1; /**< RTE_ETH_LINK_[HALF/FULL]_DUPLEX */ > > > > uint16_t link_autoneg : 1; /**< RTE_ETH_LINK_[AUTONEG/FIXED] */ > > > > uint16_t link_status : 1; /**< RTE_ETH_LINK_[DOWN/UP] */ > > > > + uint16_t link_type : 5; /**< RTE_ETH_LINK_TYPE_* */ > > > > }; > > > > }; > > > > }; > > > > > > Seems like an ABI break, and not sure that all drivers will fill those bits with zero now. > > > > Generally ABI is between APP and all DPDK libraries/PMD and not > > between DPDK libraries and PMD ? > > The problem is rte_eth_link is returne by rte_eth_link_get which is exposed > to the application. Which scenario you are talking about here ? ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-04-16 9:09 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2025-04-03 7:08 [RFC PATCH 1/4] ethdev: add support to provide link type Nithin Dabilpuram 2025-04-03 7:08 ` [RFC PATCH 2/4] common/cnxk: support to get speed cap from fwdata Nithin Dabilpuram 2025-04-03 7:08 ` [RFC PATCH 3/4] common/cnxk: provide port type " Nithin Dabilpuram 2025-04-03 7:08 ` [RFC PATCH 4/4] net/cnxk: report link type along with link status Nithin Dabilpuram 2025-04-04 0:46 ` [RFC PATCH 1/4] ethdev: add support to provide link type Stephen Hemminger 2025-04-15 7:08 ` Nithin Dabilpuram 2025-04-16 0:03 ` Stephen Hemminger 2025-04-16 9:08 ` Nithin Dabilpuram
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