* [PATCH 1/6] crypto/cnxk: update the sg list population
2025-05-27 4:00 [PATCH 0/6] fixes and improvements to cnxk crypto PMD Tejasree Kondoj
@ 2025-05-27 4:00 ` Tejasree Kondoj
2025-05-27 4:00 ` [PATCH 2/6] crypto/cnxk: add lookaside IPsec CPT LF stats Tejasree Kondoj
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Tejasree Kondoj @ 2025-05-27 4:00 UTC (permalink / raw)
To: Akhil Goyal; +Cc: Vidya Sagar Velumuri, Anoob Joseph, Aakash Sasidharan, dev
From: Vidya Sagar Velumuri <vvelumuri@marvell.com>
update the last seg with length before populating the scatter list
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
drivers/crypto/cnxk/cn10k_tls_ops.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/cnxk/cn10k_tls_ops.h b/drivers/crypto/cnxk/cn10k_tls_ops.h
index e8e2547f68..c5ef3027ac 100644
--- a/drivers/crypto/cnxk/cn10k_tls_ops.h
+++ b/drivers/crypto/cnxk/cn10k_tls_ops.h
@@ -136,6 +136,8 @@ process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k
g_size_bytes = ((i + 3) / 4) * sizeof(struct roc_sglist_comp);
+ /* Output Scatter List */
+ last_seg->data_len += sess->max_extended_len + pad_bytes;
i = 0;
scatter_comp = (struct roc_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes);
@@ -156,8 +158,6 @@ process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k
w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;
w4.s.opcode_minor = pad_len;
- /* Output Scatter List */
- last_seg->data_len += sess->max_extended_len + pad_bytes;
inst->w4.u64 = w4.u64;
} else {
struct roc_sg2list_comp *scatter_comp, *gather_comp;
@@ -189,6 +189,8 @@ process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k
cpt_inst_w5.s.gather_sz = ((i + 2) / 3);
g_size_bytes = ((i + 2) / 3) * sizeof(struct roc_sg2list_comp);
+ /* Output Scatter List */
+ last_seg->data_len += sess->max_extended_len + pad_bytes;
i = 0;
scatter_comp = (struct roc_sg2list_comp *)((uint8_t *)gather_comp + g_size_bytes);
@@ -209,8 +211,6 @@ process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k
w4.s.opcode_minor = pad_len;
w4.s.param1 = w4.s.dlen;
w4.s.param2 = cop->param1.tls_record.content_type;
- /* Output Scatter List */
- last_seg->data_len += sess->max_extended_len + pad_bytes;
inst->w4.u64 = w4.u64;
}
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 2/6] crypto/cnxk: add lookaside IPsec CPT LF stats
2025-05-27 4:00 [PATCH 0/6] fixes and improvements to cnxk crypto PMD Tejasree Kondoj
2025-05-27 4:00 ` [PATCH 1/6] crypto/cnxk: update the sg list population Tejasree Kondoj
@ 2025-05-27 4:00 ` Tejasree Kondoj
2025-05-27 4:00 ` [PATCH 3/6] crypto/cnxk: fix qp stats PMD API Tejasree Kondoj
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Tejasree Kondoj @ 2025-05-27 4:00 UTC (permalink / raw)
To: Akhil Goyal; +Cc: Anoob Joseph, Aakash Sasidharan, Vidya Sagar Velumuri, dev
Adding global CPT LF stats for lookaside IPsec.
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/crypto/cnxk/cn10k_ipsec.c | 4 ++++
drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/crypto/cnxk/cn10k_ipsec.c b/drivers/crypto/cnxk/cn10k_ipsec.c
index 33ffda0a4c..ae0482d0fe 100644
--- a/drivers/crypto/cnxk/cn10k_ipsec.c
+++ b/drivers/crypto/cnxk/cn10k_ipsec.c
@@ -117,6 +117,8 @@ cn10k_ipsec_outb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,
/* Enable mib counters */
sa_dptr->w0.s.count_mib_bytes = 1;
sa_dptr->w0.s.count_mib_pkts = 1;
+ sa_dptr->w0.s.count_glb_pkts = 1;
+ sa_dptr->w0.s.count_glb_octets = 1;
}
memset(out_sa, 0, sizeof(struct roc_ot_ipsec_outb_sa));
@@ -221,6 +223,8 @@ cn10k_ipsec_inb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,
/* Enable mib counters */
sa_dptr->w0.s.count_mib_bytes = 1;
sa_dptr->w0.s.count_mib_pkts = 1;
+ sa_dptr->w0.s.count_glb_pkts = 1;
+ sa_dptr->w0.s.count_glb_octets = 1;
}
memset(in_sa, 0, sizeof(struct roc_ot_ipsec_inb_sa));
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
index c3a0a58c8f..613ce11ec1 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
@@ -953,6 +953,7 @@ cnxk_cpt_dump_on_err(struct cnxk_cpt_qp *qp)
plt_print("");
roc_cpt_afs_print(qp->lf.roc_cpt);
+ roc_cpt_lfs_print(qp->lf.roc_cpt);
}
int
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 3/6] crypto/cnxk: fix qp stats PMD API
2025-05-27 4:00 [PATCH 0/6] fixes and improvements to cnxk crypto PMD Tejasree Kondoj
2025-05-27 4:00 ` [PATCH 1/6] crypto/cnxk: update the sg list population Tejasree Kondoj
2025-05-27 4:00 ` [PATCH 2/6] crypto/cnxk: add lookaside IPsec CPT LF stats Tejasree Kondoj
@ 2025-05-27 4:00 ` Tejasree Kondoj
2025-05-27 4:00 ` [PATCH 4/6] crypto/cnxk: fail Rx inject configure if not supported Tejasree Kondoj
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Tejasree Kondoj @ 2025-05-27 4:00 UTC (permalink / raw)
To: Akhil Goyal; +Cc: Anoob Joseph, Aakash Sasidharan, Vidya Sagar Velumuri, dev
Fixing qp stats PMD API.
Fixes: bf52722b9377 ("crypto/cnxk: add PMD API to get queue stats")
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
index 613ce11ec1..61f3e135aa 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
@@ -1218,7 +1218,7 @@ rte_pmd_cnxk_crypto_qp_stats_get(struct rte_pmd_cnxk_crypto_qptr *qptr,
stats->ctx_enc_pkts = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT);
stats->ctx_enc_bytes = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT);
- stats->ctx_dec_bytes = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT);
+ stats->ctx_dec_pkts = plt_read64(lf->rbase + CPT_LF_CTX_DEC_PKT_CNT);
stats->ctx_dec_bytes = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT);
return 0;
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 4/6] crypto/cnxk: fail Rx inject configure if not supported
2025-05-27 4:00 [PATCH 0/6] fixes and improvements to cnxk crypto PMD Tejasree Kondoj
` (2 preceding siblings ...)
2025-05-27 4:00 ` [PATCH 3/6] crypto/cnxk: fix qp stats PMD API Tejasree Kondoj
@ 2025-05-27 4:00 ` Tejasree Kondoj
2025-05-27 4:00 ` [PATCH 5/6] crypto/cnxk: add check for max supported gather entries Tejasree Kondoj
2025-05-27 4:00 ` [PATCH 6/6] crypto/cnxk: enable IV from application support Tejasree Kondoj
5 siblings, 0 replies; 7+ messages in thread
From: Tejasree Kondoj @ 2025-05-27 4:00 UTC (permalink / raw)
To: Akhil Goyal; +Cc: Aakash Sasidharan, Anoob Joseph, Vidya Sagar Velumuri, dev
From: Aakash Sasidharan <asasidharan@marvell.com>
Rx inject is supported only with CPT05 microcode version.
sg_ver2 indicates if CPT05 is loaded. Fail the rx inject
configuration with ENOTSUP error if sg_ver2 is not supported.
Signed-off-by: Aakash Sasidharan <asasidharan@marvell.com>
---
drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
index 851e6f0a88..947f50b4c8 100644
--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c
@@ -1981,6 +1981,7 @@ cn10k_cryptodev_sec_rx_inject_configure(void *device, uint16_t port_id, bool ena
{
struct rte_cryptodev *crypto_dev = device;
struct rte_eth_dev *eth_dev;
+ struct cnxk_cpt_vf *vf;
int ret;
if (!rte_eth_dev_is_valid_port(port_id))
@@ -1989,6 +1990,11 @@ cn10k_cryptodev_sec_rx_inject_configure(void *device, uint16_t port_id, bool ena
if (!(crypto_dev->feature_flags & RTE_CRYPTODEV_FF_SECURITY_RX_INJECT))
return -ENOTSUP;
+ /* Rx Inject is supported only with CPT05. sg_ver2 indicates that CPT05 is loaded */
+ vf = crypto_dev->data->dev_private;
+ if (!(vf->cpt.hw_caps[CPT_ENG_TYPE_SE].sg_ver2 && vf->cpt.hw_caps[CPT_ENG_TYPE_IE].sg_ver2))
+ return -ENOTSUP;
+
eth_dev = &rte_eth_devices[port_id];
ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 5/6] crypto/cnxk: add check for max supported gather entries
2025-05-27 4:00 [PATCH 0/6] fixes and improvements to cnxk crypto PMD Tejasree Kondoj
` (3 preceding siblings ...)
2025-05-27 4:00 ` [PATCH 4/6] crypto/cnxk: fail Rx inject configure if not supported Tejasree Kondoj
@ 2025-05-27 4:00 ` Tejasree Kondoj
2025-05-27 4:00 ` [PATCH 6/6] crypto/cnxk: enable IV from application support Tejasree Kondoj
5 siblings, 0 replies; 7+ messages in thread
From: Tejasree Kondoj @ 2025-05-27 4:00 UTC (permalink / raw)
To: Akhil Goyal; +Cc: Vidya Sagar Velumuri, Anoob Joseph, Aakash Sasidharan, dev
From: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Add check for max supported gather entries.
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
drivers/common/cnxk/roc_cpt_sg.h | 1 +
drivers/crypto/cnxk/cn10k_ipsec_la_ops.h | 10 ++++++++++
drivers/crypto/cnxk/cn10k_tls_ops.h | 10 ++++++++++
3 files changed, 21 insertions(+)
diff --git a/drivers/common/cnxk/roc_cpt_sg.h b/drivers/common/cnxk/roc_cpt_sg.h
index c12187144f..e7e01cd29a 100644
--- a/drivers/common/cnxk/roc_cpt_sg.h
+++ b/drivers/common/cnxk/roc_cpt_sg.h
@@ -14,6 +14,7 @@
#define ROC_SG_ENTRY_SIZE sizeof(struct roc_sglist_comp)
#define ROC_SG_MAX_COMP 25
#define ROC_SG_MAX_DLEN_SIZE (ROC_SG_LIST_HDR_SIZE + (ROC_SG_MAX_COMP * ROC_SG_ENTRY_SIZE))
+#define ROC_SG2_MAX_PTRS 48
struct roc_sglist_comp {
union {
diff --git a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h
index 2c500afbca..87442c2a1f 100644
--- a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h
+++ b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h
@@ -159,6 +159,11 @@ process_outb_sa(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k_s
return -ENOMEM;
}
+ if (unlikely(m_src->nb_segs > ROC_SG2_MAX_PTRS)) {
+ plt_dp_err("Exceeds max supported components. Reduce segments");
+ return -1;
+ }
+
m_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);
if (unlikely(m_data == NULL)) {
plt_dp_err("Error allocating meta buffer for request");
@@ -259,6 +264,11 @@ process_inb_sa(struct rte_crypto_op *cop, struct cn10k_sec_session *sess, struct
void *m_data;
int i;
+ if (unlikely(m_src->nb_segs > ROC_SG2_MAX_PTRS)) {
+ plt_dp_err("Exceeds max supported components. Reduce segments");
+ return -1;
+ }
+
m_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);
if (unlikely(m_data == NULL)) {
plt_dp_err("Error allocating meta buffer for request");
diff --git a/drivers/crypto/cnxk/cn10k_tls_ops.h b/drivers/crypto/cnxk/cn10k_tls_ops.h
index c5ef3027ac..427c31425c 100644
--- a/drivers/crypto/cnxk/cn10k_tls_ops.h
+++ b/drivers/crypto/cnxk/cn10k_tls_ops.h
@@ -174,6 +174,11 @@ process_tls_write(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, struct cn10k
return -ENOMEM;
}
+ if (unlikely(m_src->nb_segs > ROC_SG2_MAX_PTRS)) {
+ plt_dp_err("Exceeds max supported components. Reduce segments");
+ return -1;
+ }
+
m_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);
if (unlikely(m_data == NULL)) {
plt_dp_err("Error allocating meta buffer for request");
@@ -305,6 +310,11 @@ process_tls_read(struct rte_crypto_op *cop, struct cn10k_sec_session *sess,
uint32_t g_size_bytes;
int i;
+ if (unlikely(m_src->nb_segs > ROC_SG2_MAX_PTRS)) {
+ plt_dp_err("Exceeds max supported components. Reduce segments");
+ return -1;
+ }
+
m_data = alloc_op_meta(NULL, m_info->mlen, m_info->pool, infl_req);
if (unlikely(m_data == NULL)) {
plt_dp_err("Error allocating meta buffer for request");
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 6/6] crypto/cnxk: enable IV from application support
2025-05-27 4:00 [PATCH 0/6] fixes and improvements to cnxk crypto PMD Tejasree Kondoj
` (4 preceding siblings ...)
2025-05-27 4:00 ` [PATCH 5/6] crypto/cnxk: add check for max supported gather entries Tejasree Kondoj
@ 2025-05-27 4:00 ` Tejasree Kondoj
5 siblings, 0 replies; 7+ messages in thread
From: Tejasree Kondoj @ 2025-05-27 4:00 UTC (permalink / raw)
To: Akhil Goyal; +Cc: Anoob Joseph, Aakash Sasidharan, Vidya Sagar Velumuri, dev
Enabling IV from application as the default option.
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
---
drivers/crypto/cnxk/cn9k_ipsec.c | 19 +------------------
drivers/crypto/cnxk/cn9k_ipsec_la_ops.h | 5 +----
.../crypto/cnxk/cnxk_cryptodev_capabilities.c | 6 ++----
3 files changed, 4 insertions(+), 26 deletions(-)
diff --git a/drivers/crypto/cnxk/cn9k_ipsec.c b/drivers/crypto/cnxk/cn9k_ipsec.c
index fa00c428e6..62478d2340 100644
--- a/drivers/crypto/cnxk/cn9k_ipsec.c
+++ b/drivers/crypto/cnxk/cn9k_ipsec.c
@@ -48,11 +48,8 @@ cn9k_ipsec_outb_sa_create(struct cnxk_cpt_qp *qp,
if (ret)
return ret;
- sess->custom_hdr_len =
- sizeof(struct roc_ie_on_outb_hdr) - ROC_IE_ON_MAX_IV_LEN;
+ sess->custom_hdr_len = sizeof(struct roc_ie_on_outb_hdr) - ROC_IE_ON_MAX_IV_LEN;
-#ifdef LA_IPSEC_DEBUG
- /* Use IV from application in debug mode */
if (ipsec->options.iv_gen_disable == 1) {
sess->custom_hdr_len = sizeof(struct roc_ie_on_outb_hdr);
@@ -67,12 +64,6 @@ cn9k_ipsec_outb_sa_create(struct cnxk_cpt_qp *qp,
sess->cipher_iv_len = crypto_xform->auth.iv.length;
}
}
-#else
- if (ipsec->options.iv_gen_disable != 0) {
- plt_err("Application provided IV is not supported");
- return -ENOTSUP;
- }
-#endif
ret = cnxk_on_ipsec_outb_sa_create(ipsec, crypto_xform, &sa->out_sa);
@@ -89,16 +80,8 @@ cn9k_ipsec_outb_sa_create(struct cnxk_cpt_qp *qp,
param1.u16 = 0;
param1.s.ikev2 = 1;
-#ifdef LA_IPSEC_DEBUG
- /* Use IV from application in debug mode */
if (ipsec->options.iv_gen_disable == 1)
param1.s.per_pkt_iv = ROC_IE_ON_IV_SRC_FROM_DPTR;
-#else
- if (ipsec->options.iv_gen_disable != 0) {
- plt_err("Application provided IV is not supported");
- return -ENOTSUP;
- }
-#endif
w4.s.param1 = param1.u16;
diff --git a/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h
index 3e9f1e7efb..befd5b0c05 100644
--- a/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h
+++ b/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h
@@ -159,13 +159,10 @@ process_outb_sa(struct cpt_qp_meta_info *m_info, struct rte_crypto_op *cop,
inst->w4.s.opcode_major |= (uint64_t)ROC_DMA_MODE_SG;
}
-#ifdef LA_IPSEC_DEBUG
if (sess->inst.w4 & ROC_IE_ON_PER_PKT_IV) {
- memcpy(&hdr->iv[0],
- rte_crypto_op_ctod_offset(cop, uint8_t *, sess->cipher_iv_off),
+ memcpy(&hdr->iv[0], rte_crypto_op_ctod_offset(cop, uint8_t *, sess->cipher_iv_off),
sess->cipher_iv_len);
}
-#endif
m_src->pkt_len = pkt_len;
esn = ++sess->esn;
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
index e78bc37c37..63d2eef349 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c
@@ -2102,11 +2102,9 @@ cn10k_sec_ipsec_caps_update(struct rte_security_capability *sec_cap)
static void
cn9k_sec_ipsec_caps_update(struct rte_security_capability *sec_cap)
{
- if (sec_cap->ipsec.direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS) {
-#ifdef LA_IPSEC_DEBUG
+ if (sec_cap->ipsec.direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS)
sec_cap->ipsec.options.iv_gen_disable = 1;
-#endif
- }
+
sec_cap->ipsec.replay_win_sz_max = CNXK_ON_AR_WIN_SIZE_MAX;
sec_cap->ipsec.options.esn = 1;
}
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread