From: Ciara Loftus <ciara.loftus@intel.com>
To: dev@dpdk.org
Cc: vladimir.medvedkin@intel.com, Ciara Loftus <ciara.loftus@intel.com>
Subject: [PATCH 2/3] net/iavf: fix tx vector path selection logic
Date: Thu, 19 Jun 2025 13:36:57 +0000 [thread overview]
Message-ID: <20250619133658.13494-2-ciara.loftus@intel.com> (raw)
In-Reply-To: <20250619133658.13494-1-ciara.loftus@intel.com>
Prior to this change, it was possible the scalar path would be selected
even if the avx-512 path was available. This was due to the ordering of
the logic in the iavf_set_tx_function function. Support for all three
vector paths (sse, avx2 and avx-512) was first established and then in
that order, the tx_burst_type was set to the appropriate type. If all
three paths were supported, then the burst type would be first set to
sse, then avx2 then avx-512. However, in the avx2 logic, if an error
was encountered then the burst type was set to a fallback option of the
scalar path. This is not desired behaviour because the avx-512 path
should be selected over the scalar path when it is available.
This commit fixes this issue by only checking for avx2 support after
deeming that avx512 is not supported.
Fixes: 77b19d1d4b2e ("net/iavf: fix mbuf release path selection")
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
---
drivers/net/intel/iavf/iavf_rxtx.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/intel/iavf/iavf_rxtx.c b/drivers/net/intel/iavf/iavf_rxtx.c
index 1ce9de0699..a7922ee44d 100644
--- a/drivers/net/intel/iavf/iavf_rxtx.c
+++ b/drivers/net/intel/iavf/iavf_rxtx.c
@@ -4230,16 +4230,16 @@ iavf_set_tx_function(struct rte_eth_dev *dev)
if (check_ret == IAVF_VECTOR_PATH) {
use_sse = true;
}
- if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
- rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
- rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
- use_avx2 = true;
#ifdef CC_AVX512_SUPPORT
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&
rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)
use_avx512 = true;
#endif
+ if (!use_avx512 && (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
+ rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
+ rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
+ use_avx2 = true;
if (!use_sse && !use_avx2 && !use_avx512)
goto normal;
--
2.34.1
next prev parent reply other threads:[~2025-06-19 13:37 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-19 13:36 [PATCH 1/3] net/iavf: support qinq insertion offload for scalar path Ciara Loftus
2025-06-19 13:36 ` Ciara Loftus [this message]
2025-06-19 13:36 ` [PATCH 3/3] net/iavf: support vlan insertion offload for the avx-512 path Ciara Loftus
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