* [PATCH 0/2] *** Wangxun new NIC support ***
@ 2025-04-18 9:41 Zaiyu Wang
2025-04-18 9:41 ` [PATCH 1/2] net/txgbe: add support for Wangxun new NIC Amber-Lite 25g/40g Zaiyu Wang
` (2 more replies)
0 siblings, 3 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-04-18 9:41 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang
We have released a new NIC series: Amber-Lite, with two models supporting
10G/25G and 10G/40G rates. Due to minimal hardware differences from
existing 10G NICs, it remains supported within the txgbe driver.
Zaiyu Wang (2):
net/txgbe: add support for Wangxun new NIC Amber-Lite 25g/40g
net/txgbe: add basic code for Amber-Liter NIC configuration
drivers/net/txgbe/base/meson.build | 4 +
drivers/net/txgbe/base/txgbe_aml.c | 345 +++
drivers/net/txgbe/base/txgbe_aml.h | 11 +
drivers/net/txgbe/base/txgbe_aml40.c | 196 ++
drivers/net/txgbe/base/txgbe_aml40.h | 11 +
drivers/net/txgbe/base/txgbe_devids.h | 9 +
drivers/net/txgbe/base/txgbe_e56.c | 3371 +++++++++++++++++++++++++
drivers/net/txgbe/base/txgbe_e56.h | 1784 +++++++++++++
drivers/net/txgbe/base/txgbe_e56_bp.c | 2238 ++++++++++++++++
drivers/net/txgbe/base/txgbe_e56_bp.h | 13 +
drivers/net/txgbe/base/txgbe_hw.c | 23 +-
drivers/net/txgbe/base/txgbe_hw.h | 2 +-
drivers/net/txgbe/base/txgbe_osdep.h | 4 +
drivers/net/txgbe/base/txgbe_phy.h | 17 +
drivers/net/txgbe/base/txgbe_regs.h | 25 +-
drivers/net/txgbe/base/txgbe_type.h | 36 +
drivers/net/txgbe/txgbe_ethdev.c | 35 +-
17 files changed, 8110 insertions(+), 14 deletions(-)
create mode 100644 drivers/net/txgbe/base/txgbe_aml.c
create mode 100644 drivers/net/txgbe/base/txgbe_aml.h
create mode 100644 drivers/net/txgbe/base/txgbe_aml40.c
create mode 100644 drivers/net/txgbe/base/txgbe_aml40.h
create mode 100644 drivers/net/txgbe/base/txgbe_e56.c
create mode 100644 drivers/net/txgbe/base/txgbe_e56.h
create mode 100644 drivers/net/txgbe/base/txgbe_e56_bp.c
create mode 100644 drivers/net/txgbe/base/txgbe_e56_bp.h
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/2] net/txgbe: add support for Wangxun new NIC Amber-Lite 25g/40g
2025-04-18 9:41 [PATCH 0/2] *** Wangxun new NIC support *** Zaiyu Wang
@ 2025-04-18 9:41 ` Zaiyu Wang
2025-04-18 9:41 ` [PATCH 2/2] net/txgbe: add basic code for Amber-Liter NIC configuration Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
2 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-04-18 9:41 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Amber-Lite is a new model of network interface card launched by Wangxun.
It comes in two types: one supports 10g/25g rates, and the other
supports 10g/40g rates.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_devids.h | 9 +++++++
drivers/net/txgbe/base/txgbe_hw.c | 17 +++++++++++++
drivers/net/txgbe/base/txgbe_regs.h | 4 ++-
drivers/net/txgbe/base/txgbe_type.h | 3 +++
drivers/net/txgbe/txgbe_ethdev.c | 35 ++++++++++++++++++++-------
5 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_devids.h b/drivers/net/txgbe/base/txgbe_devids.h
index a3f26eabf6..b7133c7d54 100644
--- a/drivers/net/txgbe/base/txgbe_devids.h
+++ b/drivers/net/txgbe/base/txgbe_devids.h
@@ -19,6 +19,15 @@
#define TXGBE_DEV_ID_WX1820 0x2001
#define TXGBE_DEV_ID_SP1000_VF 0x1000
#define TXGBE_DEV_ID_WX1820_VF 0x2000
+#define TXGBE_DEV_ID_AML 0x5000
+#define TXGBE_DEV_ID_AML5025 0x5025
+#define TXGBE_DEV_ID_AML5125 0x5125
+#define TXGBE_DEV_ID_AML5040 0x5040
+#define TXGBE_DEV_ID_AML5140 0x5140
+
+#define TXGBE_DEV_ID_AML_VF 0x5001
+#define TXGBE_DEV_ID_AML5024_VF 0x5024
+#define TXGBE_DEV_ID_AML5124_VF 0x5124
/*
* Subsystem IDs
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index dd5d3ea1fe..85dbbc5eff 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -2469,6 +2469,8 @@ s32 txgbe_init_shared_code(struct txgbe_hw *hw)
txgbe_init_ops_dummy(hw);
switch (hw->mac.type) {
case txgbe_mac_raptor:
+ case txgbe_mac_aml:
+ case txgbe_mac_aml40:
status = txgbe_init_ops_pf(hw);
break;
case txgbe_mac_raptor_vf:
@@ -2506,11 +2508,26 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw)
case TXGBE_DEV_ID_WX1820:
hw->mac.type = txgbe_mac_raptor;
break;
+ case TXGBE_DEV_ID_AML:
+ case TXGBE_DEV_ID_AML5025:
+ case TXGBE_DEV_ID_AML5125:
+ hw->mac.type = txgbe_mac_aml;
+ break;
+ case TXGBE_DEV_ID_AML5040:
+ case TXGBE_DEV_ID_AML5140:
+ hw->mac.type = txgbe_mac_aml40;
+ break;
case TXGBE_DEV_ID_SP1000_VF:
case TXGBE_DEV_ID_WX1820_VF:
hw->phy.media_type = txgbe_media_type_virtual;
hw->mac.type = txgbe_mac_raptor_vf;
break;
+ case TXGBE_DEV_ID_AML_VF:
+ case TXGBE_DEV_ID_AML5024_VF:
+ case TXGBE_DEV_ID_AML5124_VF:
+ hw->phy.media_type = txgbe_media_type_virtual;
+ hw->mac.type = txgbe_mac_aml_vf;
+ break;
default:
err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
DEBUGOUT("Unsupported device id: %x", hw->device_id);
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index 7a9ba6976f..a27860ac84 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -97,7 +97,9 @@
#define TXGBE_LINK_SPEED_2_5GB_FULL 0x0400
#define TXGBE_LINK_SPEED_5GB_FULL 0x0800
#define TXGBE_LINK_SPEED_10GB_FULL 0x0080
-#define TXGBE_LINK_SPEED_40GB_FULL 0x0100
+#define TXGBE_LINK_SPEED_25GB_FULL 0x0100
+#define TXGBE_LINK_SPEED_40GB_FULL 0x0040
+#define TXGBE_LINK_SPEED_50GB_FULL 0x0200
#define TXGBE_AUTOC_AUTONEG MS64(63, 0x1)
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 4371876649..1a5e4326a7 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -148,7 +148,10 @@ enum txgbe_eeprom_type {
enum txgbe_mac_type {
txgbe_mac_unknown = 0,
txgbe_mac_raptor,
+ txgbe_mac_aml,
+ txgbe_mac_aml40,
txgbe_mac_raptor_vf,
+ txgbe_mac_aml_vf,
txgbe_num_macs
};
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index ea9faba2c0..2431057485 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -145,6 +145,11 @@ static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
static const struct rte_pci_id pci_id_txgbe_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5025) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5125) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5040) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5140) },
{ .vendor_id = 0, /* sentinel */ },
};
@@ -1829,8 +1834,13 @@ txgbe_dev_start(struct rte_eth_dev *dev)
if (err)
goto error;
- allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G |
- RTE_ETH_LINK_SPEED_10G;
+ if (hw->mac.type == txgbe_mac_aml40)
+ allowed_speeds = RTE_ETH_LINK_SPEED_40G;
+ else if (hw->mac.type == txgbe_mac_aml)
+ allowed_speeds = RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G;
+ else
+ allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G |
+ RTE_ETH_LINK_SPEED_10G;
link_speeds = &dev->data->dev_conf.link_speeds;
if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
@@ -1840,17 +1850,24 @@ txgbe_dev_start(struct rte_eth_dev *dev)
speed = 0x0;
if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
- speed = (TXGBE_LINK_SPEED_100M_FULL |
- TXGBE_LINK_SPEED_1GB_FULL |
- TXGBE_LINK_SPEED_10GB_FULL);
+ if (hw->mac.type == txgbe_mac_aml40) {
+ speed = TXGBE_LINK_SPEED_40GB_FULL;
+ } else if (hw->mac.type == txgbe_mac_aml) {
+ speed = (TXGBE_LINK_SPEED_10GB_FULL |
+ TXGBE_LINK_SPEED_25GB_FULL);
+ } else {
+ speed = (TXGBE_LINK_SPEED_100M_FULL |
+ TXGBE_LINK_SPEED_1GB_FULL |
+ TXGBE_LINK_SPEED_10GB_FULL);
+ }
hw->autoneg = true;
} else {
+ if (*link_speeds & RTE_ETH_LINK_SPEED_40G)
+ speed |= TXGBE_LINK_SPEED_40GB_FULL;
+ if (*link_speeds & RTE_ETH_LINK_SPEED_25G)
+ speed |= TXGBE_LINK_SPEED_25GB_FULL;
if (*link_speeds & RTE_ETH_LINK_SPEED_10G)
speed |= TXGBE_LINK_SPEED_10GB_FULL;
- if (*link_speeds & RTE_ETH_LINK_SPEED_5G)
- speed |= TXGBE_LINK_SPEED_5GB_FULL;
- if (*link_speeds & RTE_ETH_LINK_SPEED_2_5G)
- speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
if (*link_speeds & RTE_ETH_LINK_SPEED_1G)
speed |= TXGBE_LINK_SPEED_1GB_FULL;
if (*link_speeds & RTE_ETH_LINK_SPEED_100M)
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 2/2] net/txgbe: add basic code for Amber-Liter NIC configuration
2025-04-18 9:41 [PATCH 0/2] *** Wangxun new NIC support *** Zaiyu Wang
2025-04-18 9:41 ` [PATCH 1/2] net/txgbe: add support for Wangxun new NIC Amber-Lite 25g/40g Zaiyu Wang
@ 2025-04-18 9:41 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
2 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-04-18 9:41 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Due to minimal hardware differences between Amber-Lite and Wangxun
10G NICs, we continue to support both within the txgbe driver
instead of developing a new one.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/meson.build | 4 +
drivers/net/txgbe/base/txgbe_aml.c | 345 +++
drivers/net/txgbe/base/txgbe_aml.h | 11 +
drivers/net/txgbe/base/txgbe_aml40.c | 196 ++
drivers/net/txgbe/base/txgbe_aml40.h | 11 +
drivers/net/txgbe/base/txgbe_e56.c | 3371 +++++++++++++++++++++++++
drivers/net/txgbe/base/txgbe_e56.h | 1784 +++++++++++++
drivers/net/txgbe/base/txgbe_e56_bp.c | 2238 ++++++++++++++++
drivers/net/txgbe/base/txgbe_e56_bp.h | 13 +
drivers/net/txgbe/base/txgbe_hw.c | 10 +-
drivers/net/txgbe/base/txgbe_hw.h | 2 +-
drivers/net/txgbe/base/txgbe_osdep.h | 4 +
drivers/net/txgbe/base/txgbe_phy.h | 17 +
drivers/net/txgbe/base/txgbe_regs.h | 21 +-
drivers/net/txgbe/base/txgbe_type.h | 33 +
15 files changed, 8054 insertions(+), 6 deletions(-)
create mode 100644 drivers/net/txgbe/base/txgbe_aml.c
create mode 100644 drivers/net/txgbe/base/txgbe_aml.h
create mode 100644 drivers/net/txgbe/base/txgbe_aml40.c
create mode 100644 drivers/net/txgbe/base/txgbe_aml40.h
create mode 100644 drivers/net/txgbe/base/txgbe_e56.c
create mode 100644 drivers/net/txgbe/base/txgbe_e56.h
create mode 100644 drivers/net/txgbe/base/txgbe_e56_bp.c
create mode 100644 drivers/net/txgbe/base/txgbe_e56_bp.h
diff --git a/drivers/net/txgbe/base/meson.build b/drivers/net/txgbe/base/meson.build
index 4cf90a394a..7b191e1d29 100644
--- a/drivers/net/txgbe/base/meson.build
+++ b/drivers/net/txgbe/base/meson.build
@@ -6,10 +6,14 @@ sources = [
'txgbe_dcb.c',
'txgbe_eeprom.c',
'txgbe_hw.c',
+ 'txgbe_aml.c',
+ 'txgbe_aml40.c',
'txgbe_mbx.c',
'txgbe_mng.c',
'txgbe_phy.c',
'txgbe_vf.c',
+ 'txgbe_e56.c',
+ 'txgbe_e56_bp.c',
]
error_cflags = []
diff --git a/drivers/net/txgbe/base/txgbe_aml.c b/drivers/net/txgbe/base/txgbe_aml.c
new file mode 100644
index 0000000000..fdcab65809
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_aml.c
@@ -0,0 +1,345 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
+ */
+
+#include "txgbe_type.h"
+#include "txgbe_mbx.h"
+#include "txgbe_phy.h"
+#include "txgbe_dcb.h"
+#include "txgbe_vf.h"
+#include "txgbe_eeprom.h"
+#include "txgbe_mng.h"
+#include "txgbe_hw.h"
+#include "txgbe_aml.h"
+#include "txgbe_e56.h"
+#include "txgbe_e56_bp.h"
+
+void txgbe_init_ops_aml(struct txgbe_hw *hw);
+s32 txgbe_check_mac_link_aml(struct txgbe_hw *hw,
+ u32 *speed,
+ bool *link_up, bool link_up_wait_to_complete);
+s32 txgbe_get_link_capabilities_aml(struct txgbe_hw *hw,
+ u32 *speed, bool *autoneg);
+u32 txgbe_get_media_type_aml(struct txgbe_hw *hw);
+s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw, u32 speed,
+ bool autoneg_wait_to_complete);
+void txgbe_init_mac_link_ops_aml(struct txgbe_hw *hw);
+
+s32 txgbe_check_mac_link_aml(struct txgbe_hw *hw, u32 *speed,
+ bool *link_up, bool link_up_wait_to_complete)
+{
+ u32 links_reg, links_orig;
+ u32 i;
+
+ /* clear the old state */
+ links_orig = rd32(hw, TXGBE_PORTSTAT);
+
+ links_reg = rd32(hw, TXGBE_PORTSTAT);
+
+ if (links_orig != links_reg) {
+ DEBUGOUT("LINKS changed from %08X to %08X",
+ links_orig, links_reg);
+ }
+
+ if (link_up_wait_to_complete) {
+ for (i = 0; i < hw->mac.max_link_up_time; i++) {
+ if (!(links_reg & TXGBE_PORTSTAT_UP)) {
+ *link_up = false;
+ } else {
+ *link_up = true;
+ break;
+ }
+ msec_delay(100);
+ links_reg = rd32(hw, TXGBE_PORTSTAT);
+ }
+ } else {
+ if (links_reg & TXGBE_PORTSTAT_UP)
+ *link_up = true;
+ else
+ *link_up = false;
+ }
+
+ if (link_up) {
+ switch (links_reg & TXGBE_CFG_PORT_ST_AML_LINK_MASK) {
+ case TXGBE_CFG_PORT_ST_AML_LINK_25G:
+ *speed = TXGBE_LINK_SPEED_25GB_FULL;
+ break;
+ case TXGBE_CFG_PORT_ST_AML_LINK_10G:
+ *speed = TXGBE_LINK_SPEED_10GB_FULL;
+ break;
+ default:
+ *speed = TXGBE_LINK_SPEED_UNKNOWN;
+ }
+ } else
+ *speed = TXGBE_LINK_SPEED_UNKNOWN;
+
+ return 0;
+}
+
+
+s32 txgbe_get_link_capabilities_aml(struct txgbe_hw *hw,
+ u32 *speed,
+ bool *autoneg)
+{
+ if (hw->phy.multispeed_fiber) {
+ *speed = TXGBE_LINK_SPEED_10GB_FULL |
+ TXGBE_LINK_SPEED_25GB_FULL;
+ *autoneg = true;
+ } else if (hw->phy.sfp_type == txgbe_sfp_type_25g_sr_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_sr_core1 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_lr_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_lr_core1) {
+ *speed = TXGBE_LINK_SPEED_25GB_FULL;
+ *autoneg = false;
+ } else if (hw->phy.sfp_type == txgbe_sfp_type_25g_da_cu_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_da_cu_core1 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_5m_da_cu_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_5m_da_cu_core1 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_fcpi4_lmt_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_fcpi4_lmt_core1) {
+ *speed = TXGBE_LINK_SPEED_25GB_FULL;
+ *autoneg = false;
+ }
+
+ return 0;
+}
+
+u32 txgbe_get_media_type_aml(struct txgbe_hw *hw)
+{
+ UNREFERENCED_PARAMETER(hw);
+ return txgbe_media_type_fiber;
+}
+
+s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw,
+ u32 speed,
+ bool autoneg_wait_to_complete)
+{
+ bool autoneg = false;
+ s32 status = 0;
+ s32 ret_status = 0;
+ u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
+ bool link_up = false;
+ int i;
+ u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
+ u32 value = 0;
+
+ UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
+
+ if (hw->phy.sfp_type == txgbe_sfp_type_not_present) {
+ DEBUGOUT("SFP not detected, skip setup mac link");
+ return 0;
+ }
+
+ /* Check to see if speed passed in is supported. */
+ status = hw->mac.get_link_capabilities(hw,
+ &link_capabilities, &autoneg);
+ if (status)
+ return status;
+
+ speed &= link_capabilities;
+ if (speed == TXGBE_LINK_SPEED_UNKNOWN)
+ return TXGBE_ERR_LINK_SETUP;
+
+ if (hw->phy.sfp_type == txgbe_sfp_type_25g_5m_da_cu_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_5m_da_cu_core1||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_da_cu_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_da_cu_core1) {
+ rte_spinlock_lock(&hw->phy_lock);
+ txgbe_e56_set_link_to_kr(hw);
+ rte_spinlock_unlock(&hw->phy_lock);
+ return 0;
+ }
+
+ value = rd32(hw, TXGBE_GPIOEXT);
+ if (value & (TXGBE_SFP1_MOD_ABS_LS | TXGBE_SFP1_RX_LOS_LS))
+ return status;
+
+ for (i = 0; i < 4; i++) {
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+ if (link_up)
+ break;
+ msleep(250);
+ }
+
+ if (link_speed == speed && link_up &&
+ !(speed == TXGBE_LINK_SPEED_25GB_FULL &&
+ !(hw->fec_mode & hw->cur_fec_link))) {
+ hw->tx_speed = speed;
+ return status;
+ }
+
+ if (speed == TXGBE_LINK_SPEED_25GB_FULL &&
+ link_speed == TXGBE_LINK_SPEED_25GB_FULL) {
+ txgbe_e56_fec_polling(hw, &link_up);
+
+ if (link_up)
+ return status;
+ }
+
+ rte_spinlock_lock(&hw->phy_lock);
+ ret_status = txgbe_set_link_to_amlite(hw, speed);
+ rte_spinlock_unlock(&hw->phy_lock);
+ hw->tx_speed = speed;
+
+ if (ret_status == TXGBE_ERR_PHY_INIT_NOT_DONE)
+ return status;
+
+ if (speed == TXGBE_LINK_SPEED_25GB_FULL) {
+ txgbe_e56_fec_polling(hw, &link_up);
+ } else {
+ for (i = 0; i < 4; i++) {
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+ if (link_up)
+ return status;;
+ msleep(250);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * txgbe_setup_mac_link_multispeed_fiber_aml - Set MAC link speed
+ * @hw: pointer to hardware structure
+ * @speed: new link speed
+ * @autoneg_wait_to_complete: true when waiting for completion is needed
+ *
+ * Set the link speed in the MAC and/or PHY register and restarts link.
+ **/
+static s32 txgbe_setup_mac_link_multispeed_fiber_aml(struct txgbe_hw *hw,
+ u32 speed,
+ bool autoneg_wait_to_complete)
+{
+ u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
+ u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
+ s32 status = 0;
+ u32 speedcnt = 0;
+ bool autoneg, link_up = false;
+
+ /* Mask off requested but non-supported speeds */
+ status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
+ if (status != 0)
+ return status;
+
+ speed &= link_speed;
+
+ /* Try each speed one by one, highest priority first. We do this in
+ * software because 10Gb fiber doesn't support speed autonegotiation.
+ */
+ if (speed & TXGBE_LINK_SPEED_25GB_FULL) {
+ speedcnt++;
+ highest_link_speed = TXGBE_LINK_SPEED_25GB_FULL;
+
+ /* If we already have link at this speed, just jump out */
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+
+ if ((link_speed == TXGBE_LINK_SPEED_25GB_FULL) && link_up &&
+ hw->fec_mode & hw->cur_fec_link)
+ goto out;
+
+ /* Allow module to change analog characteristics (1G->10G) */
+ msec_delay(40);
+
+ status = hw->mac.setup_mac_link(hw,
+ TXGBE_LINK_SPEED_25GB_FULL,
+ autoneg_wait_to_complete);
+ if (status != 0)
+ return status;
+
+ /*aml wait link in setup,no need to repeatly wait*/
+ /* If we have link, just jump out */
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+
+ if (link_up)
+ goto out;
+
+ }
+
+ if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
+ speedcnt++;
+ if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
+ highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
+
+ /* If we already have link at this speed, just jump out */
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+
+ if ((link_speed == TXGBE_LINK_SPEED_10GB_FULL) && link_up)
+ goto out;
+
+ /* Allow module to change analog characteristics (25G->10G) */
+ msec_delay(40);
+
+ status = hw->mac.setup_mac_link(hw, TXGBE_LINK_SPEED_10GB_FULL,
+ autoneg_wait_to_complete);
+ if (status != 0)
+ return status;
+
+ /*aml wait link in setup,no need to repeatly wait*/
+ /* If we have link, just jump out */
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+
+ if (link_up)
+ goto out;
+ }
+
+ /* We didn't get link. Configure back to the highest speed we tried,
+ * (if there was more than one). We call ourselves back with just the
+ * single highest speed that the user requested.
+ */
+ if (speedcnt > 1)
+ status = txgbe_setup_mac_link_multispeed_fiber_aml(hw,
+ highest_link_speed,
+ autoneg_wait_to_complete);
+
+out:
+ /* Set autoneg_advertised value based on input link speed */
+ hw->phy.autoneg_advertised = 0;
+
+ if (speed & TXGBE_LINK_SPEED_25GB_FULL)
+ hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_25GB_FULL;
+
+ if (speed & TXGBE_LINK_SPEED_10GB_FULL)
+ hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
+
+ return status;
+}
+
+void txgbe_init_mac_link_ops_aml(struct txgbe_hw *hw)
+{
+ struct txgbe_mac_info *mac = &hw->mac;
+
+ if (hw->phy.media_type == txgbe_media_type_fiber ||
+ hw->phy.media_type == txgbe_media_type_fiber_qsfp) {
+ mac->disable_tx_laser =
+ txgbe_disable_tx_laser_multispeed_fiber;
+ mac->enable_tx_laser =
+ txgbe_enable_tx_laser_multispeed_fiber;
+ mac->flap_tx_laser =
+ txgbe_flap_tx_laser_multispeed_fiber;
+
+ if (hw->phy.multispeed_fiber) {
+ /* Set up dual speed SFP+ support */
+ mac->setup_link = txgbe_setup_mac_link_multispeed_fiber_aml;
+ mac->setup_mac_link = txgbe_setup_mac_link_aml;
+ mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
+ } else {
+ mac->setup_link = txgbe_setup_mac_link_aml;
+ mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
+ }
+ }
+}
+
+void txgbe_init_ops_aml(struct txgbe_hw *hw)
+{
+ struct txgbe_mac_info *mac = &hw->mac;
+ struct txgbe_phy_info *phy = &hw->phy;
+
+ /* PHY */
+ phy->get_media_type = txgbe_get_media_type_aml;
+
+ /* LINK */
+ mac->init_mac_link_ops = txgbe_init_mac_link_ops_aml;
+ mac->get_link_capabilities = txgbe_get_link_capabilities_aml;
+ mac->check_link = txgbe_check_mac_link_aml;
+}
\ No newline at end of file
diff --git a/drivers/net/txgbe/base/txgbe_aml.h b/drivers/net/txgbe/base/txgbe_aml.h
new file mode 100644
index 0000000000..8cda8d46ef
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_aml.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
+ */
+
+#ifndef _TXGBE_AML_H_
+#define _TXGBE_AML_H_
+
+#include "txgbe_type.h"
+
+#endif /* _TXGBE_AML_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_aml40.c b/drivers/net/txgbe/base/txgbe_aml40.c
new file mode 100644
index 0000000000..2b9b354afe
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_aml40.c
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
+ */
+
+#include "txgbe_type.h"
+#include "txgbe_mbx.h"
+#include "txgbe_phy.h"
+#include "txgbe_dcb.h"
+#include "txgbe_vf.h"
+#include "txgbe_eeprom.h"
+#include "txgbe_mng.h"
+#include "txgbe_hw.h"
+#include "txgbe_aml.h"
+#include "txgbe_e56.h"
+#include "txgbe_e56_bp.h"
+
+void txgbe_init_ops_aml40(struct txgbe_hw *hw);
+s32 txgbe_check_mac_link_aml40(struct txgbe_hw *hw,
+ u32 *speed,
+ bool *link_up, bool link_up_wait_to_complete);
+s32 txgbe_get_link_capabilities_aml40(struct txgbe_hw *hw,
+ u32 *speed, bool *autoneg);
+u32 txgbe_get_media_type_aml40(struct txgbe_hw *hw);
+s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw, u32 speed,
+ bool autoneg_wait_to_complete);
+void txgbe_init_mac_link_ops_aml40(struct txgbe_hw *hw);
+
+s32 txgbe_check_mac_link_aml40(struct txgbe_hw *hw, u32 *speed,
+ bool *link_up, bool link_up_wait_to_complete)
+{
+ u32 links_reg, links_orig;
+ u32 i;
+
+ /* clear the old state */
+ links_orig = rd32(hw, TXGBE_PORTSTAT);
+
+ links_reg = rd32(hw, TXGBE_PORTSTAT);
+
+ if (links_orig != links_reg) {
+ DEBUGOUT("LINKS changed from %08X to %08X",
+ links_orig, links_reg);
+ }
+
+ if (link_up_wait_to_complete) {
+ for (i = 0; i < hw->mac.max_link_up_time; i++) {
+ if (!hw->link_valid) {
+ *link_up = false;
+
+ msleep(100);
+ continue;
+ }
+
+ if (!(links_reg & TXGBE_PORTSTAT_UP)) {
+ *link_up = false;
+ } else {
+ *link_up = true;
+ break;
+ }
+ msec_delay(100);
+ links_reg = rd32(hw, TXGBE_PORTSTAT);
+ }
+ } else {
+ if (links_reg & TXGBE_PORTSTAT_UP)
+ *link_up = true;
+ else
+ *link_up = false;
+ }
+
+ if (!hw->link_valid)
+ *link_up = false;
+
+
+ if (link_up) {
+ if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_40G) ==
+ TXGBE_CFG_PORT_ST_AML_LINK_40G)
+ *speed = TXGBE_LINK_SPEED_40GB_FULL;
+ } else
+ *speed = TXGBE_LINK_SPEED_UNKNOWN;
+
+ return 0;
+}
+
+s32 txgbe_get_link_capabilities_aml40(struct txgbe_hw *hw,
+ u32 *speed,
+ bool *autoneg)
+{
+ if (hw->phy.sfp_type == txgbe_sfp_type_40g_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_40g_core1) {
+ *speed = TXGBE_LINK_SPEED_40GB_FULL;
+ *autoneg = false;
+ } else if (hw->phy.sfp_type == txgbe_sfp_type_not_present) {
+ /*
+ * Temporary workaround: set speed to 40G even if sfp not present
+ * to avoid TXGBE_ERR_LINK_SETUP returned by setup_mac_link, but
+ * a more reasonable solution is don't execute setup_mac_link when
+ * sfp module not present.
+ */
+ *speed = TXGBE_LINK_SPEED_40GB_FULL;
+ *autoneg = true;
+ }
+
+ return 0;
+}
+
+u32 txgbe_get_media_type_aml40(struct txgbe_hw *hw)
+{
+ UNREFERENCED_PARAMETER(hw);
+ return txgbe_media_type_fiber_qsfp;
+}
+
+s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw,
+ u32 speed,
+ bool autoneg_wait_to_complete)
+{
+ bool autoneg = false;
+ s32 status = 0;
+ s32 ret_status = 0;
+ u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
+ bool link_up = false;
+ int i;
+ u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
+
+ UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
+
+ if (hw->phy.sfp_type == txgbe_sfp_type_not_present) {
+ DEBUGOUT("SFP not detected, skip setup mac link");
+ return 0;
+ }
+
+ /* Check to see if speed passed in is supported. */
+ status = hw->mac.get_link_capabilities(hw,
+ &link_capabilities, &autoneg);
+ if (status)
+ return status;
+
+ speed &= link_capabilities;
+ if (speed == TXGBE_LINK_SPEED_UNKNOWN)
+ return TXGBE_ERR_LINK_SETUP;
+
+ for (i = 0; i < 4; i++) {
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+ if (link_up)
+ break;
+ msleep(250);
+ }
+
+ if (link_speed == speed && link_up)
+ return status;
+
+ rte_spinlock_lock(&hw->phy_lock);
+ ret_status = txgbe_set_link_to_amlite(hw, speed);
+ rte_spinlock_unlock(&hw->phy_lock);
+ hw->tx_speed = speed;
+
+ if (ret_status == TXGBE_ERR_TIMEOUT)
+ hw->link_valid = false;
+
+ for (i = 0; i < 4; i++) {
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+ if (link_up)
+ return status;
+ msleep(250);
+ }
+
+ return status;
+}
+
+void txgbe_init_mac_link_ops_aml40(struct txgbe_hw *hw)
+{
+ struct txgbe_mac_info *mac = &hw->mac;
+
+ mac->disable_tx_laser =
+ txgbe_disable_tx_laser_multispeed_fiber;
+ mac->enable_tx_laser =
+ txgbe_enable_tx_laser_multispeed_fiber;
+ mac->flap_tx_laser =
+ txgbe_flap_tx_laser_multispeed_fiber;
+
+ mac->setup_link = txgbe_setup_mac_link_aml40;
+ mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
+}
+
+void txgbe_init_ops_aml40(struct txgbe_hw *hw)
+{
+ struct txgbe_mac_info *mac = &hw->mac;
+ struct txgbe_phy_info *phy = &hw->phy;
+
+ /* PHY */
+ phy->get_media_type = txgbe_get_media_type_aml40;
+
+ /* LINK */
+ mac->init_mac_link_ops = txgbe_init_mac_link_ops_aml40;
+ mac->get_link_capabilities = txgbe_get_link_capabilities_aml40;
+ mac->check_link = txgbe_check_mac_link_aml40;
+}
diff --git a/drivers/net/txgbe/base/txgbe_aml40.h b/drivers/net/txgbe/base/txgbe_aml40.h
new file mode 100644
index 0000000000..cd0f46eaf3
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_aml40.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
+ */
+
+#ifndef _TXGBE_AML40_H_
+#define _TXGBE_AML40_H_
+
+#include "txgbe_type.h"
+
+#endif /* _TXGBE_AML40_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_e56.c b/drivers/net/txgbe/base/txgbe_e56.c
new file mode 100644
index 0000000000..8168d5c526
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_e56.c
@@ -0,0 +1,3371 @@
+#include "txgbe_e56.h"
+#include "../txgbe_logs.h"
+
+void
+set_fields_e56(unsigned int *src_data, unsigned int bit_high,
+ unsigned int bit_low, unsigned int set_value)
+{
+ unsigned int i;
+
+ /* Single bit field handling */
+ if (bit_high == bit_low) {
+ if (set_value == 0) {
+ /* clear single bit */
+ *src_data &= ~(1 << bit_low);
+ } else {
+ /* set single bit */
+ *src_data |= (1 << bit_low);
+ }
+ } else {
+ /* first, clear the bit fields */
+ for (i = bit_low; i <= bit_high; i++) {
+ /* clear single bit */
+ *src_data &= ~(1 << i);
+ }
+
+ /* second, or the bit fields with set value */
+ *src_data |= (set_value << bit_low);
+ }
+}
+
+/*
+ * compare function for qsort()
+ */
+static inline
+int compare(const void *a, const void *b)
+{
+ const int *num1 = (const int *)a;
+ const int *num2 = (const int *)b;
+
+ if (*num1 < *num2)
+ return -1;
+
+ else if (*num1 > *num2)
+ return 1;
+
+ else
+ return 0;
+}
+
+s32 txgbe_e56_check_phy_link(struct txgbe_hw *hw, u32 *speed,
+ bool *link_up)
+{
+ u32 rdata = 0;
+ u32 links_reg = 0;
+
+ /* must read it twice because the state may
+ * not be correct the first time you read it
+ */
+ rdata = rd32_epcs(hw, 0x30001);
+ rdata = rd32_epcs(hw, 0x30001);
+
+ if (rdata & TXGBE_E56_PHY_LINK_UP)
+ *link_up = true;
+ else
+ *link_up = false;
+
+ if (!hw->link_valid)
+ *link_up = false;
+
+ links_reg = rd32(hw, TXGBE_PORTSTAT);
+ if (*link_up) {
+ if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_40G) ==
+ TXGBE_CFG_PORT_ST_AML_LINK_40G)
+ *speed = TXGBE_LINK_SPEED_40GB_FULL;
+ else if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_25G) ==
+ TXGBE_CFG_PORT_ST_AML_LINK_25G)
+ *speed = TXGBE_LINK_SPEED_25GB_FULL;
+ else if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_10G) ==
+ TXGBE_CFG_PORT_ST_AML_LINK_10G)
+ *speed = TXGBE_LINK_SPEED_10GB_FULL;
+ } else {
+ *speed = TXGBE_LINK_SPEED_UNKNOWN;
+ }
+
+ return 0;
+}
+
+
+static inline u32
+txgbe_e56_tx_ffe_cfg(struct txgbe_hw *hw, u32 speed)
+{
+ u32 addr;
+
+ u32 ffe_main, pre1, pre2, post;
+ if (hw->phy.sfp_type == txgbe_sfp_type_25g_da_cu_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_da_cu_core1) {
+ ffe_main = S25G_TX_FFE_CFG_DAC_MAIN;
+ pre1 = S25G_TX_FFE_CFG_DAC_PRE1;
+ pre2 = S25G_TX_FFE_CFG_DAC_PRE2;
+ post = S25G_TX_FFE_CFG_DAC_POST;
+ } else {
+ ffe_main = S25G_TX_FFE_CFG_MAIN;
+ pre1 = S25G_TX_FFE_CFG_PRE1;
+ pre2 = S25G_TX_FFE_CFG_PRE2;
+ post = S25G_TX_FFE_CFG_POST;
+ }
+
+ if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
+ addr = 0x141c;
+ wr32_ephy(hw, addr, S10G_TX_FFE_CFG_MAIN);
+
+ addr = 0x1420;
+ wr32_ephy(hw, addr, S10G_TX_FFE_CFG_PRE1);
+
+ addr = 0x1424;
+ wr32_ephy(hw, addr, S10G_TX_FFE_CFG_PRE2);
+
+ addr = 0x1428;
+ wr32_ephy(hw, addr, S10G_TX_FFE_CFG_POST);
+ } else if (speed == TXGBE_LINK_SPEED_25GB_FULL) {
+ addr = 0x141c;
+ wr32_ephy(hw, addr, ffe_main);
+
+ addr = 0x1420;
+ wr32_ephy(hw, addr, pre1);
+
+ addr = 0x1424;
+ wr32_ephy(hw, addr, pre2);
+
+ addr = 0x1428;
+ wr32_ephy(hw, addr, post);
+ }
+
+ return 0;
+}
+
+int
+txgbe_e56_get_temp(struct txgbe_hw *hw, int *pTempData)
+{
+ int data_code, temp_data, temp_fraction;
+ u32 rdata;
+ u32 timer = 0;
+
+ while (1) {
+ rdata = rd32(hw, 0x1033c);
+ if (((rdata >> 12) & 0x1) != 0)
+ break;
+ if (timer++ > PHYINIT_TIMEOUT)
+ return -1;
+ }
+
+ data_code = rdata & 0xFFF;
+ temp_data = 419400 + 2205 * (data_code * 1000 / 4094 - 500);
+
+ /* Change double Temperature to int */
+ *pTempData = temp_data / 10000;
+ temp_fraction = temp_data - (*pTempData * 10000);
+ if (temp_fraction >= 5000)
+ *pTempData += 1;
+
+ return 0;
+}
+
+u32 txgbe_e56_cfg_40g(struct txgbe_hw *hw)
+{
+ u32 addr;
+ u32 rdata = 0;
+ int i;
+
+ //CMS Config Master
+ addr = E56G_CMS_ANA_OVRDVAL_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_CMS_ANA_OVRDVAL_7 *)&rdata)->ana_lcpll_lf_vco_swing_ctrl_i = 0xf;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_CMS_ANA_OVRDEN_1 *)&rdata)->ovrd_en_ana_lcpll_lf_vco_swing_ctrl_i = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G_CMS_ANA_OVRDVAL_9_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 23, 0, 0x260000);
+ wr32_ephy(hw, addr, rdata);
+
+ //TXS Config Master
+ for (i = 0; i < 4; i++) {
+ addr = E56PHY_TXS_TXS_CFG_1_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_TXS_CFG_1_ADAPTATION_WAIT_CNT_X256, 0xf);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_WKUP_CNT_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTLDO_WKUP_CNT_X32, 0xff);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTDCC_WKUP_CNT_X32, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_PIN_OVRDVAL_6_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 19, 16, 0x6);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_PIN_OVRDEN_0_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_PIN_OVRDEN_0_OVRD_EN_TX0_EFUSE_BITS_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_ANA_OVRDVAL_1_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDVAL_1_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_ANA_OVRDEN_0_ADDR + (E56PHY_TXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDEN_0_OVRD_EN_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ }
+ //Setting TX FFE
+ txgbe_e56_tx_ffe_cfg(hw, TXGBE_LINK_SPEED_10GB_FULL);
+
+ //RXS Config master
+ for (i = 0; i < 4; i++) {
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_CMS_ANA_OVRDEN_1 *)&rdata)->ovrd_en_ana_lcpll_lf_test_in_i = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_RXS_CFG_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_DSER_DATA_SEL, 0x0);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_TRAIN_CLK_GATE_BYPASS_EN, 0x1fff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_OSC_CAL_N_CDR_0 *)&rdata)->prediv0 = 0xfa0;
+ ((E56G_RXS0_OSC_CAL_N_CDR_0 *)&rdata)->target_cnt0= 0x203a;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_4_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->osc_range_sel0= 0x2;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->vco_code_init= 0x7ff;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->osc_current_boost_en0= 0x1;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->bbcdr_current_boost0 = 0x0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_SDM_WIDTH, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_PRELOCK, 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_POSTLOCK, 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_POSTLOCK, 0xc);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_PRELOCK, 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BBCDR_RDY_CNT, 0x3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_6_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_PRELOCK, 0x7);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_POSTLOCK, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_INTL_CONFIG_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_INTL_CONFIG_0 *)&rdata)->adc_intl2slice_delay0 = 0x5555;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_INTL_CONFIG_2_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_INTL_CONFIG_2 *)&rdata)->interleaver_hbw_disable0 = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_LTH, 0x56);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_UTH, 0x6a);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_LTH, 0x1e8);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_UTH, 0x78);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_2_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_LTH, 0x100);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_UTH, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_3_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_LTH, 0x4);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_UTH, 0x37);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_TXFFE_TRAIN_MOD_TYPE, 0x38);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_0_VGA_TARGET, 0x34);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT123, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT123, 0xa);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT0, 0x9);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT123, 0x9);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_1_LFEQ_LUT, 0x1ffffea);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_2_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P1, S10G_PHY_RX_CTLE_TAP_FRACP1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P2, S10G_PHY_RX_CTLE_TAP_FRACP2);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P3, S10G_PHY_RX_CTLE_TAP_FRACP3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_3_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P1, S10G_PHY_RX_CTLE_TAPWT_WEIGHT1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P2, S10G_PHY_RX_CTLE_TAPWT_WEIGHT2);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P3, S10G_PHY_RX_CTLE_TAPWT_WEIGHT3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_SLICE_DATA_AVG_CNT, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_DATA_AVG_CNT, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_FE_OFFSET_DAC_CLK_CNT_X8, 0xc);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_1_SAMP_ADAPT_CFG, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_FFE_TRAINING_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_FFE_TRAINING_0_FFE_TAP_EN, 0xf9ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_IDLE_DETECT_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MAX, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MIN, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS3_ANA_OVRDVAL_11_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw ,addr);
+ ((E56G__RXS3_ANA_OVRDVAL_11 *)&rdata)->ana_test_adc_clkgen_i = 0x0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_2_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw ,addr);
+ ((E56G__RXS0_ANA_OVRDEN_2 *)&rdata)->ovrd_en_ana_test_adc_clkgen_i = 0x0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_0_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_6_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 4,0, 0x6);
+ set_fields_e56(&rdata, 14,13, 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_BBCDR_VCOFILT_BYP_I, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_TEST_BBCDR_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_15_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 2,0, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_17_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_17_ANA_VGA2_BOOST_CSTM_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_3_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_ANABS_CONFIG_I, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_VGA2_BOOST_CSTM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_14_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_4_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_EYE_SCAN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_EYE_SCAN_1_EYE_SCAN_REF_TIMER, 0x400);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_RINGO_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 9, 4, 0x366);
+ wr32_ephy(hw, addr, rdata);
+ }
+
+ // PDIG Config master
+ addr = E56PHY_PMD_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_3_CTRL_FSM_TIMEOUT_X64K, 0x80);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_PMD_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_ON_PERIOD_X64K, 0x18);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_PERIOD_X512K, 0x3e);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_PMD_CFG_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_5_USE_RECENT_MARKER_OFFSET, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_CONT_ON_ADC_GAIN_CAL_ERR, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_DO_RX_ADC_OFST_CAL, 0x3);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_RX_ERR_ACTION_EN, 0x40);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST0_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST1_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST2_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST3_WAIT_CNT_X4096, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST4_WAIT_CNT_X4096, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST5_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST6_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST7_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST8_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST9_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST10_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST11_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST12_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST13_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST14_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST15_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST4_EN, 0x4bf);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST5_EN, 0xc4bf);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_8_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_8_TRAIN_ST7_EN, 0x47ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_12_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_12_TRAIN_ST15_EN, 0x67ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_13_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST0_DONE_EN, 0x8001);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST1_DONE_EN, 0x8002);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_14_TRAIN_ST3_DONE_EN, 0x8008);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_15_TRAIN_ST4_DONE_EN, 0x8004);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_17_TRAIN_ST8_DONE_EN, 0x20c0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_18_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_18_TRAIN_ST10_DONE_EN, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_29_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_29_TRAIN_ST15_DC_EN, 0x3f6d);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_33_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN0_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN1_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_34_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN2_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN3_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_KRT_TFSM_CFG_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X1000K, 0x49);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X8000K, 0x37);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_HOLDOFF_TIMER_X256K, 0x2f);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_FETX_FFE_TRAIN_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_FETX_FFE_TRAIN_CFG_0_KRT_FETX_INIT_FFE_CFG_2, 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ return 0;
+}
+
+u32
+txgbe_e56_cfg_25g(struct txgbe_hw *hw)
+{
+ u32 addr;
+ u32 rdata = 0;
+
+ addr = E56PHY_CMS_PIN_OVRDVAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_PIN_OVRDVAL_0_INT_PLL0_TX_SIGNAL_TYPE_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CMS_PIN_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_PIN_OVRDEN_0_OVRD_EN_PLL0_TX_SIGNAL_TYPE_I,
+ 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CMS_ANA_OVRDVAL_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_ANA_OVRDVAL_2_ANA_LCPLL_HF_VCO_SWING_CTRL_I,
+ 0xf);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CMS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_VCO_SWING_CTRL_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CMS_ANA_OVRDVAL_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 23, 0, 0x260000);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_HF_TEST_IN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_TXS_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_TXS_CFG_1_ADAPTATION_WAIT_CNT_X256, 0xf);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_WKUP_CNT_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTLDO_WKUP_CNT_X32, 0xff);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTDCC_WKUP_CNT_X32, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_PIN_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 27, 24, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_PIN_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_PIN_OVRDEN_0_OVRD_EN_TX0_EFUSE_BITS_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_ANA_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDVAL_1_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDEN_0_OVRD_EN_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ txgbe_e56_tx_ffe_cfg(hw, TXGBE_LINK_SPEED_25GB_FULL);
+
+ addr = E56PHY_RXS_RXS_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_DSER_DATA_SEL, 0x0);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_TRAIN_CLK_GATE_BYPASS_EN, 0x1fff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_1_PREDIV1, 0x700);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_1_TARGET_CNT1, 0x2418);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_OSC_RANGE_SEL1, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_VCO_CODE_INIT, 0x7fb);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_OSC_CURRENT_BOOST_EN1, 0x0);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_BBCDR_CURRENT_BOOST1, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_SDM_WIDTH, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_POSTLOCK,
+ 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_POSTLOCK,
+ 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BBCDR_RDY_CNT, 0x3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_PRELOCK, 0x7);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_POSTLOCK, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_INTL_CONFIG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_INTL_CONFIG_0_ADC_INTL2SLICE_DELAY1, 0x3333);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_INTL_CONFIG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_INTL_CONFIG_2_INTERLEAVER_HBW_DISABLE1, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_TXFFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_LTH, 0x56);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_UTH, 0x6a);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_TXFFE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_LTH, 0x1f8);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_UTH, 0xf0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_TXFFE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_LTH, 0x100);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_UTH, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_TXFFE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_LTH, 0x4);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_UTH, 0x37);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_TXFFE_TRAIN_MOD_TYPE, 0x38);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_FOM_18__ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56G__RXS0_FOM_18__DFE_COEFFL_HINT__MSB,
+ E56G__RXS0_FOM_18__DFE_COEFFL_HINT__LSB, 0x0);
+ /* change 0x90 to 0x0 to fix 25G link up keep when cable unplugged */
+ set_fields_e56(&rdata, E56G__RXS0_FOM_18__DFE_COEFFH_HINT__MSB,
+ E56G__RXS0_FOM_18__DFE_COEFFH_HINT__LSB, 0x0);
+ set_fields_e56(&rdata, E56G__RXS0_FOM_18__DFE_COEFF_HINT_LOAD__MSB,
+ E56G__RXS0_FOM_18__DFE_COEFF_HINT_LOAD__LSB, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_VGA_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_0_VGA_TARGET, 0x34);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_VGA_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT123, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT123, 0xa);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT0, 0x9);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT123, 0x9);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_1_LFEQ_LUT, 0x1ffffea);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P1,
+ S25G_PHY_RX_CTLE_TAP_FRACP1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P2,
+ S25G_PHY_RX_CTLE_TAP_FRACP2);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P3,
+ S25G_PHY_RX_CTLE_TAP_FRACP3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P1,
+ S25G_PHY_RX_CTLE_TAPWT_WEIGHT1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P2,
+ S25G_PHY_RX_CTLE_TAPWT_WEIGHT2);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P3,
+ S25G_PHY_RX_CTLE_TAPWT_WEIGHT3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_SLICE_DATA_AVG_CNT,
+ 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_DATA_AVG_CNT, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_FE_OFFSET_DAC_CLK_CNT_X8,
+ 0xc);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_1_SAMP_ADAPT_CFG, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_FFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_FFE_TRAINING_0_FFE_TAP_EN, 0xf9ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_IDLE_DETECT_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MAX, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MIN, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDVAL_11, ana_test_adc_clkgen_i, 0x0);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_2, ovrd_en_ana_test_adc_clkgen_i,
+ 0x0);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_0_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 4, 0, 0x0);
+ set_fields_e56(&rdata, 14, 13, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_BBCDR_VCOFILT_BYP_I,
+ 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_TEST_BBCDR_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 2, 0, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_17_ANA_VGA2_BOOST_CSTM_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_ANABS_CONFIG_I, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_VGA2_BOOST_CSTM_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_EYE_SCAN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_EYE_SCAN_1_EYE_SCAN_REF_TIMER, 0x400);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_RINGO_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 21, 12, 0x366);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_PMD_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_3_CTRL_FSM_TIMEOUT_X64K, 0x80);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_PMD_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_ON_PERIOD_X64K, 0x18);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_PERIOD_X512K, 0x3e);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_PMD_CFG_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_5_USE_RECENT_MARKER_OFFSET, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_CONT_ON_ADC_GAIN_CAL_ERR, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_DO_RX_ADC_OFST_CAL, 0x3);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_RX_ERR_ACTION_EN, 0x40);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST0_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST1_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST2_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST3_WAIT_CNT_X4096, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST4_WAIT_CNT_X4096, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST5_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST6_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST7_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST8_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST9_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST10_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST11_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST12_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST13_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST14_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST15_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST4_EN, 0x4bf);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST5_EN, 0xc4bf);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_8_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_8_TRAIN_ST7_EN, 0x47ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_12_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_12_TRAIN_ST15_EN, 0x67ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_13_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST0_DONE_EN, 0x8001);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST1_DONE_EN, 0x8002);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_14_TRAIN_ST3_DONE_EN, 0x8008);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_15_TRAIN_ST4_DONE_EN, 0x8004);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_17_TRAIN_ST8_DONE_EN, 0x20c0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_18_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_18_TRAIN_ST10_DONE_EN, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_29_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_29_TRAIN_ST15_DC_EN, 0x3f6d);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_33_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN0_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN1_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_34_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN2_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN3_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_KRT_TFSM_CFG_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X1000K, 0x49);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X8000K, 0x37);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_HOLDOFF_TIMER_X256K, 0x2f);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_FETX_FFE_TRAIN_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_FETX_FFE_TRAIN_CFG_0_KRT_FETX_INIT_FFE_CFG_2,
+ 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ return 0;
+}
+
+u32
+txgbe_e56_cfg_10g(struct txgbe_hw *hw)
+{
+ u32 addr;
+ u32 rdata = 0;
+
+ addr = E56G_CMS_ANA_OVRDVAL_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_CMS_ANA_OVRDVAL_7 *)&rdata)->ana_lcpll_lf_vco_swing_ctrl_i = 0xf;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_CMS_ANA_OVRDEN_1 *)&rdata)->ovrd_en_ana_lcpll_lf_vco_swing_ctrl_i = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G_CMS_ANA_OVRDVAL_9_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 23, 0, 0x260000);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_CMS_ANA_OVRDEN_1 *)&rdata)->ovrd_en_ana_lcpll_lf_test_in_i = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_TXS_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_TXS_CFG_1_ADAPTATION_WAIT_CNT_X256, 0xf);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_WKUP_CNT_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTLDO_WKUP_CNT_X32, 0xff);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTDCC_WKUP_CNT_X32, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_PIN_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 19, 16, 0x6);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_PIN_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_PIN_OVRDEN_0_OVRD_EN_TX0_EFUSE_BITS_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_ANA_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDVAL_1_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_TXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDEN_0_OVRD_EN_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ //Setting TX FFE
+ txgbe_e56_tx_ffe_cfg(hw, TXGBE_LINK_SPEED_10GB_FULL);
+
+ addr = E56PHY_RXS_RXS_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_DSER_DATA_SEL, 0x0);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_TRAIN_CLK_GATE_BYPASS_EN, 0x1fff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_OSC_CAL_N_CDR_0 *)&rdata)->prediv0 = 0xfa0;
+ ((E56G_RXS0_OSC_CAL_N_CDR_0 *)&rdata)->target_cnt0 = 0x203a;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->osc_range_sel0 = 0x2;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->vco_code_init = 0x7ff;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->osc_current_boost_en0 = 0x1;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->bbcdr_current_boost0 = 0x0;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_SDM_WIDTH, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_POSTLOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_POSTLOCK,
+ 0xc);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BBCDR_RDY_CNT, 0x3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_PRELOCK, 0x7);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_POSTLOCK, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_INTL_CONFIG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_INTL_CONFIG_0 *)&rdata)->adc_intl2slice_delay0 = 0x5555;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_INTL_CONFIG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_INTL_CONFIG_2 *)&rdata)->interleaver_hbw_disable0 = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_LTH, 0x56);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_UTH, 0x6a);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_LTH, 0x1e8);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_UTH, 0x78);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_LTH, 0x100);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_UTH, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_LTH, 0x4);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_UTH, 0x37);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_TXFFE_TRAIN_MOD_TYPE, 0x38);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_0_VGA_TARGET, 0x34);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT123, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT123, 0xa);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT0, 0x9);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT123, 0x9);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_1_LFEQ_LUT, 0x1ffffea);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P1,
+ S10G_PHY_RX_CTLE_TAP_FRACP1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P2,
+ S10G_PHY_RX_CTLE_TAP_FRACP2);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P3,
+ S10G_PHY_RX_CTLE_TAP_FRACP3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_CTLE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P1,
+ S10G_PHY_RX_CTLE_TAPWT_WEIGHT1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P2,
+ S10G_PHY_RX_CTLE_TAPWT_WEIGHT2);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P3,
+ S10G_PHY_RX_CTLE_TAPWT_WEIGHT3);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_SLICE_DATA_AVG_CNT,
+ 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_DATA_AVG_CNT, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_FE_OFFSET_DAC_CLK_CNT_X8,
+ 0xc);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_1_SAMP_ADAPT_CFG, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_FFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_FFE_TRAINING_0_FFE_TAP_EN, 0xf9ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_IDLE_DETECT_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MAX, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MIN, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDVAL_11, ana_test_adc_clkgen_i, 0x0);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_2, ovrd_en_ana_test_adc_clkgen_i,
+ 0x0);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_0_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 4, 0, 0x6);
+ set_fields_e56(&rdata, 14, 13, 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_BBCDR_VCOFILT_BYP_I,
+ 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_TEST_BBCDR_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 2, 0, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_17_ANA_VGA2_BOOST_CSTM_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_ANABS_CONFIG_I, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_VGA2_BOOST_CSTM_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDVAL_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_ANA_OVRDEN_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_EYE_SCAN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_EYE_SCAN_1_EYE_SCAN_REF_TIMER, 0x400);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS_RINGO_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 9, 4, 0x366);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_PMD_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_3_CTRL_FSM_TIMEOUT_X64K, 0x80);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_PMD_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_ON_PERIOD_X64K, 0x18);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_PERIOD_X512K, 0x3e);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_PMD_CFG_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_5_USE_RECENT_MARKER_OFFSET, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_CONT_ON_ADC_GAIN_CAL_ERR, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_DO_RX_ADC_OFST_CAL, 0x3);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_RX_ERR_ACTION_EN, 0x40);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST0_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST1_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST2_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST3_WAIT_CNT_X4096, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST4_WAIT_CNT_X4096, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST5_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST6_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST7_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST8_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST9_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST10_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST11_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST12_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST13_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST14_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST15_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST4_EN, 0x4bf);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST5_EN, 0xc4bf);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_8_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_8_TRAIN_ST7_EN, 0x47ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_12_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_12_TRAIN_ST15_EN, 0x67ff);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_13_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST0_DONE_EN, 0x8001);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST1_DONE_EN, 0x8002);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_14_TRAIN_ST3_DONE_EN, 0x8008);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_15_TRAIN_ST4_DONE_EN, 0x8004);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_17_TRAIN_ST8_DONE_EN, 0x20c0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_18_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_18_TRAIN_ST10_DONE_EN, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_29_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_29_TRAIN_ST15_DC_EN, 0x3f6d);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_33_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN0_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN1_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_CTRL_FSM_CFG_34_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN2_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN3_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_KRT_TFSM_CFG_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X1000K, 0x49);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X8000K, 0x37);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_HOLDOFF_TIMER_X256K, 0x2f);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_FETX_FFE_TRAIN_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_FETX_FFE_TRAIN_CFG_0_KRT_FETX_INIT_FFE_CFG_2,
+ 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ return 0;
+}
+
+static inline int
+txgbe_e56_rxs_osc_init_for_temp_track_range(struct txgbe_hw *hw, u32 speed)
+{
+ int status = 0;
+ unsigned int addr, rdata, timer;
+ int T = 40;
+ int RX_COARSE_MID_TD, CMVAR_RANGE_H = 0, CMVAR_RANGE_L = 0;
+ int OFFSET_CENTRE_RANGE_H, OFFSET_CENTRE_RANGE_L, RANGE_FINAL;
+ int i = 0;
+ int lane_num = 1;
+
+ txgbe_e56_get_temp(hw, &T);
+
+ for (i = 0; i < lane_num; i++) {
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_5_ANA_BBCDR_OSC_RANGE_SEL_I, CMVAR_RANGE_H);
+ wr32_ephy(hw, addr, rdata);
+ addr = E56PHY_RXS0_OVRDEN_0_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_0_OVRD_EN_RXS0_RX0_SAMP_CAL_DONE_O, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, (0x1 << i));
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ timer = 0;
+ while((rdata >> (i * 8) & 0x3f) != 0x9) {
+ usec_delay(500);
+ rdata = 0;
+ addr = E56PHY_INTR_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if(rdata & (0x100 << i))
+ break;
+
+ rdata = 0;
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ return -1;
+ }
+ }
+
+ rdata = 0;
+ addr = E56PHY_RXS_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ OFFSET_CENTRE_RANGE_H = (rdata >> 4) & 0xf;
+ if(OFFSET_CENTRE_RANGE_H > RX_COARSE_MID_TD) {
+ OFFSET_CENTRE_RANGE_H = OFFSET_CENTRE_RANGE_H - RX_COARSE_MID_TD;
+ } else {
+ OFFSET_CENTRE_RANGE_H = RX_COARSE_MID_TD - OFFSET_CENTRE_RANGE_H;
+ }
+
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ timer = 0;
+ while(1) {
+ usec_delay(500);
+ rdata = 0;
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if(((rdata >> (i * 8)) & 0x3f) == 0x21) { break; }
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ return -1;
+ }
+ }
+
+ usec_delay(500);
+ rdata = 0;
+ addr = E56PHY_INTR_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+
+ usec_delay(500);
+ addr = E56PHY_INTR_0_ADDR;
+ wr32_ephy(hw, addr, rdata);
+
+ usec_delay(500);
+ rdata = 0;
+ addr = E56PHY_INTR_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_5_ANA_BBCDR_OSC_RANGE_SEL_I, CMVAR_RANGE_L);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_0_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_BBCDR_OSC_RANGE_SEL_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_0_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_0_RXS0_RX0_SAMP_CAL_DONE_O, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDEN_0_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_0_OVRD_EN_RXS0_RX0_SAMP_CAL_DONE_O, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, (0x1 << i));
+ wr32_ephy(hw, addr, rdata);
+
+ timer = 0;
+ while(((rdata >> (i * 8)) & 0x3f) != 0x9) {
+ usec_delay(500);
+ rdata = 0;
+ addr = E56PHY_INTR_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if((rdata & 0x100) == 0x100)
+ break;
+
+ rdata = 0;
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ return -1;
+ }
+ }
+
+ rdata = 0;
+ addr = E56PHY_RXS_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ OFFSET_CENTRE_RANGE_L = (rdata >> 4) & 0xf;
+ if(OFFSET_CENTRE_RANGE_L > RX_COARSE_MID_TD) {
+ OFFSET_CENTRE_RANGE_L = OFFSET_CENTRE_RANGE_L - RX_COARSE_MID_TD;
+ } else {
+ OFFSET_CENTRE_RANGE_L = RX_COARSE_MID_TD - OFFSET_CENTRE_RANGE_L;
+ }
+ if (OFFSET_CENTRE_RANGE_L < OFFSET_CENTRE_RANGE_H) {
+ RANGE_FINAL = CMVAR_RANGE_L;
+ }
+ else {
+ RANGE_FINAL = CMVAR_RANGE_H;
+ }
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ timer = 0;
+ while(1) {
+ usec_delay(500);
+ rdata = 0;
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if(((rdata >> (i * 8)) & 0x3f) == 0x21) { break; }
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ return -1;
+ }
+ }
+
+ usec_delay(500);
+ rdata = 0;
+ addr = E56PHY_INTR_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+ wr32_ephy(hw, addr, rdata);
+
+ usec_delay(500);
+ rdata = 0;
+ addr = E56PHY_INTR_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_5_ANA_BBCDR_OSC_RANGE_SEL_I, RANGE_FINAL);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDEN_0_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_0_OVRD_EN_RXS0_RX0_SAMP_CAL_DONE_O, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ }
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if (speed == TXGBE_LINK_SPEED_40GB_FULL)
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0xf);
+ else
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ return status;
+}
+
+static int txgbe_e56_set_rxs_ufine_le_max_40g(struct txgbe_hw *hw, u32 speed)
+{
+ int status = 0;
+ unsigned int rdata;
+ unsigned int ULTRAFINE_CODE;
+ int i = 0;
+ unsigned int CMVAR_UFINE_MAX = 0;
+ u32 addr;
+
+ for (i = 0; i < 4; i++) {
+ if (speed == TXGBE_LINK_SPEED_10GB_FULL || speed == TXGBE_LINK_SPEED_40GB_FULL ) {
+ CMVAR_UFINE_MAX = S10G_CMVAR_UFINE_MAX;
+ }
+ else if (speed == TXGBE_LINK_SPEED_25GB_FULL) {
+ CMVAR_UFINE_MAX = S25G_CMVAR_UFINE_MAX;
+ }
+
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ ULTRAFINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i);
+
+ while (ULTRAFINE_CODE > CMVAR_UFINE_MAX) {
+ ULTRAFINE_CODE = ULTRAFINE_CODE - 1;
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i) = ULTRAFINE_CODE;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+
+ msleep(10);
+ }
+ }
+ return status;
+}
+
+
+static inline
+int txgbe_e56_set_rxs_ufine_le_max(struct txgbe_hw *hw, u32 speed)
+{
+ int status = 0;
+ unsigned int rdata;
+ unsigned int ULTRAFINE_CODE;
+
+ unsigned int CMVAR_UFINE_MAX = 0;
+
+ if (speed == TXGBE_LINK_SPEED_10GB_FULL)
+ CMVAR_UFINE_MAX = S10G_CMVAR_UFINE_MAX;
+ else if (speed == TXGBE_LINK_SPEED_25GB_FULL)
+ CMVAR_UFINE_MAX = S25G_CMVAR_UFINE_MAX;
+
+ /* a. Assign software defined variables as below */
+ /* ii. ULTRAFINE_CODE = ALIAS::RXS::ULTRAFINE */
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ ULTRAFINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i);
+
+ /* b. Perform the below logic sequence */
+ while (ULTRAFINE_CODE > CMVAR_UFINE_MAX) {
+ ULTRAFINE_CODE = ULTRAFINE_CODE - 1;
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i,
+ ULTRAFINE_CODE);
+ /* Set ovrd_en=1 to overide ASIC value */
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i,
+ 1);
+ /* Wait until 1milliseconds or greater */
+ msleep(10);
+ }
+
+ return status;
+}
+
+int txgbe_e56_rx_rd_second_code_40g(struct txgbe_hw *hw, int *SECOND_CODE, int lane)
+{
+ int status = 0, i, N, median;
+ unsigned int rdata;
+ u32 addr;
+ int arraySize, RXS_BBCDR_SECOND_ORDER_ST[5];
+
+ //Set ovrd_en=0 to read ASIC value
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (lane * E56PHY_RXS_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_int_cstm_i) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ N =5;
+ for (i=0; i<N; i=i+1) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (lane * E56PHY_RXS_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ RXS_BBCDR_SECOND_ORDER_ST[i] = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_int_cstm_i);
+ usec_delay(100);
+ }
+
+ arraySize = sizeof(RXS_BBCDR_SECOND_ORDER_ST) / sizeof(RXS_BBCDR_SECOND_ORDER_ST[0]);
+ qsort(RXS_BBCDR_SECOND_ORDER_ST, arraySize, sizeof(int), compare);
+
+ median = ( (N+1)/2 ) -1;
+ *SECOND_CODE = RXS_BBCDR_SECOND_ORDER_ST[median];
+
+ return status;
+}
+
+int txgbe_e56_rx_rd_second_code(struct txgbe_hw *hw, int *SECOND_CODE)
+{
+ int status = 0, i, N, median;
+ unsigned int rdata;
+ int arraySize, RXS_BBCDR_SECOND_ORDER_ST[5];
+
+
+ /* Set ovrd_en=0 to read ASIC value */
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_int_cstm_i, 0);
+
+ /*
+ * As status update from RXS hardware is asynchronous to read status
+ * of SECOND_ORDER, follow sequence mentioned below.
+ */
+ N = 5;
+ for (i = 0; i < N; i = i + 1) {
+ /* set RXS_BBCDR_SECOND_ORDER_ST[i] = RXS::ANA_OVRDVAL[5]::ana_bbcdr_int_cstm_i[4:0] */
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ RXS_BBCDR_SECOND_ORDER_ST[i] = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_int_cstm_i);
+ usec_delay(100);
+ }
+
+ /* sort array RXS_BBCDR_SECOND_ORDER_ST[i] */
+ arraySize = sizeof(RXS_BBCDR_SECOND_ORDER_ST) / sizeof(
+ RXS_BBCDR_SECOND_ORDER_ST[0]);
+ qsort(RXS_BBCDR_SECOND_ORDER_ST, arraySize, sizeof(int), compare);
+
+ median = ((N + 1) / 2) -1;
+ *SECOND_CODE = RXS_BBCDR_SECOND_ORDER_ST[median];
+
+ return status;
+}
+
+/*
+ * 2.3.4 RXS post CDR lock temperature tracking sequence
+ *
+ * Below sequence must be run before the temperature drifts by >5degC
+ * after the CDR locks for the first time or after the ious time this
+ * sequence was run. It is recommended to call this sequence periodically
+ * (eg: once every 100ms) or trigger sequence if the temperature drifts
+ * by >=5degC. Temperature must be read from an on-die temperature sensor.
+ */
+static inline
+int txgbe_phy_rxs_post_cdr_lock_temp_track_seq_40g(struct txgbe_hw *hw, u32 speed)
+{
+ int status = 0;
+ unsigned int rdata;
+ int SECOND_CODE;
+ int COARSE_CODE;
+ int FINE_CODE;
+ int ULTRAFINE_CODE;
+
+ int CMVAR_SEC_LOW_TH ;
+ int CMVAR_UFINE_MAX = 0;
+ int CMVAR_FINE_MAX ;
+ int CMVAR_UFINE_UMAX_WRAP = 0;
+ int CMVAR_COARSE_MAX ;
+ int CMVAR_UFINE_FMAX_WRAP = 0;
+ int CMVAR_FINE_FMAX_WRAP = 0;
+ int CMVAR_SEC_HIGH_TH ;
+ int CMVAR_UFINE_MIN ;
+ int CMVAR_FINE_MIN ;
+ int CMVAR_UFINE_UMIN_WRAP ;
+ int CMVAR_COARSE_MIN ;
+ int CMVAR_UFINE_FMIN_WRAP ;
+ int CMVAR_FINE_FMIN_WRAP ;
+ int i;
+ u32 addr;
+ for (i = 0; i < 4; i++){
+ if(speed == TXGBE_LINK_SPEED_10GB_FULL || speed == TXGBE_LINK_SPEED_40GB_FULL) {
+ CMVAR_SEC_LOW_TH = S10G_CMVAR_SEC_LOW_TH ;
+ CMVAR_UFINE_MAX = S10G_CMVAR_UFINE_MAX ;
+ CMVAR_FINE_MAX = S10G_CMVAR_FINE_MAX ;
+ CMVAR_UFINE_UMAX_WRAP = S10G_CMVAR_UFINE_UMAX_WRAP;
+ CMVAR_COARSE_MAX = S10G_CMVAR_COARSE_MAX ;
+ CMVAR_UFINE_FMAX_WRAP = S10G_CMVAR_UFINE_FMAX_WRAP;
+ CMVAR_FINE_FMAX_WRAP = S10G_CMVAR_FINE_FMAX_WRAP ;
+ CMVAR_SEC_HIGH_TH = S10G_CMVAR_SEC_HIGH_TH ;
+ CMVAR_UFINE_MIN = S10G_CMVAR_UFINE_MIN ;
+ CMVAR_FINE_MIN = S10G_CMVAR_FINE_MIN ;
+ CMVAR_UFINE_UMIN_WRAP = S10G_CMVAR_UFINE_UMIN_WRAP;
+ CMVAR_COARSE_MIN = S10G_CMVAR_COARSE_MIN ;
+ CMVAR_UFINE_FMIN_WRAP = S10G_CMVAR_UFINE_FMIN_WRAP;
+ CMVAR_FINE_FMIN_WRAP = S10G_CMVAR_FINE_FMIN_WRAP ;
+ }
+ else if (speed == TXGBE_LINK_SPEED_25GB_FULL) {
+ CMVAR_SEC_LOW_TH = S25G_CMVAR_SEC_LOW_TH ;
+ CMVAR_UFINE_MAX = S25G_CMVAR_UFINE_MAX ;
+ CMVAR_FINE_MAX = S25G_CMVAR_FINE_MAX ;
+ CMVAR_UFINE_UMAX_WRAP = S25G_CMVAR_UFINE_UMAX_WRAP;
+ CMVAR_COARSE_MAX = S25G_CMVAR_COARSE_MAX ;
+ CMVAR_UFINE_FMAX_WRAP = S25G_CMVAR_UFINE_FMAX_WRAP;
+ CMVAR_FINE_FMAX_WRAP = S25G_CMVAR_FINE_FMAX_WRAP ;
+ CMVAR_SEC_HIGH_TH = S25G_CMVAR_SEC_HIGH_TH ;
+ CMVAR_UFINE_MIN = S25G_CMVAR_UFINE_MIN ;
+ CMVAR_FINE_MIN = S25G_CMVAR_FINE_MIN ;
+ CMVAR_UFINE_UMIN_WRAP = S25G_CMVAR_UFINE_UMIN_WRAP;
+ CMVAR_COARSE_MIN = S25G_CMVAR_COARSE_MIN ;
+ CMVAR_UFINE_FMIN_WRAP = S25G_CMVAR_UFINE_FMIN_WRAP;
+ CMVAR_FINE_FMIN_WRAP = S25G_CMVAR_FINE_FMIN_WRAP ;
+ }
+
+ status |= txgbe_e56_rx_rd_second_code_40g(hw, &SECOND_CODE, i);
+
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ COARSE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i);
+ FINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i);
+ ULTRAFINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i);
+
+ if (SECOND_CODE <= CMVAR_SEC_LOW_TH) {
+ if (ULTRAFINE_CODE < CMVAR_UFINE_MAX) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i) = ULTRAFINE_CODE + 1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else if (FINE_CODE < CMVAR_FINE_MAX) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i) = CMVAR_UFINE_UMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = FINE_CODE + 1;
+ wr32_ephy(hw, addr, rdata);
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else if (COARSE_CODE < CMVAR_COARSE_MAX) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i) = CMVAR_UFINE_FMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = CMVAR_FINE_FMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i) = COARSE_CODE + 1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_coarse_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else {
+ ;
+ }
+ } else if (SECOND_CODE >= CMVAR_SEC_HIGH_TH) {
+ if (ULTRAFINE_CODE > CMVAR_UFINE_MIN) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i) = ULTRAFINE_CODE - 1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else if (FINE_CODE > CMVAR_FINE_MIN) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i) = CMVAR_UFINE_UMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = FINE_CODE - 1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else if (COARSE_CODE > CMVAR_COARSE_MIN) {
+ addr = E56G__RXS0_ANA_OVRDVAL_5_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i) = CMVAR_UFINE_FMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = CMVAR_FINE_FMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i) = COARSE_CODE - 1;
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR + (E56PHY_RXS_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_coarse_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ wr32_ephy(hw, addr, rdata);
+ } else {
+ ;
+ }
+ }
+ }
+ return status;
+}
+
+/*
+ * 2.3.4 RXS post CDR lock temperature tracking sequence
+ *
+ * Below sequence must be run before the temperature drifts by >5degC
+ * after the CDR locks for the first time or after the ious time this
+ * sequence was run. It is recommended to call this sequence periodically
+ * (eg: once every 100ms) or trigger sequence if the temperature drifts
+ * by >=5degC. Temperature must be read from an on-die temperature sensor.
+ */
+
+int txgbe_temp_track_seq(struct txgbe_hw *hw, u32 speed)
+{
+ int status = 0;
+ unsigned int rdata;
+ int SECOND_CODE;
+ int COARSE_CODE;
+ int FINE_CODE;
+ int ULTRAFINE_CODE;
+
+ int CMVAR_SEC_LOW_TH ;
+ int CMVAR_UFINE_MAX = 0;
+ int CMVAR_FINE_MAX ;
+ int CMVAR_UFINE_UMAX_WRAP = 0;
+ int CMVAR_COARSE_MAX ;
+ int CMVAR_UFINE_FMAX_WRAP = 0;
+ int CMVAR_FINE_FMAX_WRAP = 0;
+ int CMVAR_SEC_HIGH_TH ;
+ int CMVAR_UFINE_MIN ;
+ int CMVAR_FINE_MIN ;
+ int CMVAR_UFINE_UMIN_WRAP ;
+ int CMVAR_COARSE_MIN ;
+ int CMVAR_UFINE_FMIN_WRAP ;
+ int CMVAR_FINE_FMIN_WRAP ;
+ int temperature;
+
+ if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
+ CMVAR_SEC_LOW_TH = S10G_CMVAR_SEC_LOW_TH;
+ CMVAR_UFINE_MAX = S10G_CMVAR_UFINE_MAX;
+ CMVAR_FINE_MAX = S10G_CMVAR_FINE_MAX;
+ CMVAR_UFINE_UMAX_WRAP = S10G_CMVAR_UFINE_UMAX_WRAP;
+ CMVAR_COARSE_MAX = S10G_CMVAR_COARSE_MAX;
+ CMVAR_UFINE_FMAX_WRAP = S10G_CMVAR_UFINE_FMAX_WRAP;
+ CMVAR_FINE_FMAX_WRAP = S10G_CMVAR_FINE_FMAX_WRAP;
+ CMVAR_SEC_HIGH_TH = S10G_CMVAR_SEC_HIGH_TH;
+ CMVAR_UFINE_MIN = S10G_CMVAR_UFINE_MIN;
+ CMVAR_FINE_MIN = S10G_CMVAR_FINE_MIN;
+ CMVAR_UFINE_UMIN_WRAP = S10G_CMVAR_UFINE_UMIN_WRAP;
+ CMVAR_COARSE_MIN = S10G_CMVAR_COARSE_MIN;
+ CMVAR_UFINE_FMIN_WRAP = S10G_CMVAR_UFINE_FMIN_WRAP;
+ CMVAR_FINE_FMIN_WRAP = S10G_CMVAR_FINE_FMIN_WRAP ;
+ } else if (speed == TXGBE_LINK_SPEED_25GB_FULL) {
+ CMVAR_SEC_LOW_TH = S25G_CMVAR_SEC_LOW_TH;
+ CMVAR_UFINE_MAX = S25G_CMVAR_UFINE_MAX;
+ CMVAR_FINE_MAX = S25G_CMVAR_FINE_MAX;
+ CMVAR_UFINE_UMAX_WRAP = S25G_CMVAR_UFINE_UMAX_WRAP;
+ CMVAR_COARSE_MAX = S25G_CMVAR_COARSE_MAX;
+ CMVAR_UFINE_FMAX_WRAP = S25G_CMVAR_UFINE_FMAX_WRAP;
+ CMVAR_FINE_FMAX_WRAP = S25G_CMVAR_FINE_FMAX_WRAP;
+ CMVAR_SEC_HIGH_TH = S25G_CMVAR_SEC_HIGH_TH;
+ CMVAR_UFINE_MIN = S25G_CMVAR_UFINE_MIN;
+ CMVAR_FINE_MIN = S25G_CMVAR_FINE_MIN;
+ CMVAR_UFINE_UMIN_WRAP = S25G_CMVAR_UFINE_UMIN_WRAP;
+ CMVAR_COARSE_MIN = S25G_CMVAR_COARSE_MIN;
+ CMVAR_UFINE_FMIN_WRAP = S25G_CMVAR_UFINE_FMIN_WRAP;
+ CMVAR_FINE_FMIN_WRAP = S25G_CMVAR_FINE_FMIN_WRAP;
+ } else {
+ return 0;
+ }
+
+ status = txgbe_e56_get_temp(hw, &temperature);
+ if (status)
+ temperature = DEFAULT_TEMP;
+
+ hw->temperature = temperature;
+
+ /*
+ * Assign software defined variables as below
+ * a. SECOND_CODE = ALIAS::RXS::SECOND_ORDER
+ */
+ status |= txgbe_e56_rx_rd_second_code(hw, &SECOND_CODE);
+
+ /*
+ * b. COARSE_CODE = ALIAS::RXS::COARSE
+ * c. FINE_CODE = ALIAS::RXS::FINE
+ * d. ULTRAFINE_CODE = ALIAS::RXS::ULTRAFINE
+ */
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ COARSE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i);
+ FINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i);
+ ULTRAFINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i);
+
+ if (SECOND_CODE <= CMVAR_SEC_LOW_TH) {
+ if (ULTRAFINE_CODE < CMVAR_UFINE_MAX) {
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i,
+ ULTRAFINE_CODE + 1);
+ /* Set ovrd_en=1 to overide ASIC value */
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (FINE_CODE < CMVAR_FINE_MAX) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_UMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = FINE_CODE + 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ /*
+ * Note: All two of above code updates should be written in a single register write
+ * Set ovrd_en=1 to overide ASIC value
+ */
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (COARSE_CODE < CMVAR_COARSE_MAX) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_FMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = CMVAR_FINE_FMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i) = COARSE_CODE + 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ /*
+ * Note: All three of above code updates should be written in a single register write
+ * Set ovrd_en=1 to overide ASIC value
+ */
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_coarse_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else {
+ ;
+ }
+ } else if (SECOND_CODE >= CMVAR_SEC_HIGH_TH) {
+ if (ULTRAFINE_CODE > CMVAR_UFINE_MIN) {
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i,
+ ULTRAFINE_CODE - 1);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (FINE_CODE > CMVAR_FINE_MIN) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_UMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = FINE_CODE - 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (COARSE_CODE > CMVAR_COARSE_MIN) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_FMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = CMVAR_FINE_FMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i) = COARSE_CODE - 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_coarse_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else {
+ ;
+ }
+ }
+
+ return status;
+}
+
+static inline int
+txgbe_e56_ctle_bypass_seq(struct txgbe_hw *hw, u32 speed)
+{
+ int status = 0;
+ unsigned int rdata;
+
+
+ /* 1. Program the following RXS registers as mentioned below. */
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+
+ /* 2. Program the following PDIG registers as mentioned below. */
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDVAL_1);
+
+ EPHY_RREG(E56G__PMD_RXS0_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDEN_1);
+
+ if (speed == TXGBE_LINK_SPEED_40GB_FULL) {
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS1_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS2_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS3_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+
+ EPHY_RREG(E56G__PMD_RXS1_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDVAL_1, rxs1_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDVAL_1, rxs1_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS1_OVRDVAL_1);
+ EPHY_RREG(E56G__PMD_RXS2_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDVAL_1, rxs2_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDVAL_1, rxs2_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS2_OVRDVAL_1);
+ EPHY_RREG(E56G__PMD_RXS3_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDVAL_1, rxs3_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDVAL_1, rxs3_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS3_OVRDVAL_1);
+
+ EPHY_RREG(E56G__PMD_RXS1_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDEN_1, ovrd_en_rxs1_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS1_OVRDEN_1, ovrd_en_rxs1_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS1_OVRDEN_1);
+ EPHY_RREG(E56G__PMD_RXS2_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDEN_1, ovrd_en_rxs2_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS2_OVRDEN_1, ovrd_en_rxs2_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS2_OVRDEN_1);
+ EPHY_RREG(E56G__PMD_RXS3_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDEN_1, ovrd_en_rxs3_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS3_OVRDEN_1, ovrd_en_rxs3_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS3_OVRDEN_1);
+
+ }
+ return status;
+}
+
+static int txgbe_e56_rxs_calib_adapt_seq_40G(struct txgbe_hw *hw, u32 speed)
+{
+ int status = 0, i, j;
+ u32 addr, timer;
+ u32 rdata = 0x0;
+ u32 bypassCtle = true;
+
+ for (i = 0; i < 4; i++) {
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_2_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_OFST_ADAPT_EN_I , 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_2_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_GAIN_ADAPT_EN_I , 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_EN_I , 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_DONE_O, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_DONE_O , 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_2_ADDR + (i * E56PHY_PMD_RX_OFFSET);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_INTL_ADAPT_EN_I , 0x1);
+ wr32_ephy(hw, addr, rdata);
+ }
+
+ if (bypassCtle == 1)
+ txgbe_e56_ctle_bypass_seq(hw, speed);
+
+ txgbe_e56_rxs_osc_init_for_temp_track_range(hw, speed);
+
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ timer = 0;
+ rdata = 0;
+ while(EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx0_st) != E56PHY_RX_RDY_ST &&
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx1_st) != E56PHY_RX_RDY_ST &&
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx2_st) != E56PHY_RX_RDY_ST &&
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx3_st) != E56PHY_RX_RDY_ST) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT){
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ return TXGBE_ERR_TIMEOUT;
+ }
+ }
+
+ rdata = 0;
+ timer = 0;
+ while(EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_cdr_rdy_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ return TXGBE_ERR_TIMEOUT;
+ }
+
+ rdata = 0;
+ timer = 0;
+ while(EPHY_XFLD(E56G__PMD_RXS1_OVRDVAL_1, rxs1_rx0_cdr_rdy_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS1_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ return TXGBE_ERR_TIMEOUT;
+ }
+ rdata = 0;
+ timer = 0;
+ while(EPHY_XFLD(E56G__PMD_RXS2_OVRDVAL_1, rxs2_rx0_cdr_rdy_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS2_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ return TXGBE_ERR_TIMEOUT;
+ }
+
+ rdata = 0;
+ timer = 0;
+ while(EPHY_XFLD(E56G__PMD_RXS3_OVRDVAL_1, rxs3_rx0_cdr_rdy_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS3_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ return TXGBE_ERR_TIMEOUT;
+ }
+
+ for (i = 0; i < 4; i++) {
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_VGA_TRAIN_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_VGA_TRAIN_EN_I , 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_CTLE_TRAIN_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_CTLE_TRAIN_EN_I , 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_DONE_O , 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ timer = 0;
+ while(((rdata >> E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_DONE_O_LSB) & 1) != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(1000);
+
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ }
+ }
+
+ for(j = 0; j < 16; j++) {
+ //a. ALIAS::RXS::ADC_OFST_ADAPT_EN = 0b1
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__PMD_RXS0_OVRDEN_2_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_2, ovrd_en_rxs0_rx0_adc_ofst_adapt_done_o) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ addr = E56G__PMD_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ timer = 0;
+ while(EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_adc_ofst_adapt_done_o) != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ }
+ }
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56G__PMD_RXS0_OVRDEN_2_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_2, ovrd_en_rxs0_rx0_adc_ofst_adapt_done_o) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ timer = 0;
+ addr = E56G__PMD_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ while(EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_adc_gain_adapt_done_o) != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ }
+ }
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ }
+ addr = E56G__PMD_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_vga_train_done_o) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ timer = 0;
+ addr = E56G__PMD_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ while(EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_vga_train_done_o) != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ }
+ }
+
+ if(bypassCtle == 0) {
+ addr = E56G__PMD_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_done_o) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ timer = 0;
+ addr = E56G__PMD_RXS0_OVRDVAL_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ while(EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_done_o) != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ }
+ }
+ }
+
+ addr = E56G__PMD_RXS0_OVRDEN_1_ADDR + (E56PHY_PMD_RX_OFFSET * i);
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_vga_train_en_i) = 0;
+ if(bypassCtle == 0) {
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_en_i) = 0;
+ }
+ wr32_ephy(hw, addr, rdata);
+ }
+ return status;
+}
+static inline int
+txgbe_e56_rxs_calib_adapt_seq(struct txgbe_hw *hw, u32 speed)
+{
+ int status = 0, i;
+ u32 addr, timer;
+ u32 rdata = 0x0;
+ u32 bypassCtle = 1;
+
+ if (hw->phy.sfp_type == txgbe_sfp_type_25g_da_cu_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_da_cu_core1)
+ bypassCtle = 0;
+
+ if (hw->mac.type == txgbe_mac_aml) {
+ msleep(350);
+ rdata = rd32(hw, TXGBE_GPIOEXT);
+ if (rdata & (TXGBE_SFP1_MOD_ABS_LS | TXGBE_SFP1_RX_LOS_LS)) {
+ return TXGBE_ERR_PHY_INIT_NOT_DONE;
+ }
+ }
+
+ rdata = 0;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_OFST_ADAPT_EN_I
+ , 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_GAIN_ADAPT_EN_I
+ , 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_EN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_DONE_O, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_DONE_O
+ , 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_INTL_ADAPT_EN_I
+ , 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ if (bypassCtle == 1)
+ txgbe_e56_ctle_bypass_seq(hw, speed);
+
+ /*
+ * 2. Follow sequence described in 2.3.2 RXS Osc Initialization for temperature
+ * tracking range here. RXS would be enabled at the end of this sequence. For the case
+ * when PAM4 KR training is not enabled (including PAM4 mode without KR training),
+ * wait until ALIAS::PDIG::CTRL_FSM_RX_ST would return RX_TRAIN_15_ST (RX_RDY_ST).
+ */
+ txgbe_e56_rxs_osc_init_for_temp_track_range(hw, speed);
+
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ timer = 0;
+ rdata = 0;
+ while (EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0,
+ ctrl_fsm_rx0_st) != E56PHY_RX_RDY_ST) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(500);
+ EPHY_RREG(E56G__PMD_CTRL_FSM_RX_STAT_0);
+ if (timer++ > PHYINIT_TIMEOUT) {
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ return TXGBE_ERR_TIMEOUT;
+ }
+ }
+
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_cdr_rdy_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ return TXGBE_ERR_TIMEOUT;
+ }
+
+ /*
+ * 4. Disable VGA and CTLE training so that they don't interfere with ADC calibration
+ * a. Set ALIAS::RXS::VGA_TRAIN_EN = 0b0
+ */
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_VGA_TRAIN_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_VGA_TRAIN_EN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* b. Set ALIAS::RXS::CTLE_TRAIN_EN = 0b0 */
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_CTLE_TRAIN_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_CTLE_TRAIN_EN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /*
+ * 5. Perform ADC interleaver calibration
+ * a. Remove the OVERRIDE on ALIAS::RXS::ADC_INTL_CAL_DONE
+ */
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_DONE_O
+ , 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ timer = 0;
+ while (((rdata >> E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_DONE_O_LSB) & 1)
+ != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(1000);
+ if (timer++ > PHYINIT_TIMEOUT)
+ break;
+ }
+
+ /*
+ * 6. Perform ADC offset adaptation and ADC gain adaptation,
+ * repeat them a few times and after that keep it disabled.
+ */
+ for (i = 0; i < 16; i++) {
+ //a. ALIAS::RXS::ADC_OFST_ADAPT_EN = 0b1
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ //b. Wait for 1ms or greater
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_2,
+ ovrd_en_rxs0_rx0_adc_ofst_adapt_done_o, 0);
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1,
+ rxs0_rx0_adc_ofst_adapt_done_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ break;
+ }
+
+ /* c. ALIAS::RXS::ADC_OFST_ADAPT_EN = 0b0 */
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ /* d. ALIAS::RXS::ADC_GAIN_ADAPT_EN = 0b1 */
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* e. Wait for 1ms or greater */
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_2,
+ ovrd_en_rxs0_rx0_adc_ofst_adapt_done_o, 0);
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1,
+ rxs0_rx0_adc_gain_adapt_done_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ break;
+ }
+
+ /* f. ALIAS::RXS::ADC_GAIN_ADAPT_EN = 0b0 */
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ }
+ /* g. Repeat #a to #f total 16 times */
+
+ /*
+ * 7. Perform ADC interleaver adaptation for 10ms or greater, and after that disable it
+ * a. ALIAS::RXS::ADC_INTL_ADAPT_EN = 0b1
+ */
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ /* b. Wait for 10ms or greater */
+ msleep(10);
+
+ /* c. ALIAS::RXS::ADC_INTL_ADAPT_EN = 0b0 */
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_2,
+ ovrd_en_rxs0_rx0_adc_intl_adapt_en_i, 0);
+
+ /*
+ * 8. Now re-enable VGA and CTLE trainings, so that it continues to adapt tracking changes in temperature or voltage
+ * <1> Set ALIAS::RXS::VGA_TRAIN_EN = 0b1
+ * Set ALIAS::RXS::CTLE_TRAIN_EN = 0b1
+ */
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_vga_train_en_i) = 1;
+ if (bypassCtle == 0)
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_en_i) = 1;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDVAL_1);
+
+ /*
+ * <2> wait for ALIAS::RXS::VGA_TRAIN_DONE = 1
+ * wait for ALIAS::RXS::CTLE_TRAIN_DONE = 1
+ */
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_1,
+ ovrd_en_rxs0_rx0_vga_train_done_o, 0);
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_vga_train_done_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ break;
+ }
+
+ if (bypassCtle == 0) {
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_1,
+ ovrd_en_rxs0_rx0_ctle_train_done_o, 0);
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_done_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(500);
+ if (timer++ > PHYINIT_TIMEOUT)
+ break;
+ }
+ }
+
+ /* a. Remove the OVERRIDE on ALIAS::RXS::VGA_TRAIN_EN */
+ EPHY_RREG(E56G__PMD_RXS0_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_vga_train_en_i) = 0;
+ /* b. Remove the OVERRIDE on ALIAS::RXS::CTLE_TRAIN_EN */
+ if (bypassCtle == 0)
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_en_i) = 0;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDEN_1);
+
+ return status;
+}
+
+static inline u32
+txgbe_e56_cfg_temp(struct txgbe_hw *hw)
+{
+ u32 status;
+ u32 value;
+ int temp;
+
+ status = txgbe_e56_get_temp(hw, &temp);
+ if (status)
+ temp = DEFAULT_TEMP;
+
+ if (temp < DEFAULT_TEMP) {
+ value = rd32_ephy(hw, CMS_ANA_OVRDEN0);
+ set_fields_e56(&value, 25, 25, 0x1);
+ wr32_ephy(hw, CMS_ANA_OVRDEN0, value);
+
+ value = rd32_ephy(hw, CMS_ANA_OVRDVAL2);
+ set_fields_e56(&value, 20, 16, 0x1);
+ wr32_ephy(hw, CMS_ANA_OVRDVAL2, value);
+
+ value = rd32_ephy(hw, CMS_ANA_OVRDEN1);
+ set_fields_e56(&value, 12, 12, 0x1);
+ wr32_ephy(hw, CMS_ANA_OVRDEN1, value);
+
+ value = rd32_ephy(hw, CMS_ANA_OVRDVAL7);
+ set_fields_e56(&value, 8, 4, 0x1);
+ wr32_ephy(hw, CMS_ANA_OVRDVAL7, value);
+ } else if (temp > HIGH_TEMP) {
+ value = rd32_ephy(hw, CMS_ANA_OVRDEN0);
+ set_fields_e56(&value, 25, 25, 0x1);
+ wr32_ephy(hw, CMS_ANA_OVRDEN0, value);
+
+ value = rd32_ephy(hw, CMS_ANA_OVRDVAL2);
+ set_fields_e56(&value, 20, 16, 0x3);
+ wr32_ephy(hw, CMS_ANA_OVRDVAL2, value);
+
+ value = rd32_ephy(hw, CMS_ANA_OVRDEN1);
+ set_fields_e56(&value, 12, 12, 0x1);
+ wr32_ephy(hw, CMS_ANA_OVRDEN1, value);
+
+ value = rd32_ephy(hw, CMS_ANA_OVRDVAL7);
+ set_fields_e56(&value, 8, 4, 0x3);
+ wr32_ephy(hw, CMS_ANA_OVRDVAL7, value);
+ } else {
+ value = rd32_ephy(hw, CMS_ANA_OVRDEN1);
+ set_fields_e56(&value, 4, 4, 0x1);
+ wr32_ephy(hw, CMS_ANA_OVRDEN1, value);
+
+ value = rd32_ephy(hw, CMS_ANA_OVRDVAL4);
+ set_fields_e56(&value, 24, 24, 0x1);
+ set_fields_e56(&value, 31, 29, 0x4);
+ wr32_ephy(hw, CMS_ANA_OVRDVAL4, value);
+
+ value = rd32_ephy(hw, CMS_ANA_OVRDVAL5);
+ set_fields_e56(&value, 1, 0, 0x0);
+ wr32_ephy(hw, CMS_ANA_OVRDVAL5, value);
+
+ value = rd32_ephy(hw, CMS_ANA_OVRDEN1);
+ set_fields_e56(&value, 23, 23, 0x1);
+ wr32_ephy(hw, CMS_ANA_OVRDEN1, value);
+
+ value = rd32_ephy(hw, CMS_ANA_OVRDVAL9);
+ set_fields_e56(&value, 24, 24, 0x1);
+ set_fields_e56(&value, 31, 29, 0x4);
+ wr32_ephy(hw, CMS_ANA_OVRDVAL9, value);
+
+ value = rd32_ephy(hw, CMS_ANA_OVRDVAL10);
+ set_fields_e56(&value, 1, 0, 0x0);
+ wr32_ephy(hw, CMS_ANA_OVRDVAL10, value);
+ }
+
+ return 0;
+}
+
+static int txgbe_e56_config_rx_40G(struct txgbe_hw *hw, u32 speed)
+{
+ s32 status;
+
+ status = txgbe_e56_rxs_calib_adapt_seq_40G(hw, speed);
+ if (status)
+ return status;
+
+ //Step 2 of 2.3.4
+ txgbe_e56_set_rxs_ufine_le_max_40g(hw, speed);
+
+ //2.3.4 RXS post CDR lock temperature tracking sequence
+ txgbe_phy_rxs_post_cdr_lock_temp_track_seq_40g(hw, speed);
+
+ hw->link_valid = true;
+
+ return 0;
+}
+
+static int txgbe_e56_config_rx(struct txgbe_hw *hw, u32 speed)
+{
+ s32 status;
+
+ status = txgbe_e56_rxs_calib_adapt_seq(hw, speed);
+ if (status)
+ return status;
+
+ /* Step 2 of 2.3.4 */
+ txgbe_e56_set_rxs_ufine_le_max(hw, speed);
+
+ /* 2.3.4 RXS post CDR lock temperature tracking sequence */
+ txgbe_temp_track_seq(hw, speed);
+
+ return 0;
+}
+
+//--------------------------------------------------------------
+//2.2.10 SEQ::RX_DISABLE
+//Use PDIG::PMD_CFG[0]::rx_en_cfg[<lane no.>] = 0b0 to powerdown specific RXS lanes.
+//Completion of RXS powerdown can be confirmed by observing ALIAS::PDIG::CTRL_FSM_RX_ST = POWERDN_ST
+//--------------------------------------------------------------
+static int txgbe_e56_disable_rx40G(struct txgbe_hw *hw)
+{
+ int status = 0;
+ unsigned int rdata, timer;
+ unsigned int addr;
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ rdata = 0x0000;
+ addr = E56G__RXS0_ANA_OVRDEN_0_ADDR + (i * E56PHY_RXS_OFFSET);
+ wr32_ephy(hw, addr, rdata);
+ }
+
+ addr = E56G__PMD_BASER_PMD_CONTROL_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ EPHY_XFLD(E56G__PMD_BASER_PMD_CONTROL, training_enable_ln0) = 0;
+ EPHY_XFLD(E56G__PMD_BASER_PMD_CONTROL, training_enable_ln1) = 0;
+ EPHY_XFLD(E56G__PMD_BASER_PMD_CONTROL, training_enable_ln2) = 0;
+ EPHY_XFLD(E56G__PMD_BASER_PMD_CONTROL, training_enable_ln3) = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ timer = 0;
+
+ while (EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx0_st) != 0x21 ||
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx1_st) != 0x21 ||
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx2_st) != 0x21 ||
+ EPHY_XFLD(E56G__PMD_CTRL_FSM_RX_STAT_0, ctrl_fsm_rx3_st) != 0x21) {
+ rdata = 0;
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(100);
+ if (timer++ > PHYINIT_TIMEOUT) {
+ printf("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!!!\n");
+ break;
+ }
+ }
+
+ return status;
+}
+
+//--------------------------------------------------------------
+//2.2.10 SEQ::RX_DISABLE
+//Use PDIG::PMD_CFG[0]::rx_en_cfg[<lane no.>] = 0b0 to powerdown specific RXS lanes.
+//Completion of RXS powerdown can be confirmed by observing ALIAS::PDIG::CTRL_FSM_RX_ST = POWERDN_ST
+//--------------------------------------------------------------
+static int txgbe_e56_disable_rx(struct txgbe_hw *hw)
+{
+ int status = 0;
+ unsigned int rdata, timer;
+ unsigned int addr, temp;
+
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_bbcdr_osc_range_sel_i, 0);
+
+ EPHY_RREG(E56G__PMD_RXS0_OVRDEN_3);
+ temp = EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_3, ovrd_en_rxs0_rx0_spareout_o);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_3, ovrd_en_rxs0_rx0_spareout_o) = temp & 0x8F;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDEN_3);
+
+ EPHY_RREG(E56G__RXS0_DIG_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_DIG_OVRDEN_1, top_comp_th_ovrd_en) = 0;
+ EPHY_XFLD(E56G__RXS0_DIG_OVRDEN_1, mid_comp_th_ovrd_en) = 0;
+ EPHY_XFLD(E56G__RXS0_DIG_OVRDEN_1, bot_comp_th_ovrd_en) = 0;
+ EPHY_WREG(E56G__RXS0_DIG_OVRDEN_1);
+
+ txgbe_e56_ephy_config(E56G__RXS0_DFT_1, ber_en, 0);
+
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_3, ovrd_en_ana_sel_lpbk_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_2, ovrd_en_ana_en_adccal_lpbk_i, 0);
+
+ txgbe_e56_ephy_config(E56G__RXS0_RXS_CFG_0, train_clk_gate_bypass_en, 0x1FFF);
+
+ txgbe_e56_ephy_config(E56G__PMD_BASER_PMD_CONTROL, training_enable_ln0, 0);
+
+ txgbe_e56_ephy_config(E56G__PMD_PMD_CFG_5, rx_to_tx_lpbk_en, 0);
+
+ txgbe_e56_ephy_config(E56G__PMD_PMD_CFG_0, rx_en_cfg, 0);
+
+ timer = 0;
+ while (1) {
+ rdata = 0;
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if ((rdata & 0x3f) == 0x21)
+ break;
+ usec_delay(100);
+ if (timer++ > PHYINIT_TIMEOUT) {
+ printf("ERROR: Wait E56PHY_CTRL_FSM_RX_STAT_0_ADDR Timeout!!!\n");
+ break;
+ }
+ }
+
+ return status;
+}
+
+int txgbe_e56_reconfig_rx(struct txgbe_hw *hw, u32 speed)
+{
+ u32 addr;
+ u32 rdata;
+ int status = 0;
+
+ wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
+ ~TXGBE_MACTXCFG_TXE);
+ wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA,
+ ~TXGBE_MACRXCFG_ENA);
+
+ hw->mac.disable_sec_tx_path(hw);
+
+ if (hw->mac.type == txgbe_mac_aml) {
+ rdata = rd32(hw, TXGBE_GPIOEXT);
+ if (rdata & (TXGBE_SFP1_MOD_ABS_LS | TXGBE_SFP1_RX_LOS_LS)) {
+ return TXGBE_ERR_TIMEOUT;
+ }
+ }
+
+ wr32_ephy(hw, E56PHY_INTR_0_ENABLE_ADDR, 0x0);
+ wr32_ephy(hw, E56PHY_INTR_1_ENABLE_ADDR, 0x0);
+
+ if (hw->mac.type == txgbe_mac_aml40) {
+ txgbe_e56_disable_rx40G(hw);
+ status = txgbe_e56_config_rx_40G(hw, speed);
+ } else {
+ txgbe_e56_disable_rx(hw);
+ status = txgbe_e56_config_rx(hw, speed);
+ }
+
+ addr = E56PHY_INTR_0_ADDR;
+ wr32_ephy(hw, addr, E56PHY_INTR_0_IDLE_ENTRY1);
+
+ addr = E56PHY_INTR_1_ADDR;
+ wr32_ephy(hw, addr, E56PHY_INTR_1_IDLE_EXIT1);
+
+ wr32_ephy(hw, E56PHY_INTR_0_ENABLE_ADDR, E56PHY_INTR_0_IDLE_ENTRY1);
+ wr32_ephy(hw, E56PHY_INTR_1_ENABLE_ADDR, E56PHY_INTR_1_IDLE_EXIT1);
+
+ hw->mac.enable_sec_tx_path(hw);
+ wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA,
+ TXGBE_MACRXCFG_ENA);
+
+ return status;
+}
+
+int txgbe_set_link_to_amlite(struct txgbe_hw *hw, u32 speed)
+{
+ u32 value = 0;
+ u32 ppl_lock = false;
+ int status = 0;
+ u32 reset = 0;
+
+ if ((rd32(hw, TXGBE_EPHY_STAT) & TXGBE_EPHY_STAT_PPL_LOCK)
+ == TXGBE_EPHY_STAT_PPL_LOCK) {
+ ppl_lock = true;
+ wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
+ ~TXGBE_MACTXCFG_TXE);
+ wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA,
+ ~TXGBE_MACRXCFG_ENA);
+
+ hw->mac.disable_sec_tx_path(hw);
+ }
+
+ hw->mac.disable_tx_laser(hw);
+
+ if (hw->bus.lan_id == 0)
+ reset = TXGBE_RST_EPHY_LAN_0;
+
+ else
+ reset = TXGBE_RST_EPHY_LAN_1;
+
+ wr32(hw, TXGBE_RST,
+ reset | rd32(hw, TXGBE_RST));
+ txgbe_flush(hw);
+ usec_delay(10);
+
+ /* XLGPCS REGS Start */
+ value = rd32_epcs(hw, VR_PCS_DIG_CTRL1);
+ value |= 0x8000;
+ wr32_epcs(hw, VR_PCS_DIG_CTRL1, value);
+
+ usec_delay(1000);
+ value = rd32_epcs(hw, VR_PCS_DIG_CTRL1);
+ if ((value & 0x8000)) {
+ status = TXGBE_ERR_PHY_INIT_NOT_DONE;
+ goto out;
+ }
+
+ value = rd32_epcs(hw, SR_AN_CTRL);
+ set_fields_e56(&value, 12, 12, 0);
+ wr32_epcs(hw, SR_AN_CTRL, value);
+
+ if (speed == TXGBE_LINK_SPEED_40GB_FULL) {
+ value = rd32_epcs(hw, SR_PCS_CTRL1);
+ set_fields_e56(&value, 5, 2, 0x3);
+ wr32_epcs(hw, SR_PCS_CTRL1, value);
+
+ value = rd32_epcs(hw, SR_PCS_CTRL2);
+ set_fields_e56(&value, 3, 0, 0x4);
+ wr32_epcs(hw, SR_PCS_CTRL2, value);
+
+ value = rd32_ephy(hw, ANA_OVRDVAL0);
+ set_fields_e56(&value, 29, 29, 0x1);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, ANA_OVRDVAL0, value);
+
+ value = rd32_ephy(hw, ANA_OVRDVAL5);
+ set_fields_e56(&value, 24, 24, 0x1);
+ wr32_ephy(hw, ANA_OVRDVAL5, value);
+
+ value = rd32_ephy(hw, ANA_OVRDEN0);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, ANA_OVRDEN0, value);
+
+ value = rd32_ephy(hw, ANA_OVRDEN1);
+ set_fields_e56(&value, 30,30, 0x1);
+ set_fields_e56(&value, 25,25, 0x1);
+ wr32_ephy(hw, ANA_OVRDEN1, value);
+
+ value = rd32_ephy(hw, PLL0_CFG0);
+ set_fields_e56(&value, 25, 24, 0x1);
+ set_fields_e56(&value, 17, 16, 0x3);
+ wr32_ephy(hw, PLL0_CFG0, value);
+
+ value = rd32_ephy(hw, PLL0_CFG2);
+ set_fields_e56(&value, 12, 8, 0x4);
+ wr32_ephy(hw, PLL0_CFG2, value);
+
+ value = rd32_ephy(hw, PLL1_CFG0);
+ set_fields_e56(&value, 25, 24, 0x1);
+ set_fields_e56(&value, 17, 16, 0x3);
+ wr32_ephy(hw, PLL1_CFG0, value);
+
+ value = rd32_ephy(hw, PLL1_CFG2);
+ set_fields_e56(&value, 12, 8, 0x8);
+ wr32_ephy(hw, PLL1_CFG2, value);
+
+ value = rd32_ephy(hw, PLL0_DIV_CFG0);
+ set_fields_e56(&value, 18, 8, 0x294);
+ set_fields_e56(&value, 4, 0, 0x8);
+ wr32_ephy(hw, PLL0_DIV_CFG0, value);
+
+ value = rd32_ephy(hw, DATAPATH_CFG0);
+ set_fields_e56(&value, 30, 28, 0x7);
+ set_fields_e56(&value, 26, 24, 0x5);
+ set_fields_e56(&value, 18, 16, 0x5);
+ set_fields_e56(&value, 14, 12, 0x5);
+ set_fields_e56(&value, 10, 8, 0x5);
+ wr32_ephy(hw, DATAPATH_CFG0, value);
+
+ value = rd32_ephy(hw, DATAPATH_CFG1);
+ set_fields_e56(&value, 26, 24, 0x5);
+ set_fields_e56(&value, 10, 8, 0x5);
+ set_fields_e56(&value, 18, 16, 0x5);
+ set_fields_e56(&value, 2, 0, 0x5);
+ wr32_ephy(hw, DATAPATH_CFG1, value);
+
+ value = rd32_ephy(hw, AN_CFG1);
+ set_fields_e56(&value, 4, 0, 0x2);
+ wr32_ephy(hw, AN_CFG1, value);
+
+ txgbe_e56_cfg_temp(hw);
+ txgbe_e56_cfg_40g(hw);
+
+ value = rd32_ephy(hw, PMD_CFG0);
+ set_fields_e56(&value, 21, 20, 0x3);
+ set_fields_e56(&value, 19, 12, 0xf); //TX_EN set
+ set_fields_e56(&value, 8, 8, 0x0);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, PMD_CFG0, value);
+
+ status = txgbe_e56_config_rx_40G(hw, speed);
+ }
+
+ if (speed == TXGBE_LINK_SPEED_25GB_FULL) {
+ value = rd32_epcs(hw, SR_PCS_CTRL1);
+ set_fields_e56(&value, 5, 2, 5);
+ wr32_epcs(hw, SR_PCS_CTRL1, value);
+
+ value = rd32_epcs(hw, SR_PCS_CTRL2);
+ set_fields_e56(&value, 3, 0, 7);
+ wr32_epcs(hw, SR_PCS_CTRL2, value);
+
+ value = rd32_epcs(hw, SR_PMA_CTRL2);
+ set_fields_e56(&value, 6, 0, 0x39);
+ wr32_epcs(hw, SR_PMA_CTRL2, value);
+
+ value = rd32_ephy(hw, ANA_OVRDVAL0);
+ set_fields_e56(&value, 29, 29, 0x1);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, ANA_OVRDVAL0, value);
+
+ value = rd32_ephy(hw, ANA_OVRDVAL5);
+ /* Update to 0 from SNPS for PIN CLKP/N: Enable the termination of the input buffer */
+ set_fields_e56(&value, 24, 24, 0x0);
+ wr32_ephy(hw, ANA_OVRDVAL5, value);
+
+ value = rd32_ephy(hw, ANA_OVRDEN0);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, ANA_OVRDEN0, value);
+
+ value = rd32_ephy(hw, ANA_OVRDEN1);
+ set_fields_e56(&value, 30, 30, 0x1);
+ set_fields_e56(&value, 25, 25, 0x1);
+ wr32_ephy(hw, ANA_OVRDEN1, value);
+
+ value = rd32_ephy(hw, PLL0_CFG0);
+ set_fields_e56(&value, 25, 24, 0x1);
+ set_fields_e56(&value, 17, 16, 0x3);
+ wr32_ephy(hw, PLL0_CFG0, value);
+
+ value = rd32_ephy(hw, PLL0_CFG2);
+ set_fields_e56(&value, 12, 8, 0x4);
+ wr32_ephy(hw, PLL0_CFG2, value);
+
+ value = rd32_ephy(hw, PLL1_CFG0);
+ set_fields_e56(&value, 25, 24, 0x1);
+ set_fields_e56(&value, 17, 16, 0x3);
+ wr32_ephy(hw, PLL1_CFG0, value);
+
+ value = rd32_ephy(hw, PLL1_CFG2);
+ set_fields_e56(&value, 12, 8, 0x8);
+ wr32_ephy(hw, PLL1_CFG2, value);
+
+ value = rd32_ephy(hw, PLL0_DIV_CFG0);
+ set_fields_e56(&value, 18, 8, 0x294);
+ set_fields_e56(&value, 4, 0, 0x8);
+ wr32_ephy(hw, PLL0_DIV_CFG0, value);
+
+ value = rd32_ephy(hw, DATAPATH_CFG0);
+ set_fields_e56(&value, 30, 28, 0x7);
+ set_fields_e56(&value, 26, 24, 0x5);
+ set_fields_e56(&value, 18, 16, 0x3);
+ set_fields_e56(&value, 14, 12, 0x5);
+ set_fields_e56(&value, 10, 8, 0x5);
+ wr32_ephy(hw, DATAPATH_CFG0, value);
+
+ value = rd32_ephy(hw, DATAPATH_CFG1);
+ set_fields_e56(&value, 26, 24, 0x5);
+ set_fields_e56(&value, 10, 8, 0x5);
+ set_fields_e56(&value, 18, 16, 0x3);
+ set_fields_e56(&value, 2, 0, 0x3);
+ wr32_ephy(hw, DATAPATH_CFG1, value);
+
+ value = rd32_ephy(hw, AN_CFG1);
+ set_fields_e56(&value, 4, 0, 0x9);
+ wr32_ephy(hw, AN_CFG1, value);
+
+ txgbe_e56_cfg_temp(hw);
+ txgbe_e56_cfg_25g(hw);
+
+ value = rd32_ephy(hw, PMD_CFG0);
+ set_fields_e56(&value, 21, 20, 0x3);
+ set_fields_e56(&value, 19, 12, 0x1); /* TX_EN set */
+ set_fields_e56(&value, 8, 8, 0x0);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, PMD_CFG0, value);
+
+ status = txgbe_e56_config_rx(hw, speed);
+
+ }
+
+ if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
+ value = rd32_epcs(hw, SR_PCS_CTRL1);
+ set_fields_e56(&value, 5, 2, 0);
+ wr32_epcs(hw, SR_PCS_CTRL1, value);
+
+ value = rd32_epcs(hw, SR_PCS_CTRL2);
+ set_fields_e56(&value, 3, 0, 0);
+ wr32_epcs(hw, SR_PCS_CTRL2, value);
+
+ value = rd32_epcs(hw, SR_PMA_CTRL2);
+ set_fields_e56(&value, 6, 0, 0xb);
+ wr32_epcs(hw, SR_PMA_CTRL2, value);
+
+ value = rd32_ephy(hw, ANA_OVRDVAL0);
+ set_fields_e56(&value, 29, 29, 0x1);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, ANA_OVRDVAL0, value);
+
+ value = rd32_ephy(hw, ANA_OVRDVAL5);
+ set_fields_e56(&value, 24, 24, 0x1);
+ wr32_ephy(hw, ANA_OVRDVAL5, value);
+
+ value = rd32_ephy(hw, ANA_OVRDEN0);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, ANA_OVRDEN0, value);
+
+ value = rd32_ephy(hw, ANA_OVRDEN1);
+ set_fields_e56(&value, 30, 30, 0x1);
+ set_fields_e56(&value, 25, 25, 0x1);
+ wr32_ephy(hw, ANA_OVRDEN1, value);
+
+ value = rd32_ephy(hw, PLL0_CFG0);
+ set_fields_e56(&value, 25, 24, 0x1);
+ set_fields_e56(&value, 17, 16, 0x3);
+ wr32_ephy(hw, PLL0_CFG0, value);
+
+ value = rd32_ephy(hw, PLL0_CFG2);
+ set_fields_e56(&value, 12, 8, 0x4);
+ wr32_ephy(hw, PLL0_CFG2, value);
+
+ value = rd32_ephy(hw, PLL1_CFG0);
+ set_fields_e56(&value, 25, 24, 0x1);
+ set_fields_e56(&value, 17, 16, 0x3);
+ wr32_ephy(hw, PLL1_CFG0, value);
+
+ value = rd32_ephy(hw, PLL1_CFG2);
+ set_fields_e56(&value, 12, 8, 0x8);
+ wr32_ephy(hw, PLL1_CFG2, value);
+
+ value = rd32_ephy(hw, PLL0_DIV_CFG0);
+ set_fields_e56(&value, 18, 8, 0x294);
+ set_fields_e56(&value, 4, 0, 0x8);
+ wr32_ephy(hw, PLL0_DIV_CFG0, value);
+
+ value = rd32_ephy(hw, DATAPATH_CFG0);
+ set_fields_e56(&value, 30, 28, 0x7);
+ set_fields_e56(&value, 26, 24, 0x5);
+ set_fields_e56(&value, 18, 16, 0x5);
+ set_fields_e56(&value, 14, 12, 0x5);
+ set_fields_e56(&value, 10, 8, 0x5);
+ wr32_ephy(hw, DATAPATH_CFG0, value);
+
+ value = rd32_ephy(hw, DATAPATH_CFG1);
+ set_fields_e56(&value, 26, 24, 0x5);
+ set_fields_e56(&value, 10, 8, 0x5);
+ set_fields_e56(&value, 18, 16, 0x5);
+ set_fields_e56(&value, 2, 0, 0x5);
+ wr32_ephy(hw, DATAPATH_CFG1, value);
+
+ value = rd32_ephy(hw, AN_CFG1);
+ set_fields_e56(&value, 4, 0, 0x2);
+ wr32_ephy(hw, AN_CFG1, value);
+
+ txgbe_e56_cfg_temp(hw);
+ txgbe_e56_cfg_10g(hw);
+
+ value = rd32_ephy(hw, PMD_CFG0);
+ set_fields_e56(&value, 21, 20, 0x3);
+ set_fields_e56(&value, 19, 12, 0x1); /* TX_EN set */
+ set_fields_e56(&value, 8, 8, 0x0);
+ set_fields_e56(&value, 1, 1, 0x1);
+ wr32_ephy(hw, PMD_CFG0, value);
+
+ status = txgbe_e56_config_rx(hw, speed);
+ }
+
+ value = rd32_ephy(hw, E56PHY_RXS_IDLE_DETECT_1_ADDR);
+ set_fields_e56(&value, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MAX, 0x28);
+ set_fields_e56(&value, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MIN, 0xa);
+ wr32_ephy(hw, E56PHY_RXS_IDLE_DETECT_1_ADDR, value);
+
+ wr32_ephy(hw, E56PHY_INTR_0_ADDR, E56PHY_INTR_0_IDLE_ENTRY1);
+ wr32_ephy(hw, E56PHY_INTR_1_ADDR, E56PHY_INTR_1_IDLE_EXIT1);
+ wr32_ephy(hw, E56PHY_INTR_0_ENABLE_ADDR, E56PHY_INTR_0_IDLE_ENTRY1);
+ wr32_ephy(hw, E56PHY_INTR_1_ENABLE_ADDR, E56PHY_INTR_1_IDLE_EXIT1);
+
+ if (hw->fec_mode != TXGBE_PHY_FEC_AUTO) {
+ hw->cur_fec_link = hw->fec_mode;
+ txgbe_e56_fec_set(hw);
+ }
+
+out:
+ if (ppl_lock) {
+ hw->mac.enable_sec_tx_path(hw);
+ wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA,//todo
+ TXGBE_MACRXCFG_ENA);
+ }
+
+ hw->mac.enable_tx_laser(hw);
+
+ return status;
+}
+
+s32 txgbe_e56_fec_set(struct txgbe_hw *hw)
+{
+ u32 value;
+
+ if (hw->cur_fec_link & TXGBE_PHY_FEC_RS) {
+ /* disable BASER FEC */
+ value = rd32_epcs(hw, SR_PMA_KR_FEC_CTRL);
+ set_fields_e56(&value, 0, 0, 0);
+ wr32_epcs(hw, SR_PMA_KR_FEC_CTRL, value);
+
+ /* enable RS FEC */
+ wr32_epcs(hw, 0x180a3, 0x68c1);
+ wr32_epcs(hw, 0x180a4, 0x3321);
+ wr32_epcs(hw, 0x180a5, 0x973e);
+ wr32_epcs(hw, 0x180a6, 0xccde);
+
+ wr32_epcs(hw, 0x38018, 1024);
+ value = rd32_epcs(hw, 0x100c8);
+ set_fields_e56(&value, 2, 2, 1);
+ wr32_epcs(hw, 0x100c8, value);
+ } else if (hw->cur_fec_link & TXGBE_PHY_FEC_BASER) {
+ /* disable RS FEC */
+ wr32_epcs(hw, 0x180a3, 0x7690);
+ wr32_epcs(hw, 0x180a4, 0x3347);
+ wr32_epcs(hw, 0x180a5, 0x896f);
+ wr32_epcs(hw, 0x180a6, 0xccb8);
+ wr32_epcs(hw, 0x38018, 0x3fff);
+ value = rd32_epcs(hw, 0x100c8);
+ set_fields_e56(&value, 2, 2, 0);
+ wr32_epcs(hw, 0x100c8, value);
+
+ /* enable BASER FEC */
+ value = rd32_epcs(hw, SR_PMA_KR_FEC_CTRL);
+ set_fields_e56(&value, 0, 0, 1);
+ wr32_epcs(hw, SR_PMA_KR_FEC_CTRL, value);
+ } else {
+ /* disable RS FEC */
+ wr32_epcs(hw, 0x180a3, 0x7690);
+ wr32_epcs(hw, 0x180a4, 0x3347);
+ wr32_epcs(hw, 0x180a5, 0x896f);
+ wr32_epcs(hw, 0x180a6, 0xccb8);
+ wr32_epcs(hw, 0x38018, 0x3fff);
+ value = rd32_epcs(hw, 0x100c8);
+ set_fields_e56(&value, 2, 2, 0);
+ wr32_epcs(hw, 0x100c8, value);
+
+ /* disable BASER FEC */
+ value = rd32_epcs(hw, SR_PMA_KR_FEC_CTRL);
+ set_fields_e56(&value, 0, 0, 0);
+ wr32_epcs(hw, SR_PMA_KR_FEC_CTRL, value);
+ }
+
+ return 0;
+}
+
+s32 txgbe_e56_fec_polling(struct txgbe_hw *hw, bool *link_up)
+{
+ u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
+ s32 status = 0, i =0, j = 0;
+
+ do {
+ if (!(hw->fec_mode & BIT(j))) {
+ j += 1;
+ continue;
+ }
+
+ hw->cur_fec_link = hw->fec_mode & BIT(j);
+
+ /*
+ * If in fec auto mode, try another fec mode after no link in 1s
+ * for lr sfp, enable KR-FEC to link up with mellonax and intel
+ */
+ rte_spinlock_lock(&hw->phy_lock);
+ txgbe_e56_fec_set(hw);
+ rte_spinlock_unlock(&hw->phy_lock);
+
+ for (i = 0; i < 4; i++) {
+ msleep(250);
+ txgbe_e56_check_phy_link(hw, &link_speed, link_up);
+ if (*link_up)
+ return 0;
+ }
+ j += 1;
+ } while (j < 3);
+
+ return status;
+}
\ No newline at end of file
diff --git a/drivers/net/txgbe/base/txgbe_e56.h b/drivers/net/txgbe/base/txgbe_e56.h
new file mode 100644
index 0000000000..bb56236b6f
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_e56.h
@@ -0,0 +1,1784 @@
+#ifndef _TXGBE_E56_H_
+#define _TXGBE_E56_H_
+
+#include "txgbe_type.h"
+#include "txgbe_hw.h"
+#include "txgbe_osdep.h"
+#include "txgbe_phy.h"
+
+#define EPHY_RREG(REG) \
+ do {\
+ rdata = 0; \
+ rdata = rd32_ephy(hw, REG##_ADDR); \
+ } while(0)
+
+#define EPHY_WREG(REG) \
+ do { \
+ wr32_ephy(hw, REG##_ADDR, rdata); \
+ } while(0)
+
+#define EPCS_RREG(REG) \
+ do {\
+ rdata = 0; \
+ rdata = rd32_epcs(hw, REG##_ADDR); \
+ } while(0)
+
+#define EPCS_WREG(REG) \
+ do { \
+ wr32_epcs(hw, REG##_ADDR, rdata); \
+ } while(0)
+
+#define txgbe_e56_ephy_config(reg, field, val) \
+ do { \
+ EPHY_RREG(reg); \
+ EPHY_XFLD(reg, field) = (val); \
+ EPHY_WREG(reg); \
+ } while(0)
+
+#define txgbe_e56_epcs_config(reg, field, val) \
+ do { \
+ EPCS_RREG(reg); \
+ EPCS_XFLD(reg, field) = (val); \
+ EPCS_WREG(reg); \
+ } while(0)
+
+//--------------------------------
+//LAN GPIO define for SFP+ module
+//--------------------------------
+//-- Fields
+#define SFP1_RS0 5,5
+#define SFP1_RS1 4,4
+#define SFP1_RX_LOS 3,3
+#define SFP1_MOD_ABS 2,2
+#define SFP1_TX_DISABLE 1,1
+#define SFP1_TX_FAULT 0,0
+#define EPHY_XFLD(REG, FLD) ((REG *)&rdata)->FLD
+#define EPCS_XFLD(REG, FLD) ((REG *)&rdata)->FLD
+
+typedef union {
+ struct {
+ u32 ana_refclk_buf_daisy_en_i : 1;
+ u32 ana_refclk_buf_pad_en_i : 1;
+ u32 ana_vddinoff_dcore_dig_o : 1;
+ u32 ana_lcpll_en_clkout_hf_left_top_i : 1;
+ u32 ana_lcpll_en_clkout_hf_right_top_i : 1;
+ u32 ana_lcpll_en_clkout_hf_left_bot_i : 1;
+ u32 ana_lcpll_en_clkout_hf_right_bot_i : 1;
+ u32 ana_lcpll_en_clkout_lf_left_top_i : 1;
+ u32 ana_lcpll_en_clkout_lf_right_top_i : 1;
+ u32 ana_lcpll_en_clkout_lf_left_bot_i : 1;
+ u32 ana_lcpll_en_clkout_lf_right_bot_i : 1;
+ u32 ana_bg_en_i : 1;
+ u32 ana_en_rescal_i : 1;
+ u32 ana_rescal_comp_o : 1;
+ u32 ana_en_ldo_core_i : 1;
+ u32 ana_lcpll_hf_en_bias_i : 1;
+ u32 ana_lcpll_hf_en_loop_i : 1;
+ u32 ana_lcpll_hf_en_cp_i : 1;
+ u32 ana_lcpll_hf_set_lpf_i : 1;
+ u32 ana_lcpll_hf_en_vco_i : 1;
+ u32 ana_lcpll_hf_vco_amp_status_o : 1;
+ u32 ana_lcpll_hf_en_odiv_i : 1;
+ u32 ana_lcpll_lf_en_bias_i : 1;
+ u32 ana_lcpll_lf_en_loop_i : 1;
+ u32 ana_lcpll_lf_en_cp_i : 1;
+ u32 ana_lcpll_lf_set_lpf_i : 1;
+ u32 ana_lcpll_lf_en_vco_i : 1;
+ u32 ana_lcpll_lf_vco_amp_status_o : 1;
+ u32 ana_lcpll_lf_en_odiv_i : 1;
+ u32 ana_lcpll_hf_refclk_select_i : 1;
+ u32 ana_lcpll_lf_refclk_select_i : 1;
+ u32 rsvd0 : 1;
+ };
+ u32 reg;
+} E56G_CMS_ANA_OVRDVAL_0;
+
+#define E56G_CMS_ANA_OVRDVAL_0_ADDR 0xcb0
+/* AMLITE ETH PHY Registers */
+#define VR_PCS_DIG_CTRL1 0x38000
+#define SR_PCS_CTRL1 0x30000
+#define SR_PCS_CTRL2 0x30007
+#define SR_PMA_CTRL2 0x10007
+#define VR_PCS_DIG_CTRL3 0x38003
+#define VR_PMA_CTRL3 0x180a8
+#define VR_PMA_CTRL4 0x180a9
+#define SR_PMA_RS_FEC_CTRL 0x100c8
+#define CMS_ANA_OVRDEN0 0xca4
+#define ANA_OVRDEN0 0xca4
+#define ANA_OVRDEN1 0xca8
+#define ANA_OVRDVAL0 0xcb0
+#define ANA_OVRDVAL5 0xcc4
+#define OSC_CAL_N_CDR4 0x14
+#define PLL0_CFG0 0xc10
+#define PLL0_CFG2 0xc18
+#define PLL0_DIV_CFG0 0xc1c
+#define PLL1_CFG0 0xc48
+#define PLL1_CFG2 0xc50
+#define CMS_PIN_OVRDEN0 0xc8c
+#define CMS_PIN_OVRDVAL0 0xc94
+#define DATAPATH_CFG0 0x142c
+#define DATAPATH_CFG1 0x1430
+#define AN_CFG1 0x1438
+#define SPARE52 0x16fc
+#define RXS_CFG0 0x000
+#define PMD_CFG0 0x1400
+#define SR_PCS_STS1 0x30001
+#define PMD_CTRL_FSM_TX_STAT0 0x14dc
+#define CMS_ANA_OVRDEN0 0xca4
+#define CMS_ANA_OVRDEN1 0xca8
+#define CMS_ANA_OVRDVAL2 0xcb8
+#define CMS_ANA_OVRDVAL4 0xcc0
+#define CMS_ANA_OVRDVAL5 0xcc4
+#define CMS_ANA_OVRDVAL7 0xccc
+#define CMS_ANA_OVRDVAL9 0xcd4
+#define CMS_ANA_OVRDVAL10 0xcd8
+
+#define TXS_TXS_CFG1 0x804
+#define TXS_WKUP_CNT 0x808
+#define TXS_PIN_OVRDEN0 0x80c
+#define TXS_PIN_OVRDVAL6 0x82c
+#define TXS_ANA_OVRDVAL1 0x854
+
+#define E56PHY_CMS_BASE_ADDR 0x0C00
+
+#define E56PHY_CMS_PIN_OVRDEN_0_ADDR (E56PHY_CMS_BASE_ADDR+0x8C)
+#define E56PHY_CMS_PIN_OVRDEN_0_OVRD_EN_PLL0_TX_SIGNAL_TYPE_I 12,12
+
+#define E56PHY_CMS_PIN_OVRDVAL_0_ADDR (E56PHY_CMS_BASE_ADDR+0x94)
+#define E56PHY_CMS_PIN_OVRDVAL_0_INT_PLL0_TX_SIGNAL_TYPE_I 10,10
+
+#define E56PHY_CMS_ANA_OVRDEN_0_ADDR (E56PHY_CMS_BASE_ADDR+0xA4)
+
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_VCO_SWING_CTRL_I 29,29
+
+
+#define E56PHY_CMS_ANA_OVRDEN_1_ADDR (E56PHY_CMS_BASE_ADDR+0xA8)
+#define E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_HF_TEST_IN_I 4,4
+
+#define E56PHY_CMS_ANA_OVRDVAL_2_ADDR (E56PHY_CMS_BASE_ADDR+0xB8)
+
+#define E56PHY_CMS_ANA_OVRDVAL_2_ANA_LCPLL_HF_VCO_SWING_CTRL_I 31,28
+
+#define E56PHY_CMS_ANA_OVRDVAL_4_ADDR (E56PHY_CMS_BASE_ADDR+0xC0)
+
+
+#define E56PHY_TXS_BASE_ADDR 0x0800
+#define E56PHY_TXS1_BASE_ADDR 0x0900
+#define E56PHY_TXS2_BASE_ADDR 0x0A00
+#define E56PHY_TXS3_BASE_ADDR 0x0B00
+#define E56PHY_TXS_OFFSET 0x0100
+
+#define E56PHY_PMD_RX_OFFSET 0x02C
+
+#define E56PHY_TXS_TXS_CFG_1_ADDR (E56PHY_TXS_BASE_ADDR+0x04)
+#define E56PHY_TXS_TXS_CFG_1_ADAPTATION_WAIT_CNT_X256 7,4
+#define E56PHY_TXS_WKUP_CNT_ADDR (E56PHY_TXS_BASE_ADDR+0x08)
+#define E56PHY_TXS_WKUP_CNTLDO_WKUP_CNT_X32 7,0
+#define E56PHY_TXS_WKUP_CNTDCC_WKUP_CNT_X32 15,8
+
+
+#define E56PHY_TXS_PIN_OVRDEN_0_ADDR (E56PHY_TXS_BASE_ADDR+0x0C)
+#define E56PHY_TXS_PIN_OVRDEN_0_OVRD_EN_TX0_EFUSE_BITS_I 28,28
+
+#define E56PHY_TXS_PIN_OVRDVAL_6_ADDR (E56PHY_TXS_BASE_ADDR+0x2C)
+
+#define E56PHY_TXS_ANA_OVRDVAL_1_ADDR (E56PHY_TXS_BASE_ADDR+0x54)
+#define E56PHY_TXS_ANA_OVRDVAL_1_ANA_TEST_DAC_I 23,8
+
+#define E56PHY_TXS_ANA_OVRDEN_0_ADDR (E56PHY_TXS_BASE_ADDR+0x44)
+#define E56PHY_TXS_ANA_OVRDEN_0_OVRD_EN_ANA_TEST_DAC_I 13,13
+
+#define E56PHY_RXS_BASE_ADDR 0x0000
+#define E56PHY_RXS1_BASE_ADDR 0x0200
+#define E56PHY_RXS2_BASE_ADDR 0x0400
+#define E56PHY_RXS3_BASE_ADDR 0x0600
+#define E56PHY_RXS_OFFSET 0x0200
+
+#define E56PHY_RXS_RXS_CFG_0_ADDR (E56PHY_RXS_BASE_ADDR+0x000)
+#define E56PHY_RXS_RXS_CFG_0_DSER_DATA_SEL 1,1
+#define E56PHY_RXS_RXS_CFG_0_TRAIN_CLK_GATE_BYPASS_EN 17,4
+
+#define E56PHY_RXS_OSC_CAL_N_CDR_1_ADDR (E56PHY_RXS_BASE_ADDR+0x008)
+#define E56PHY_RXS_OSC_CAL_N_CDR_1_PREDIV1 15,0
+#define E56PHY_RXS_OSC_CAL_N_CDR_1_PREDIV1_LSB 0
+#define E56PHY_RXS_OSC_CAL_N_CDR_1_TARGET_CNT1 31,16
+#define E56PHY_RXS_OSC_CAL_N_CDR_1_TARGET_CNT1_LSB 16
+
+
+#define E56PHY_RXS_OSC_CAL_N_CDR_4_ADDR (E56PHY_RXS_BASE_ADDR+0x014)
+#define E56PHY_RXS_OSC_CAL_N_CDR_4_OSC_RANGE_SEL1 3,2
+#define E56PHY_RXS_OSC_CAL_N_CDR_4_VCO_CODE_INIT 18,8
+#define E56PHY_RXS_OSC_CAL_N_CDR_4_OSC_CURRENT_BOOST_EN1 21,21
+#define E56PHY_RXS_OSC_CAL_N_CDR_4_BBCDR_CURRENT_BOOST1 27,26
+
+#define E56PHY_RXS_OSC_CAL_N_CDR_5_ADDR (E56PHY_RXS_BASE_ADDR+0x018)
+#define E56PHY_RXS_OSC_CAL_N_CDR_5_SDM_WIDTH 3,2
+#define E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_PRELOCK 15,12
+#define E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_POSTLOCK 19,16
+#define E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_POSTLOCK 23,20
+#define E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_PRELOCK 27,24
+#define E56PHY_RXS_OSC_CAL_N_CDR_5_BBCDR_RDY_CNT 30,28
+
+#define E56PHY_RXS_OSC_CAL_N_CDR_6_ADDR (E56PHY_RXS_BASE_ADDR+0x01C)
+#define E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_PRELOCK 3,0
+#define E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_POSTLOCK 7,4
+
+#define E56PHY_RXS_INTL_CONFIG_0_ADDR (E56PHY_RXS_BASE_ADDR+0x020)
+#define E56PHY_RXS_INTL_CONFIG_0_ADC_INTL2SLICE_DELAY1 31,16
+
+#define E56PHY_RXS_INTL_CONFIG_2_ADDR (E56PHY_RXS_BASE_ADDR+0x028)
+#define E56PHY_RXS_INTL_CONFIG_2_INTERLEAVER_HBW_DISABLE1 1,1
+
+#define E56PHY_RXS_TXFFE_TRAINING_0_ADDR (E56PHY_RXS_BASE_ADDR+0x02C)
+#define E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_LTH 18,12
+#define E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_UTH 26,20
+
+#define E56PHY_RXS_TXFFE_TRAINING_1_ADDR (E56PHY_RXS_BASE_ADDR+0x030)
+#define E56PHY_RXS_TXFFE_TRAINING_1_C1_LTH 8,0
+#define E56PHY_RXS_TXFFE_TRAINING_1_C1_UTH 20,12
+
+#define E56PHY_RXS_TXFFE_TRAINING_2_ADDR (E56PHY_RXS_BASE_ADDR+0x034)
+#define E56PHY_RXS_TXFFE_TRAINING_2_CM1_LTH 8,0
+#define E56PHY_RXS_TXFFE_TRAINING_2_CM1_UTH 20,12
+
+
+#define E56PHY_RXS_TXFFE_TRAINING_3_ADDR (E56PHY_RXS_BASE_ADDR+0x038)
+#define E56PHY_RXS_TXFFE_TRAINING_3_CM2_LTH 8,0
+#define E56PHY_RXS_TXFFE_TRAINING_3_CM2_UTH 20,12
+#define E56PHY_RXS_TXFFE_TRAINING_3_TXFFE_TRAIN_MOD_TYPE 26,21
+
+#define E56PHY_RXS_VGA_TRAINING_0_ADDR (E56PHY_RXS_BASE_ADDR+0x04C)
+#define E56PHY_RXS_VGA_TRAINING_0_VGA_TARGET 18,12
+
+
+#define E56PHY_RXS_VGA_TRAINING_1_ADDR (E56PHY_RXS_BASE_ADDR+0x050)
+#define E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT0 4,0
+#define E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT0 12,8
+#define E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT123 20,16
+#define E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT123 28,24
+
+#define E56PHY_RXS_CTLE_TRAINING_0_ADDR (E56PHY_RXS_BASE_ADDR+0x054)
+#define E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT0 24,20
+#define E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT123 31,27
+
+#define E56PHY_RXS_CTLE_TRAINING_1_ADDR (E56PHY_RXS_BASE_ADDR+0x058)
+#define E56PHY_RXS_CTLE_TRAINING_1_LFEQ_LUT 24,0
+
+#define E56PHY_RXS_CTLE_TRAINING_2_ADDR (E56PHY_RXS_BASE_ADDR+0x05C)
+#define E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P1 5,0
+#define E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P2 13,8
+#define E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P3 21,16
+
+
+#define E56PHY_RXS_CTLE_TRAINING_3_ADDR (E56PHY_RXS_BASE_ADDR+0x060)
+#define E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P1 9,8
+#define E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P2 11,10
+#define E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P3 13,12
+
+#define E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADDR (E56PHY_RXS_BASE_ADDR+0x064)
+#define E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_SLICE_DATA_AVG_CNT 5,4
+#define E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_DATA_AVG_CNT 9,8
+#define E56PHY_RXS_OFFSET_N_GAIN_CAL_0_FE_OFFSET_DAC_CLK_CNT_X8 31,28
+
+#define E56PHY_RXS_OFFSET_N_GAIN_CAL_1_ADDR (E56PHY_RXS_BASE_ADDR+0x068)
+#define E56PHY_RXS_OFFSET_N_GAIN_CAL_1_SAMP_ADAPT_CFG 31,28
+
+#define E56PHY_RXS_FFE_TRAINING_0_ADDR (E56PHY_RXS_BASE_ADDR+0x070)
+#define E56PHY_RXS_FFE_TRAINING_0_FFE_TAP_EN 23,8
+
+#define E56PHY_RXS_IDLE_DETECT_1_ADDR (E56PHY_RXS_BASE_ADDR+0x088)
+#define E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MAX 22,16
+#define E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MIN 30,24
+
+#define E56PHY_RXS_ANA_OVRDEN_0_ADDR (E56PHY_RXS_BASE_ADDR+0x08C)
+#define E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_RTERM_I 0,0
+#define E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_TRIM_RTERM_I 1,1
+#define E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_BBCDR_OSC_RANGE_SEL_I 29,29
+
+#define E56PHY_RXS_ANA_OVRDEN_1_ADDR (E56PHY_RXS_BASE_ADDR+0x090)
+#define E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_BBCDR_VCOFILT_BYP_I 0,0
+#define E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_TEST_BBCDR_I 9,9
+
+#define E56PHY_RXS_ANA_OVRDEN_3_ADDR (E56PHY_RXS_BASE_ADDR+0x098)
+#define E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_ANABS_CONFIG_I 15,15
+#define E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_VGA2_BOOST_CSTM_I 25,25
+
+#define E56PHY_RXS_ANA_OVRDEN_4_ADDR (E56PHY_RXS_BASE_ADDR+0x09C)
+#define E56PHY_RXS_ANA_OVRDVAL_0_ADDR (E56PHY_RXS_BASE_ADDR+0x0A0)
+#define E56PHY_RXS_ANA_OVRDVAL_0_ANA_EN_RTERM_I 0,0
+
+#define E56PHY_RXS_ANA_OVRDVAL_6_ADDR (E56PHY_RXS_BASE_ADDR+0x0B8)
+#define E56PHY_RXS_ANA_OVRDVAL_14_ADDR (E56PHY_RXS_BASE_ADDR+0x0D8)
+#define E56PHY_RXS_ANA_OVRDVAL_15_ADDR (E56PHY_RXS_BASE_ADDR+0x0DC)
+#define E56PHY_RXS_ANA_OVRDVAL_17_ADDR (E56PHY_RXS_BASE_ADDR+0x0E4)
+#define E56PHY_RXS_ANA_OVRDVAL_17_ANA_VGA2_BOOST_CSTM_I 18,16
+
+#define E56PHY_RXS_EYE_SCAN_1_ADDR (E56PHY_RXS_BASE_ADDR+0x1A4)
+#define E56PHY_RXS_EYE_SCAN_1_EYE_SCAN_REF_TIMER 31,0
+
+#define E56PHY_RXS_ANA_OVRDVAL_5_ADDR (E56PHY_RXS_BASE_ADDR+0x0B4)
+#define E56PHY_RXS_ANA_OVRDVAL_5_ANA_BBCDR_OSC_RANGE_SEL_I 1,0
+
+#define E56PHY_RXS_RINGO_0_ADDR (E56PHY_RXS_BASE_ADDR+0x1FC)
+
+#define E56PHY_PMD_BASE_ADDR 0x1400
+#define E56PHY_PMD_CFG_0_ADDR (E56PHY_PMD_BASE_ADDR+0x000)
+#define E56PHY_PMD_CFG_0_RX_EN_CFG 19,16
+
+#define E56PHY_PMD_CFG_3_ADDR (E56PHY_PMD_BASE_ADDR+0x00C)
+#define E56PHY_PMD_CFG_3_CTRL_FSM_TIMEOUT_X64K 31,24
+#define E56PHY_PMD_CFG_4_ADDR (E56PHY_PMD_BASE_ADDR+0x010)
+#define E56PHY_PMD_CFG_4_TRAIN_DC_ON_PERIOD_X64K 7,0
+#define E56PHY_PMD_CFG_4_TRAIN_DC_PERIOD_X512K 15,8
+#define E56PHY_PMD_CFG_5_ADDR (E56PHY_PMD_BASE_ADDR+0x014)
+#define E56PHY_PMD_CFG_5_USE_RECENT_MARKER_OFFSET 12,12
+#define E56PHY_CTRL_FSM_CFG_0_ADDR (E56PHY_PMD_BASE_ADDR+0x040)
+#define E56PHY_CTRL_FSM_CFG_0_CONT_ON_ADC_OFST_CAL_ERR 4,4
+#define E56PHY_CTRL_FSM_CFG_0_CONT_ON_ADC_GAIN_CAL_ERR 5,5
+#define E56PHY_CTRL_FSM_CFG_0_DO_RX_ADC_OFST_CAL 9,8
+#define E56PHY_CTRL_FSM_CFG_0_RX_ERR_ACTION_EN 31,24
+
+
+#define E56PHY_CTRL_FSM_CFG_1_ADDR (E56PHY_PMD_BASE_ADDR+0x044)
+#define E56PHY_CTRL_FSM_CFG_1_TRAIN_ST0_WAIT_CNT_X4096 7,0
+#define E56PHY_CTRL_FSM_CFG_1_TRAIN_ST1_WAIT_CNT_X4096 15,8
+#define E56PHY_CTRL_FSM_CFG_1_TRAIN_ST2_WAIT_CNT_X4096 23,16
+#define E56PHY_CTRL_FSM_CFG_1_TRAIN_ST3_WAIT_CNT_X4096 31,24
+
+#define E56PHY_CTRL_FSM_CFG_2_ADDR (E56PHY_PMD_BASE_ADDR+0x048)
+#define E56PHY_CTRL_FSM_CFG_2_TRAIN_ST4_WAIT_CNT_X4096 7,0
+#define E56PHY_CTRL_FSM_CFG_2_TRAIN_ST5_WAIT_CNT_X4096 15,8
+#define E56PHY_CTRL_FSM_CFG_2_TRAIN_ST6_WAIT_CNT_X4096 23,16
+#define E56PHY_CTRL_FSM_CFG_2_TRAIN_ST7_WAIT_CNT_X4096 31,24
+
+#define E56PHY_CTRL_FSM_CFG_3_ADDR (E56PHY_PMD_BASE_ADDR+0x04C)
+#define E56PHY_CTRL_FSM_CFG_3_TRAIN_ST8_WAIT_CNT_X4096 7,0
+
+#define E56PHY_CTRL_FSM_CFG_3_TRAIN_ST9_WAIT_CNT_X4096 15,8
+#define E56PHY_CTRL_FSM_CFG_3_TRAIN_ST10_WAIT_CNT_X4096 23,16
+#define E56PHY_CTRL_FSM_CFG_3_TRAIN_ST11_WAIT_CNT_X4096 31,24
+
+#define E56PHY_CTRL_FSM_CFG_4_ADDR (E56PHY_PMD_BASE_ADDR+0x050)
+#define E56PHY_CTRL_FSM_CFG_4_TRAIN_ST12_WAIT_CNT_X4096 7,0
+#define E56PHY_CTRL_FSM_CFG_4_TRAIN_ST13_WAIT_CNT_X4096 15,8
+#define E56PHY_CTRL_FSM_CFG_4_TRAIN_ST14_WAIT_CNT_X4096 23,16
+#define E56PHY_CTRL_FSM_CFG_4_TRAIN_ST15_WAIT_CNT_X4096 31,24
+
+#define E56PHY_CTRL_FSM_CFG_7_ADDR (E56PHY_PMD_BASE_ADDR+0x05C)
+#define E56PHY_CTRL_FSM_CFG_7_TRAIN_ST4_EN 15,0
+#define E56PHY_CTRL_FSM_CFG_7_TRAIN_ST5_EN 31,16
+
+#define E56PHY_CTRL_FSM_CFG_8_ADDR (E56PHY_PMD_BASE_ADDR+0x060)
+#define E56PHY_CTRL_FSM_CFG_8_TRAIN_ST7_EN 31,16
+
+#define E56PHY_CTRL_FSM_CFG_12_ADDR (E56PHY_PMD_BASE_ADDR+0x070)
+#define E56PHY_CTRL_FSM_CFG_12_TRAIN_ST15_EN 31,16
+
+#define E56PHY_CTRL_FSM_CFG_13_ADDR (E56PHY_PMD_BASE_ADDR+0x074)
+#define E56PHY_CTRL_FSM_CFG_13_TRAIN_ST0_DONE_EN 15,0
+#define E56PHY_CTRL_FSM_CFG_13_TRAIN_ST1_DONE_EN 31,16
+
+#define E56PHY_CTRL_FSM_CFG_14_ADDR (E56PHY_PMD_BASE_ADDR+0x078)
+#define E56PHY_CTRL_FSM_CFG_14_TRAIN_ST3_DONE_EN 31,16
+
+#define E56PHY_CTRL_FSM_CFG_15_ADDR (E56PHY_PMD_BASE_ADDR+0x07C)
+#define E56PHY_CTRL_FSM_CFG_15_TRAIN_ST4_DONE_EN 15,0
+
+#define E56PHY_CTRL_FSM_CFG_17_ADDR (E56PHY_PMD_BASE_ADDR+0x084)
+#define E56PHY_CTRL_FSM_CFG_17_TRAIN_ST8_DONE_EN 15,0
+
+#define E56PHY_CTRL_FSM_CFG_18_ADDR (E56PHY_PMD_BASE_ADDR+0x088)
+#define E56PHY_CTRL_FSM_CFG_18_TRAIN_ST10_DONE_EN 15,0
+
+#define E56PHY_CTRL_FSM_CFG_29_ADDR (E56PHY_PMD_BASE_ADDR+0x0B4)
+#define E56PHY_CTRL_FSM_CFG_29_TRAIN_ST15_DC_EN 31,16
+
+#define E56PHY_CTRL_FSM_CFG_33_ADDR (E56PHY_PMD_BASE_ADDR+0x0C4)
+#define E56PHY_CTRL_FSM_CFG_33_TRAIN0_RATE_SEL 15,0
+#define E56PHY_CTRL_FSM_CFG_33_TRAIN1_RATE_SEL 31,16
+
+#define E56PHY_CTRL_FSM_CFG_34_ADDR (E56PHY_PMD_BASE_ADDR+0x0C8)
+#define E56PHY_CTRL_FSM_CFG_34_TRAIN2_RATE_SEL 15,0
+#define E56PHY_CTRL_FSM_CFG_34_TRAIN3_RATE_SEL 31,16
+
+#define E56PHY_CTRL_FSM_RX_STAT_0_ADDR (E56PHY_PMD_BASE_ADDR+0x0FC)
+#define E56PHY_RXS0_OVRDEN_0_ADDR (E56PHY_PMD_BASE_ADDR+0x130)
+#define E56PHY_RXS0_OVRDEN_0_OVRD_EN_RXS0_RX0_SAMP_CAL_DONE_O 27,27
+
+#define E56PHY_RXS0_OVRDEN_1_ADDR (E56PHY_PMD_BASE_ADDR+0x134)
+#define E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_VGA_TRAIN_EN_I 14,14
+#define E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_CTLE_TRAIN_EN_I 16,16
+#define E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_CDR_EN_I 18,18
+#define E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_EN_I 23,23
+#define E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_DONE_O 24,24
+#define E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_DONE_O_LSB 24
+
+
+#define E56PHY_RXS0_OVRDEN_2_ADDR (E56PHY_PMD_BASE_ADDR+0x138)
+#define E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_OFST_ADAPT_EN_I 0,0
+#define E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_GAIN_ADAPT_EN_I 3,3
+#define E56PHY_RXS0_OVRDEN_2_OVRD_EN_RXS0_RX0_ADC_INTL_ADAPT_EN_I 6,6
+
+#define E56PHY_RXS0_OVRDVAL_0_ADDR (E56PHY_PMD_BASE_ADDR+0x140)
+#define E56PHY_RXS0_OVRDVAL_0_RXS0_RX0_SAMP_CAL_DONE_O 22,22
+
+#define E56PHY_RXS0_OVRDVAL_1_ADDR (E56PHY_PMD_BASE_ADDR+0x144)
+#define E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_VGA_TRAIN_EN_I 7,7
+#define E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_CTLE_TRAIN_EN_I 9,9
+#define E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_CDR_EN_I 11,11
+#define E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_EN_I 16,16
+#define E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_DONE_O 17,17
+#define E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_DONE_O_LSB 17
+#define E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I 25,25
+#define E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I 28,28
+#define E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_ADAPT_EN_I 31,31
+
+#define E56PHY_INTR_0_IDLE_ENTRY1 0x10000000
+#define E56PHY_INTR_0_ADDR (E56PHY_PMD_BASE_ADDR+0x1EC)
+#define E56PHY_INTR_0_ENABLE_ADDR (E56PHY_PMD_BASE_ADDR+0x1E0)
+
+#define E56PHY_INTR_1_IDLE_EXIT1 0x1
+#define E56PHY_INTR_1_ADDR (E56PHY_PMD_BASE_ADDR+0x1F0)
+#define E56PHY_INTR_1_ENABLE_ADDR (E56PHY_PMD_BASE_ADDR+0x1E4)
+
+#define E56PHY_KRT_TFSM_CFG_ADDR (E56PHY_PMD_BASE_ADDR+0x2B8)
+#define E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X1000K 7,0
+#define E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X8000K 15,8
+#define E56PHY_KRT_TFSM_CFGKRT_TFSM_HOLDOFF_TIMER_X256K 23,16
+
+#define E56PHY_FETX_FFE_TRAIN_CFG_0_ADDR (E56PHY_PMD_BASE_ADDR+0x2BC)
+#define E56PHY_FETX_FFE_TRAIN_CFG_0_KRT_FETX_INIT_FFE_CFG_2 9,8
+#define E56PHY_FETX_FFE_TRAIN_CFG_0_KRT_FETX_INIT_FFE_CFG_3 13,12
+
+#define PHYINIT_TIMEOUT 1000 //PHY initialization timeout value in 0.5ms unit
+
+#define E56G__BASEADDR 0x0
+
+typedef union {
+ struct {
+ u32 ana_lcpll_lf_vco_swing_ctrl_i : 4;
+ u32 ana_lcpll_lf_lpf_setcode_calib_i : 5;
+ u32 rsvd0 : 3;
+ u32 ana_lcpll_lf_vco_coarse_bin_i : 5;
+ u32 rsvd1 : 3;
+ u32 ana_lcpll_lf_vco_fine_therm_i : 8;
+ u32 ana_lcpll_lf_clkout_fb_ctrl_i : 2;
+ u32 rsvd2 : 2;
+ };
+ u32 reg;
+} E56G_CMS_ANA_OVRDVAL_7;
+#define E56G_CMS_ANA_OVRDVAL_7_ADDR (E56G__BASEADDR+0xccc)
+
+typedef union {
+ struct {
+ u32 ovrd_en_ana_lcpll_hf_vco_amp_status_o : 1;
+ u32 ovrd_en_ana_lcpll_hf_clkout_fb_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_hf_clkdiv_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_hf_en_odiv_i : 1;
+ u32 ovrd_en_ana_lcpll_hf_test_in_i : 1;
+ u32 ovrd_en_ana_lcpll_hf_test_out_o : 1;
+ u32 ovrd_en_ana_lcpll_lf_en_bias_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_en_loop_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_en_cp_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_icp_base_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_icp_fine_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_lpf_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_lpf_setcode_calib_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_set_lpf_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_en_vco_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_vco_sel_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_vco_swing_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_vco_coarse_bin_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_vco_fine_therm_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_vco_amp_status_o : 1;
+ u32 ovrd_en_ana_lcpll_lf_clkout_fb_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_clkdiv_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_en_odiv_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_test_in_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_test_out_o : 1;
+ u32 ovrd_en_ana_lcpll_hf_refclk_select_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_refclk_select_i : 1;
+ u32 ovrd_en_ana_lcpll_hf_clk_ref_sel_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_clk_ref_sel_i : 1;
+ u32 ovrd_en_ana_test_bias_i : 1;
+ u32 ovrd_en_ana_test_slicer_i : 1;
+ u32 ovrd_en_ana_test_sampler_i : 1;
+ };
+ u32 reg;
+} E56G_CMS_ANA_OVRDEN_1;
+
+#define E56G_CMS_ANA_OVRDEN_1_ADDR (E56G__BASEADDR+0xca8)
+
+typedef union {
+ struct {
+ u32 ana_lcpll_lf_test_in_i : 32;
+ };
+ u32 reg;
+} E56G_CMS_ANA_OVRDVAL_9;
+
+#define E56G_CMS_ANA_OVRDVAL_9_ADDR (E56G__BASEADDR+0xcd4)
+
+typedef union {
+ struct {
+ u32 ovrd_en_ana_bbcdr_vcofilt_byp_i : 1;
+ u32 ovrd_en_ana_bbcdr_coarse_i : 1;
+ u32 ovrd_en_ana_bbcdr_fine_i : 1;
+ u32 ovrd_en_ana_bbcdr_ultrafine_i : 1;
+ u32 ovrd_en_ana_en_bbcdr_i : 1;
+ u32 ovrd_en_ana_bbcdr_divctrl_i : 1;
+ u32 ovrd_en_ana_bbcdr_int_cstm_i : 1;
+ u32 ovrd_en_ana_bbcdr_prop_step_i : 1;
+ u32 ovrd_en_ana_en_bbcdr_clk_i : 1;
+ u32 ovrd_en_ana_test_bbcdr_i : 1;
+ u32 ovrd_en_ana_bbcdr_en_elv_cnt_ping0_pong1_i : 1;
+ u32 ovrd_en_ana_bbcdr_clrz_elv_cnt_ping_i : 1;
+ u32 ovrd_en_ana_bbcdr_clrz_elv_cnt_pong_i : 1;
+ u32 ovrd_en_ana_bbcdr_clrz_cnt_sync_i : 1;
+ u32 ovrd_en_ana_bbcdr_en_elv_cnt_rd_i : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_rdout_0_o : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_rdout_90_o : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_rdout_180_o : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_rdout_270_o : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_ping_0_o : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_ping_90_o : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_ping_180_o : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_ping_270_o : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_pong_0_o : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_pong_90_o : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_pong_180_o : 1;
+ u32 ovrd_en_ana_bbcdr_elv_cnt_pong_270_o : 1;
+ u32 ovrd_en_ana_en_bbcdr_samp_dac_i : 1;
+ u32 ovrd_en_ana_bbcdr_dac0_i : 1;
+ u32 ovrd_en_ana_bbcdr_dac90_i : 1;
+ u32 ovrd_en_ana_vga2_cload_in_cstm_i : 1;
+ u32 ovrd_en_ana_intlvr_cut_bw_i : 1;
+ };
+ u32 reg;
+} E56G__RXS0_ANA_OVRDEN_1;
+
+#define E56G__RXS0_ANA_OVRDEN_1_ADDR (E56G__BASEADDR+0x90)
+
+//-----Access structure typedef for Register:E56G__RXS0_OSC_CAL_N_CDR_0
+typedef union {
+ struct {
+ u32 prediv0 : 16;
+ u32 target_cnt0 : 16;
+ };
+ u32 reg;
+} E56G_RXS0_OSC_CAL_N_CDR_0;
+//-----MACRO defines for Register:E56G__RXS0_OSC_CAL_N_CDR_0
+#define E56G_RXS0_OSC_CAL_N_CDR_0_ADDR (E56G__BASEADDR+0x4)
+
+typedef union {
+ struct {
+ u32 osc_range_sel0 : 2;
+ u32 osc_range_sel1 : 2;
+ u32 osc_range_sel2 : 2;
+ u32 osc_range_sel3 : 2;
+ u32 vco_code_init : 11;
+ u32 calibrate_range_sel : 1;
+ u32 osc_current_boost_en0 : 1;
+ u32 osc_current_boost_en1 : 1;
+ u32 osc_current_boost_en2 : 1;
+ u32 osc_current_boost_en3 : 1;
+ u32 bbcdr_current_boost0 : 2;
+ u32 bbcdr_current_boost1 : 2;
+ u32 bbcdr_current_boost2 : 2;
+ u32 bbcdr_current_boost3 : 2;
+ };
+ u32 reg;
+} E56G_RXS0_OSC_CAL_N_CDR_4;
+//-----MACRO defines for Register:E56G__RXS0_OSC_CAL_N_CDR_4
+#define E56G_RXS0_OSC_CAL_N_CDR_4_ADDR (E56G__BASEADDR+0x14)
+
+//-----Access structure typedef for Register:E56G__RXS0_INTL_CONFIG_0
+typedef union {
+ struct {
+ u32 adc_intl2slice_delay0 : 16;
+ u32 adc_intl2slice_delay1 : 16;
+ };
+ u32 reg;
+} E56G_RXS0_INTL_CONFIG_0;
+//-----MACRO defines for Register:E56G__RXS0_INTL_CONFIG_0
+#define E56G_RXS0_INTL_CONFIG_0_ADDR (E56G__BASEADDR+0x20)
+
+//-----Access structure typedef for Register:E56G__RXS0_INTL_CONFIG_2
+typedef union {
+ struct {
+ u32 interleaver_hbw_disable0 : 1;
+ u32 interleaver_hbw_disable1 : 1;
+ u32 interleaver_hbw_disable2 : 1;
+ u32 interleaver_hbw_disable3 : 1;
+ u32 rsvd0 : 28;
+ };
+ u32 reg;
+} E56G_RXS0_INTL_CONFIG_2;
+//-----MACRO defines for Register:E56G__RXS0_INTL_CONFIG_2
+#define E56G_RXS0_INTL_CONFIG_2_ADDR (E56G__BASEADDR+0x28)
+
+typedef union {
+ struct {
+ u32 ovrd_en_ana_bbcdr_dac180_i : 1;
+ u32 ovrd_en_ana_bbcdr_dac270_i : 1;
+ u32 ovrd_en_ana_bbcdr_en_samp_cal_cnt_i : 1;
+ u32 ovrd_en_ana_bbcdr_clrz_samp_cal_cnt_i : 1;
+ u32 ovrd_en_ana_bbcdr_samp_cnt_0_o : 1;
+ u32 ovrd_en_ana_bbcdr_samp_cnt_90_o : 1;
+ u32 ovrd_en_ana_bbcdr_samp_cnt_180_o : 1;
+ u32 ovrd_en_ana_bbcdr_samp_cnt_270_o : 1;
+ u32 ovrd_en_ana_en_adcbuf1_i : 1;
+ u32 ovrd_en_ana_test_adcbuf1_i : 1;
+ u32 ovrd_en_ana_en_adc_clk4ui_i : 1;
+ u32 ovrd_en_ana_adc_clk_skew0_i : 1;
+ u32 ovrd_en_ana_adc_clk_skew90_i : 1;
+ u32 ovrd_en_ana_adc_clk_skew180_i : 1;
+ u32 ovrd_en_ana_adc_clk_skew270_i : 1;
+ u32 ovrd_en_ana_adc_update_skew_i : 1;
+ u32 ovrd_en_ana_en_adc_pi_i : 1;
+ u32 ovrd_en_ana_adc_pictrl_quad_i : 1;
+ u32 ovrd_en_ana_adc_pctrl_code_i : 1;
+ u32 ovrd_en_ana_adc_clkdiv_i : 1;
+ u32 ovrd_en_ana_test_adc_clkgen_i : 1;
+ u32 ovrd_en_ana_en_adc_i : 1;
+ u32 ovrd_en_ana_en_adc_vref_i : 1;
+ u32 ovrd_en_ana_vref_cnfg_i : 1;
+ u32 ovrd_en_ana_adc_data_cstm_o : 1;
+ u32 ovrd_en_ana_en_adccal_lpbk_i : 1;
+ u32 ovrd_en_ana_sel_adcoffset_cal_i : 1;
+ u32 ovrd_en_ana_sel_adcgain_cal_i : 1;
+ u32 ovrd_en_ana_adcgain_cal_swing_ctrl_i : 1;
+ u32 ovrd_en_ana_adc_gain_i : 1;
+ u32 ovrd_en_ana_vga_cload_out_cstm_i : 1;
+ u32 ovrd_en_ana_vga2_cload_out_cstm_i : 1;
+ };
+ u32 reg;
+} E56G__RXS0_ANA_OVRDEN_2;
+//-----MACRO defines for Register:E56G__RXS0_ANA_OVRDEN_2
+#define E56G__RXS0_ANA_OVRDEN_2_ADDR (E56G__BASEADDR+0x94)
+
+typedef union {
+ struct {
+ u32 ovrd_en_ana_adc_offset_i : 1;
+ u32 ovrd_en_ana_adc_slice_addr_i : 1;
+ u32 ovrd_en_ana_slice_wr_i : 1;
+ u32 ovrd_en_ana_test_adc_i : 1;
+ u32 ovrd_en_ana_test_adc_o : 1;
+ u32 ovrd_en_ana_spare_o : 8;
+ u32 ovrd_en_ana_sel_lpbk_i : 1;
+ u32 ovrd_en_ana_ana_debug_sel_i : 1;
+ u32 ovrd_en_ana_anabs_config_i : 1;
+ u32 ovrd_en_ana_en_anabs_i : 1;
+ u32 ovrd_en_ana_anabs_rxn_o : 1;
+ u32 ovrd_en_ana_anabs_rxp_o : 1;
+ u32 ovrd_en_ana_dser_clk_en_i : 1;
+ u32 ovrd_en_ana_dser_clk_config_i : 1;
+ u32 ovrd_en_ana_en_mmcdr_clk_obs_i : 1;
+ u32 ovrd_en_ana_skew_coarse0_fine1_i : 1;
+ u32 ovrd_en_ana_vddinoff_acore_dig_o : 1;
+ u32 ovrd_en_ana_vddinoff_dcore_dig_o : 1;
+ u32 ovrd_en_ana_vga2_boost_cstm_i : 1;
+ u32 ovrd_en_ana_adc_sel_vbgr_bias_i : 1;
+ u32 ovrd_en_ana_adc_nbuf_cnfg_i : 1;
+ u32 ovrd_en_ana_adc_pbuf_cnfg_i : 1;
+ u32 rsvd0 : 3;
+ };
+ u32 reg;
+} E56G__RXS0_ANA_OVRDEN_3;
+//-----MACRO defines for Register:E56G__RXS0_ANA_OVRDEN_3
+#define E56G__RXS0_ANA_OVRDEN_3_NUM 1
+#define E56G__RXS0_ANA_OVRDEN_3_ADDR (E56G__BASEADDR+0x98)
+
+//-----Access structure typedef for Register:E56G__RXS0_RXS_CFG_0
+typedef union {
+ struct {
+ u32 pam4_ab_swap_en : 1;
+ u32 dser_data_sel : 1;
+ u32 signal_type : 1;
+ u32 precode_en : 1;
+ u32 train_clk_gate_bypass_en : 14;
+ u32 rsvd0 : 14;
+ };
+ u32 reg;
+} E56G__RXS0_RXS_CFG_0;
+//-----MACRO defines for Register:E56G__RXS0_RXS_CFG_0
+#define E56G__RXS0_RXS_CFG_0_NUM 1
+#define E56G__RXS0_RXS_CFG_0_ADDR (E56G__BASEADDR+0x0)
+
+//-----Access structure typedef for Register:E56G__PMD_BASER_PMD_CONTROL
+typedef union {
+ struct {
+ u32 restart_training_ln0 : 1;
+ u32 training_enable_ln0 : 1;
+ u32 restart_training_ln1 : 1;
+ u32 training_enable_ln1 : 1;
+ u32 restart_training_ln2 : 1;
+ u32 training_enable_ln2 : 1;
+ u32 restart_training_ln3 : 1;
+ u32 training_enable_ln3 : 1;
+ u32 rsvd0 : 24;
+ };
+ u32 reg;
+} E56G__PMD_BASER_PMD_CONTROL;
+//-----MACRO defines for Register:E56G__PMD_BASER_PMD_CONTROL
+#define E56G__PMD_BASER_PMD_CONTROL_NUM 1
+#define E56G__PMD_BASER_PMD_CONTROL_ADDR (E56G__BASEADDR+0x1640)
+
+//-----Access structure typedef for Register:E56G__PMD_PMD_CFG_5
+typedef union {
+ struct {
+ u32 rx_to_tx_lpbk_en : 4;
+ u32 sel_wp_pmt_out : 4;
+ u32 sel_wp_pmt_clkout : 4;
+ u32 use_recent_marker_offset : 1;
+ u32 interrupt_debug_mode : 1;
+ u32 rsvd0 : 2;
+ u32 tx_ffe_coeff_update : 4;
+ u32 rsvd1 : 12;
+ };
+ u32 reg;
+} E56G__PMD_PMD_CFG_5;
+//-----MACRO defines for Register:E56G__PMD_PMD_CFG_5
+#define E56G__PMD_PMD_CFG_5_NUM 1
+#define E56G__PMD_PMD_CFG_5_ADDR (E56G__BASEADDR+0x1414)
+
+//-----Access structure typedef for Register:E56G__PMD_PMD_CFG_0
+typedef union {
+ struct {
+ u32 soft_reset : 1;
+ u32 pmd_en : 1;
+ u32 rsvd0 : 2;
+ u32 pll_refclk_sel : 2;
+ u32 rsvd1 : 2;
+ u32 pmd_mode : 1;
+ u32 rsvd2 : 3;
+ u32 tx_en_cfg : 4;
+ u32 rx_en_cfg : 4;
+ u32 pll_en_cfg : 2;
+ u32 rsvd3 : 2;
+ u32 pam4_precode_no_krt_en : 4;
+ u32 rsvd4 : 4;
+ };
+ u32 reg;
+} E56G__PMD_PMD_CFG_0;
+//-----MACRO defines for Register:E56G__PMD_PMD_CFG_0
+#define E56G__PMD_PMD_CFG_0_NUM 1
+#define E56G__PMD_PMD_CFG_0_ADDR (E56G__BASEADDR+0x1400)
+
+//-----Access structure typedef for Register:E56G__PMD_RXS0_OVRDEN_0
+typedef union {
+ struct {
+ u32 ovrd_en_rxs0_rx0_rstn_i : 1;
+ u32 ovrd_en_rxs0_rx0_bitclk_divctrl_i : 1;
+ u32 ovrd_en_rxs0_rx0_bitclk_rate_i : 1;
+ u32 ovrd_en_rxs0_rx0_symdata_width_i : 1;
+ u32 ovrd_en_rxs0_rx0_symdata_o : 1;
+ u32 ovrd_en_rxs0_rx0_precode_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_signal_type_i : 1;
+ u32 ovrd_en_rxs0_rx0_sync_detect_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_sync_o : 1;
+ u32 ovrd_en_rxs0_rx0_rate_select_i : 1;
+ u32 ovrd_en_rxs0_rx0_rterm_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_bias_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_ldo_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_ldo_rdy_i : 1;
+ u32 ovrd_en_rxs0_rx0_blwc_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_ctle_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_vga_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_osc_sel_i : 1;
+ u32 ovrd_en_rxs0_rx0_osc_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_clkgencdr_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_ctlecdr_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_samp_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_adc_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_osc_cal_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_osc_cal_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_osc_freq_error_o : 1;
+ u32 ovrd_en_rxs0_rx0_samp_cal_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_samp_cal_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_samp_cal_err_o : 1;
+ u32 ovrd_en_rxs0_rx0_adc_ofst_cal_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_adc_ofst_cal_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_adc_ofst_cal_error_o : 1;
+ };
+ u32 reg;
+} E56G__PMD_RXS0_OVRDEN_0;
+//-----MACRO defines for Register:E56G__PMD_RXS0_OVRDEN_0
+#define E56G__PMD_RXS0_OVRDEN_0_NUM 1
+#define E56G__PMD_RXS0_OVRDEN_0_ADDR (E56G__BASEADDR+0x1530)
+
+//-----Access structure typedef for Register:E56G__PMD_RXS0_OVRDEN_3
+typedef union {
+ struct {
+ u32 ovrd_en_rxs0_rx0_sparein_i : 8;
+ u32 ovrd_en_rxs0_rx0_spareout_o : 8;
+ u32 rsvd0 : 16;
+ };
+ u32 reg;
+} E56G__PMD_RXS0_OVRDEN_3;
+//-----MACRO defines for Register:E56G__PMD_RXS0_OVRDEN_3
+#define E56G__PMD_RXS0_OVRDEN_3_NUM 1
+#define E56G__PMD_RXS0_OVRDEN_3_ADDR (E56G__BASEADDR+0x153c)
+
+//-----Access structure typedef for Register:E56G__RXS0_DIG_OVRDEN_1
+typedef union {
+ struct {
+ u32 vco_code_cont_adj_done_ovrd_en : 1;
+ u32 dfe_coeffl_ovrd_en : 1;
+ u32 dfe_coeffh_ovrd_en : 1;
+ u32 rsvd0 : 1;
+ u32 top_comp_th_ovrd_en : 1;
+ u32 mid_comp_th_ovrd_en : 1;
+ u32 bot_comp_th_ovrd_en : 1;
+ u32 rsvd1 : 1;
+ u32 level_target_ovrd_en : 4;
+ u32 ffe_coeff_c0to3_ovrd_en : 4;
+ u32 ffe_coeff_c4to7_ovrd_en : 4;
+ u32 ffe_coeff_c8to11_ovrd_en : 4;
+ u32 ffe_coeff_c12to15_ovrd_en : 4;
+ u32 ffe_coeff_update_ovrd_en : 1;
+ u32 rsvd2 : 3;
+ };
+ u32 reg;
+} E56G__RXS0_DIG_OVRDEN_1;
+//-----MACRO defines for Register:E56G__RXS0_DIG_OVRDEN_1
+#define E56G__RXS0_DIG_OVRDEN_1_NUM 1
+#define E56G__RXS0_DIG_OVRDEN_1_ADDR (E56G__BASEADDR+0x160)
+
+//-----Access structure typedef for Register:E56G__RXS0_DFT_1
+typedef union {
+ struct {
+ u32 ber_en : 1;
+ u32 rsvd0 : 3;
+ u32 read_mode_en : 1;
+ u32 rsvd1 : 3;
+ u32 err_cnt_mode_all0_one1 : 1;
+ u32 rsvd2 : 3;
+ u32 init_lfsr_mode_continue0_restart1 : 1;
+ u32 rsvd3 : 3;
+ u32 pattern_sel : 4;
+ u32 rsvd4 : 12;
+ };
+ u32 reg;
+} E56G__RXS0_DFT_1;
+//-----MACRO defines for Register:E56G__RXS0_DFT_1
+#define E56G__RXS0_DFT_1_NUM 1
+#define E56G__RXS0_DFT_1_ADDR (E56G__BASEADDR+0xec)
+
+//-----Access structure typedef for Register:E56G__PMD_RXS0_OVRDEN_2
+typedef union {
+ struct {
+ u32 ovrd_en_rxs0_rx0_adc_ofst_adapt_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_adc_ofst_adapt_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_adc_ofst_adapt_error_o : 1;
+ u32 ovrd_en_rxs0_rx0_adc_gain_adapt_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_adc_gain_adapt_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_adc_gain_adapt_error_o : 1;
+ u32 ovrd_en_rxs0_rx0_adc_intl_adapt_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_adc_intl_adapt_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_adc_intl_adapt_error_o : 1;
+ u32 ovrd_en_rxs0_rx0_fe_ofst_adapt_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_fe_ofst_adapt_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_fe_ofst_adapt_error_o : 1;
+ u32 ovrd_en_rxs0_rx0_samp_th_adapt_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_samp_th_adapt_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_efuse_bits_i : 1;
+ u32 ovrd_en_rxs0_rx0_wp_pmt_in_i : 1;
+ u32 ovrd_en_rxs0_rx0_wp_pmt_out_o : 1;
+ u32 rsvd0 : 15;
+ };
+ u32 reg;
+} E56G__PMD_RXS0_OVRDEN_2;
+//-----MACRO defines for Register:E56G__PMD_RXS0_OVRDEN_2
+#define E56G__PMD_RXS0_OVRDEN_2_ADDR (E56G__BASEADDR+0x1538)
+
+typedef union {
+ struct {
+ u32 ana_bbcdr_osc_range_sel_i : 2;
+ u32 rsvd0 : 2;
+ u32 ana_bbcdr_coarse_i : 4;
+ u32 ana_bbcdr_fine_i : 3;
+ u32 rsvd1 : 1;
+ u32 ana_bbcdr_ultrafine_i : 3;
+ u32 rsvd2 : 1;
+ u32 ana_bbcdr_divctrl_i : 2;
+ u32 rsvd3 : 2;
+ u32 ana_bbcdr_int_cstm_i : 5;
+ u32 rsvd4 : 3;
+ u32 ana_bbcdr_prop_step_i : 4;
+ };
+ u32 reg;
+} E56G__RXS0_ANA_OVRDVAL_5;
+//-----MACRO defines for Register:E56G__RXS0_ANA_OVRDVAL_5
+#define E56G__RXS0_ANA_OVRDVAL_5_ADDR (E56G__BASEADDR+0xb4)
+
+typedef union {
+ struct {
+ u32 ana_adc_pictrl_quad_i : 2;
+ u32 rsvd0 : 2;
+ u32 ana_adc_clkdiv_i : 2;
+ u32 rsvd1 : 2;
+ u32 ana_test_adc_clkgen_i : 4;
+ u32 ana_vref_cnfg_i : 4;
+ u32 ana_adcgain_cal_swing_ctrl_i : 4;
+ u32 ana_adc_gain_i : 4;
+ u32 ana_adc_offset_i : 4;
+ u32 ana_ana_debug_sel_i : 4;
+ };
+ u32 reg;
+} E56G__RXS3_ANA_OVRDVAL_11;
+//-----MACRO defines for Register:E56G__RXS3_ANA_OVRDVAL_11
+#define E56G__RXS3_ANA_OVRDVAL_11_ADDR (E56G__BASEADDR+0x6cc)
+
+typedef union {
+ struct {
+ u32 rxs0_rx0_fe_ofst_cal_error_o : 1;
+ u32 rxs0_rx0_fom_en_i : 1;
+ u32 rxs0_rx0_idle_detect_en_i : 1;
+ u32 rxs0_rx0_idle_o : 1;
+ u32 rxs0_rx0_txffe_train_en_i : 1;
+ u32 rxs0_rx0_txffe_train_enack_o : 1;
+ u32 rxs0_rx0_txffe_train_done_o : 1;
+ u32 rxs0_rx0_vga_train_en_i : 1;
+ u32 rxs0_rx0_vga_train_done_o : 1;
+ u32 rxs0_rx0_ctle_train_en_i : 1;
+ u32 rxs0_rx0_ctle_train_done_o : 1;
+ u32 rxs0_rx0_cdr_en_i : 1;
+ u32 rxs0_rx0_cdr_rdy_o : 1;
+ u32 rxs0_rx0_ffe_train_en_i : 1;
+ u32 rxs0_rx0_ffe_train_done_o : 1;
+ u32 rxs0_rx0_mmpd_en_i : 1;
+ u32 rxs0_rx0_adc_intl_cal_en_i : 1;
+ u32 rxs0_rx0_adc_intl_cal_done_o : 1;
+ u32 rxs0_rx0_adc_intl_cal_error_o : 1;
+ u32 rxs0_rx0_dfe_train_en_i : 1;
+ u32 rxs0_rx0_dfe_train_done_o : 1;
+ u32 rxs0_rx0_vga_adapt_en_i : 1;
+ u32 rxs0_rx0_vga_adapt_done_o : 1;
+ u32 rxs0_rx0_ctle_adapt_en_i : 1;
+ u32 rxs0_rx0_ctle_adapt_done_o : 1;
+ u32 rxs0_rx0_adc_ofst_adapt_en_i : 1;
+ u32 rxs0_rx0_adc_ofst_adapt_done_o : 1;
+ u32 rxs0_rx0_adc_ofst_adapt_error_o : 1;
+ u32 rxs0_rx0_adc_gain_adapt_en_i : 1;
+ u32 rxs0_rx0_adc_gain_adapt_done_o : 1;
+ u32 rxs0_rx0_adc_gain_adapt_error_o : 1;
+ u32 rxs0_rx0_adc_intl_adapt_en_i : 1;
+ };
+ u32 reg;
+} E56G__PMD_RXS0_OVRDVAL_1;
+#define E56G__PMD_RXS0_OVRDVAL_1_ADDR (E56G__BASEADDR+0x1544)
+
+//-----Access structure typedef for Register:E56G__PMD_RXS1_OVRDVAL_1
+typedef union {
+ struct {
+ u32 rxs1_rx0_fe_ofst_cal_error_o : 1;
+ u32 rxs1_rx0_fom_en_i : 1;
+ u32 rxs1_rx0_idle_detect_en_i : 1;
+ u32 rxs1_rx0_idle_o : 1;
+ u32 rxs1_rx0_txffe_train_en_i : 1;
+ u32 rxs1_rx0_txffe_train_enack_o : 1;
+ u32 rxs1_rx0_txffe_train_done_o : 1;
+ u32 rxs1_rx0_vga_train_en_i : 1;
+ u32 rxs1_rx0_vga_train_done_o : 1;
+ u32 rxs1_rx0_ctle_train_en_i : 1;
+ u32 rxs1_rx0_ctle_train_done_o : 1;
+ u32 rxs1_rx0_cdr_en_i : 1;
+ u32 rxs1_rx0_cdr_rdy_o : 1;
+ u32 rxs1_rx0_ffe_train_en_i : 1;
+ u32 rxs1_rx0_ffe_train_done_o : 1;
+ u32 rxs1_rx0_mmpd_en_i : 1;
+ u32 rxs1_rx0_adc_intl_cal_en_i : 1;
+ u32 rxs1_rx0_adc_intl_cal_done_o : 1;
+ u32 rxs1_rx0_adc_intl_cal_error_o : 1;
+ u32 rxs1_rx0_dfe_train_en_i : 1;
+ u32 rxs1_rx0_dfe_train_done_o : 1;
+ u32 rxs1_rx0_vga_adapt_en_i : 1;
+ u32 rxs1_rx0_vga_adapt_done_o : 1;
+ u32 rxs1_rx0_ctle_adapt_en_i : 1;
+ u32 rxs1_rx0_ctle_adapt_done_o : 1;
+ u32 rxs1_rx0_adc_ofst_adapt_en_i : 1;
+ u32 rxs1_rx0_adc_ofst_adapt_done_o : 1;
+ u32 rxs1_rx0_adc_ofst_adapt_error_o : 1;
+ u32 rxs1_rx0_adc_gain_adapt_en_i : 1;
+ u32 rxs1_rx0_adc_gain_adapt_done_o : 1;
+ u32 rxs1_rx0_adc_gain_adapt_error_o : 1;
+ u32 rxs1_rx0_adc_intl_adapt_en_i : 1;
+ };
+ u32 reg;
+} E56G__PMD_RXS1_OVRDVAL_1;
+//-----MACRO defines for Register:E56G__PMD_RXS1_OVRDVAL_1
+#define E56G__PMD_RXS1_OVRDVAL_1_ADDR (E56G__BASEADDR+0x1570)
+
+//-----Access structure typedef for Register:E56G__PMD_RXS2_OVRDVAL_1
+typedef union {
+ struct {
+ u32 rxs2_rx0_fe_ofst_cal_error_o : 1;
+ u32 rxs2_rx0_fom_en_i : 1;
+ u32 rxs2_rx0_idle_detect_en_i : 1;
+ u32 rxs2_rx0_idle_o : 1;
+ u32 rxs2_rx0_txffe_train_en_i : 1;
+ u32 rxs2_rx0_txffe_train_enack_o : 1;
+ u32 rxs2_rx0_txffe_train_done_o : 1;
+ u32 rxs2_rx0_vga_train_en_i : 1;
+ u32 rxs2_rx0_vga_train_done_o : 1;
+ u32 rxs2_rx0_ctle_train_en_i : 1;
+ u32 rxs2_rx0_ctle_train_done_o : 1;
+ u32 rxs2_rx0_cdr_en_i : 1;
+ u32 rxs2_rx0_cdr_rdy_o : 1;
+ u32 rxs2_rx0_ffe_train_en_i : 1;
+ u32 rxs2_rx0_ffe_train_done_o : 1;
+ u32 rxs2_rx0_mmpd_en_i : 1;
+ u32 rxs2_rx0_adc_intl_cal_en_i : 1;
+ u32 rxs2_rx0_adc_intl_cal_done_o : 1;
+ u32 rxs2_rx0_adc_intl_cal_error_o : 1;
+ u32 rxs2_rx0_dfe_train_en_i : 1;
+ u32 rxs2_rx0_dfe_train_done_o : 1;
+ u32 rxs2_rx0_vga_adapt_en_i : 1;
+ u32 rxs2_rx0_vga_adapt_done_o : 1;
+ u32 rxs2_rx0_ctle_adapt_en_i : 1;
+ u32 rxs2_rx0_ctle_adapt_done_o : 1;
+ u32 rxs2_rx0_adc_ofst_adapt_en_i : 1;
+ u32 rxs2_rx0_adc_ofst_adapt_done_o : 1;
+ u32 rxs2_rx0_adc_ofst_adapt_error_o : 1;
+ u32 rxs2_rx0_adc_gain_adapt_en_i : 1;
+ u32 rxs2_rx0_adc_gain_adapt_done_o : 1;
+ u32 rxs2_rx0_adc_gain_adapt_error_o : 1;
+ u32 rxs2_rx0_adc_intl_adapt_en_i : 1;
+ };
+ u32 reg;
+} E56G__PMD_RXS2_OVRDVAL_1;
+//-----MACRO defines for Register:E56G__PMD_RXS2_OVRDVAL_1
+#define E56G__PMD_RXS2_OVRDVAL_1_ADDR (E56G__BASEADDR+0x159c)
+
+//-----Access structure typedef for Register:E56G__PMD_RXS3_OVRDVAL_1
+typedef union {
+ struct {
+ u32 rxs3_rx0_fe_ofst_cal_error_o : 1;
+ u32 rxs3_rx0_fom_en_i : 1;
+ u32 rxs3_rx0_idle_detect_en_i : 1;
+ u32 rxs3_rx0_idle_o : 1;
+ u32 rxs3_rx0_txffe_train_en_i : 1;
+ u32 rxs3_rx0_txffe_train_enack_o : 1;
+ u32 rxs3_rx0_txffe_train_done_o : 1;
+ u32 rxs3_rx0_vga_train_en_i : 1;
+ u32 rxs3_rx0_vga_train_done_o : 1;
+ u32 rxs3_rx0_ctle_train_en_i : 1;
+ u32 rxs3_rx0_ctle_train_done_o : 1;
+ u32 rxs3_rx0_cdr_en_i : 1;
+ u32 rxs3_rx0_cdr_rdy_o : 1;
+ u32 rxs3_rx0_ffe_train_en_i : 1;
+ u32 rxs3_rx0_ffe_train_done_o : 1;
+ u32 rxs3_rx0_mmpd_en_i : 1;
+ u32 rxs3_rx0_adc_intl_cal_en_i : 1;
+ u32 rxs3_rx0_adc_intl_cal_done_o : 1;
+ u32 rxs3_rx0_adc_intl_cal_error_o : 1;
+ u32 rxs3_rx0_dfe_train_en_i : 1;
+ u32 rxs3_rx0_dfe_train_done_o : 1;
+ u32 rxs3_rx0_vga_adapt_en_i : 1;
+ u32 rxs3_rx0_vga_adapt_done_o : 1;
+ u32 rxs3_rx0_ctle_adapt_en_i : 1;
+ u32 rxs3_rx0_ctle_adapt_done_o : 1;
+ u32 rxs3_rx0_adc_ofst_adapt_en_i : 1;
+ u32 rxs3_rx0_adc_ofst_adapt_done_o : 1;
+ u32 rxs3_rx0_adc_ofst_adapt_error_o : 1;
+ u32 rxs3_rx0_adc_gain_adapt_en_i : 1;
+ u32 rxs3_rx0_adc_gain_adapt_done_o : 1;
+ u32 rxs3_rx0_adc_gain_adapt_error_o : 1;
+ u32 rxs3_rx0_adc_intl_adapt_en_i : 1;
+ };
+ u32 reg;
+} E56G__PMD_RXS3_OVRDVAL_1;
+//-----MACRO defines for Register:E56G__PMD_RXS3_OVRDVAL_1
+#define E56G__PMD_RXS3_OVRDVAL_1_ADDR (E56G__BASEADDR+0x15c8)
+
+//-----Access structure typedef for Register:E56G__PMD_CTRL_FSM_RX_STAT_0
+typedef union {
+ struct {
+ u32 ctrl_fsm_rx0_st : 6;
+ u32 rsvd0 : 2;
+ u32 ctrl_fsm_rx1_st : 6;
+ u32 rsvd1 : 2;
+ u32 ctrl_fsm_rx2_st : 6;
+ u32 rsvd2 : 2;
+ u32 ctrl_fsm_rx3_st : 6;
+ u32 rsvd3 : 2;
+ };
+ u32 reg;
+} E56G__PMD_CTRL_FSM_RX_STAT_0;
+//-----MACRO defines for Register:E56G__PMD_CTRL_FSM_RX_STAT_0
+#define E56G__PMD_CTRL_FSM_RX_STAT_0_ADDR (E56G__BASEADDR+0x14fc)
+
+typedef union {
+ struct {
+ u32 ana_en_rterm_i : 1;
+ u32 ana_en_bias_i : 1;
+ u32 ana_en_ldo_i : 1;
+ u32 ana_rstn_i : 1;
+ u32 ana_en_blwc_i : 1;
+ u32 ana_en_acc_amp_i : 1;
+ u32 ana_en_acc_dac_i : 1;
+ u32 ana_en_afe_offset_cal_i : 1;
+ u32 ana_clk_offsetcal_i : 1;
+ u32 ana_acc_os_comp_o : 1;
+ u32 ana_en_ctle_i : 1;
+ u32 ana_ctle_bypass_i : 1;
+ u32 ana_en_ctlecdr_i : 1;
+ u32 ana_cdr_ctle_boost_i : 1;
+ u32 ana_en_vga_i : 1;
+ u32 ana_en_bbcdr_vco_i : 1;
+ u32 ana_bbcdr_vcofilt_byp_i : 1;
+ u32 ana_en_bbcdr_i : 1;
+ u32 ana_en_bbcdr_clk_i : 1;
+ u32 ana_bbcdr_en_elv_cnt_ping0_pong1_i : 1;
+ u32 ana_bbcdr_clrz_elv_cnt_ping_i : 1;
+ u32 ana_bbcdr_clrz_elv_cnt_pong_i : 1;
+ u32 ana_bbcdr_clrz_cnt_sync_i : 1;
+ u32 ana_bbcdr_en_elv_cnt_rd_i : 1;
+ u32 ana_bbcdr_elv_cnt_ping_0_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_90_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_180_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_270_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_0_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_90_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_180_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_270_o : 1;
+ };
+ u32 reg;
+} E56G__RXS0_ANA_OVRDVAL_0;
+#define E56G__RXS0_ANA_OVRDVAL_0_ADDR (E56G__BASEADDR+0xa0)
+
+//-----Access structure typedef for Register:E56G__RXS1_ANA_OVRDVAL_0
+typedef union {
+ struct {
+ u32 ana_en_rterm_i : 1;
+ u32 ana_en_bias_i : 1;
+ u32 ana_en_ldo_i : 1;
+ u32 ana_rstn_i : 1;
+ u32 ana_en_blwc_i : 1;
+ u32 ana_en_acc_amp_i : 1;
+ u32 ana_en_acc_dac_i : 1;
+ u32 ana_en_afe_offset_cal_i : 1;
+ u32 ana_clk_offsetcal_i : 1;
+ u32 ana_acc_os_comp_o : 1;
+ u32 ana_en_ctle_i : 1;
+ u32 ana_ctle_bypass_i : 1;
+ u32 ana_en_ctlecdr_i : 1;
+ u32 ana_cdr_ctle_boost_i : 1;
+ u32 ana_en_vga_i : 1;
+ u32 ana_en_bbcdr_vco_i : 1;
+ u32 ana_bbcdr_vcofilt_byp_i : 1;
+ u32 ana_en_bbcdr_i : 1;
+ u32 ana_en_bbcdr_clk_i : 1;
+ u32 ana_bbcdr_en_elv_cnt_ping0_pong1_i : 1;
+ u32 ana_bbcdr_clrz_elv_cnt_ping_i : 1;
+ u32 ana_bbcdr_clrz_elv_cnt_pong_i : 1;
+ u32 ana_bbcdr_clrz_cnt_sync_i : 1;
+ u32 ana_bbcdr_en_elv_cnt_rd_i : 1;
+ u32 ana_bbcdr_elv_cnt_ping_0_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_90_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_180_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_270_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_0_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_90_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_180_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_270_o : 1;
+ };
+ u32 reg;
+} E56G__RXS1_ANA_OVRDVAL_0;
+//-----MACRO defines for Register:E56G__RXS1_ANA_OVRDVAL_0
+#define E56G__RXS1_ANA_OVRDVAL_0_ADDR (E56G__BASEADDR+0x2a0)
+
+//-----Access structure typedef for Register:E56G__RXS2_ANA_OVRDVAL_0
+typedef union {
+ struct {
+ u32 ana_en_rterm_i : 1;
+ u32 ana_en_bias_i : 1;
+ u32 ana_en_ldo_i : 1;
+ u32 ana_rstn_i : 1;
+ u32 ana_en_blwc_i : 1;
+ u32 ana_en_acc_amp_i : 1;
+ u32 ana_en_acc_dac_i : 1;
+ u32 ana_en_afe_offset_cal_i : 1;
+ u32 ana_clk_offsetcal_i : 1;
+ u32 ana_acc_os_comp_o : 1;
+ u32 ana_en_ctle_i : 1;
+ u32 ana_ctle_bypass_i : 1;
+ u32 ana_en_ctlecdr_i : 1;
+ u32 ana_cdr_ctle_boost_i : 1;
+ u32 ana_en_vga_i : 1;
+ u32 ana_en_bbcdr_vco_i : 1;
+ u32 ana_bbcdr_vcofilt_byp_i : 1;
+ u32 ana_en_bbcdr_i : 1;
+ u32 ana_en_bbcdr_clk_i : 1;
+ u32 ana_bbcdr_en_elv_cnt_ping0_pong1_i : 1;
+ u32 ana_bbcdr_clrz_elv_cnt_ping_i : 1;
+ u32 ana_bbcdr_clrz_elv_cnt_pong_i : 1;
+ u32 ana_bbcdr_clrz_cnt_sync_i : 1;
+ u32 ana_bbcdr_en_elv_cnt_rd_i : 1;
+ u32 ana_bbcdr_elv_cnt_ping_0_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_90_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_180_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_270_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_0_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_90_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_180_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_270_o : 1;
+ };
+ u32 reg;
+} E56G__RXS2_ANA_OVRDVAL_0;
+//-----MACRO defines for Register:E56G__RXS2_ANA_OVRDVAL_0
+#define E56G__RXS2_ANA_OVRDVAL_0_ADDR (E56G__BASEADDR+0x4a0)
+
+//-----Access structure typedef for Register:E56G__RXS3_ANA_OVRDVAL_0
+typedef union {
+ struct {
+ u32 ana_en_rterm_i : 1;
+ u32 ana_en_bias_i : 1;
+ u32 ana_en_ldo_i : 1;
+ u32 ana_rstn_i : 1;
+ u32 ana_en_blwc_i : 1;
+ u32 ana_en_acc_amp_i : 1;
+ u32 ana_en_acc_dac_i : 1;
+ u32 ana_en_afe_offset_cal_i : 1;
+ u32 ana_clk_offsetcal_i : 1;
+ u32 ana_acc_os_comp_o : 1;
+ u32 ana_en_ctle_i : 1;
+ u32 ana_ctle_bypass_i : 1;
+ u32 ana_en_ctlecdr_i : 1;
+ u32 ana_cdr_ctle_boost_i : 1;
+ u32 ana_en_vga_i : 1;
+ u32 ana_en_bbcdr_vco_i : 1;
+ u32 ana_bbcdr_vcofilt_byp_i : 1;
+ u32 ana_en_bbcdr_i : 1;
+ u32 ana_en_bbcdr_clk_i : 1;
+ u32 ana_bbcdr_en_elv_cnt_ping0_pong1_i : 1;
+ u32 ana_bbcdr_clrz_elv_cnt_ping_i : 1;
+ u32 ana_bbcdr_clrz_elv_cnt_pong_i : 1;
+ u32 ana_bbcdr_clrz_cnt_sync_i : 1;
+ u32 ana_bbcdr_en_elv_cnt_rd_i : 1;
+ u32 ana_bbcdr_elv_cnt_ping_0_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_90_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_180_o : 1;
+ u32 ana_bbcdr_elv_cnt_ping_270_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_0_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_90_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_180_o : 1;
+ u32 ana_bbcdr_elv_cnt_pong_270_o : 1;
+ };
+ u32 reg;
+} E56G__RXS3_ANA_OVRDVAL_0;
+//-----MACRO defines for Register:E56G__RXS3_ANA_OVRDVAL_0
+#define E56G__RXS3_ANA_OVRDVAL_0_ADDR (E56G__BASEADDR+0x6a0)
+
+//-----Access structure typedef for Register:E56G__RXS0_ANA_OVRDEN_0
+typedef union {
+ struct {
+ u32 ovrd_en_ana_en_rterm_i : 1;
+ u32 ovrd_en_ana_trim_rterm_i : 1;
+ u32 ovrd_en_ana_en_bias_i : 1;
+ u32 ovrd_en_ana_test_bias_i : 1;
+ u32 ovrd_en_ana_en_ldo_i : 1;
+ u32 ovrd_en_ana_test_ldo_i : 1;
+ u32 ovrd_en_ana_rstn_i : 1;
+ u32 ovrd_en_ana_en_blwc_i : 1;
+ u32 ovrd_en_ana_en_acc_amp_i : 1;
+ u32 ovrd_en_ana_en_acc_dac_i : 1;
+ u32 ovrd_en_ana_en_afe_offset_cal_i : 1;
+ u32 ovrd_en_ana_clk_offsetcal_i : 1;
+ u32 ovrd_en_ana_acc_os_code_i : 1;
+ u32 ovrd_en_ana_acc_os_comp_o : 1;
+ u32 ovrd_en_ana_test_acc_i : 1;
+ u32 ovrd_en_ana_en_ctle_i : 1;
+ u32 ovrd_en_ana_ctle_bypass_i : 1;
+ u32 ovrd_en_ana_ctle_cz_cstm_i : 1;
+ u32 ovrd_en_ana_ctle_cload_cstm_i : 1;
+ u32 ovrd_en_ana_test_ctle_i : 1;
+ u32 ovrd_en_ana_lfeq_ctrl_cstm_i : 1;
+ u32 ovrd_en_ana_en_ctlecdr_i : 1;
+ u32 ovrd_en_ana_cdr_ctle_boost_i : 1;
+ u32 ovrd_en_ana_test_ctlecdr_i : 1;
+ u32 ovrd_en_ana_en_vga_i : 1;
+ u32 ovrd_en_ana_vga_gain_cstm_i : 1;
+ u32 ovrd_en_ana_vga_cload_in_cstm_i : 1;
+ u32 ovrd_en_ana_test_vga_i : 1;
+ u32 ovrd_en_ana_en_bbcdr_vco_i : 1;
+ u32 ovrd_en_ana_bbcdr_osc_range_sel_i : 1;
+ u32 ovrd_en_ana_sel_vga_gain_byp_i : 1;
+ u32 ovrd_en_ana_vga2_gain_cstm_i : 1;
+ };
+ u32 reg;
+} E56G__RXS0_ANA_OVRDEN_0;
+//-----MACRO defines for Register:E56G__RXS0_ANA_OVRDEN_0
+#define E56G__RXS0_ANA_OVRDEN_0_ADDR (E56G__BASEADDR+0x8c)
+
+//-----Access structure typedef for Register:E56G__RXS1_ANA_OVRDEN_0
+typedef union {
+ struct {
+ u32 ovrd_en_ana_en_rterm_i : 1;
+ u32 ovrd_en_ana_trim_rterm_i : 1;
+ u32 ovrd_en_ana_en_bias_i : 1;
+ u32 ovrd_en_ana_test_bias_i : 1;
+ u32 ovrd_en_ana_en_ldo_i : 1;
+ u32 ovrd_en_ana_test_ldo_i : 1;
+ u32 ovrd_en_ana_rstn_i : 1;
+ u32 ovrd_en_ana_en_blwc_i : 1;
+ u32 ovrd_en_ana_en_acc_amp_i : 1;
+ u32 ovrd_en_ana_en_acc_dac_i : 1;
+ u32 ovrd_en_ana_en_afe_offset_cal_i : 1;
+ u32 ovrd_en_ana_clk_offsetcal_i : 1;
+ u32 ovrd_en_ana_acc_os_code_i : 1;
+ u32 ovrd_en_ana_acc_os_comp_o : 1;
+ u32 ovrd_en_ana_test_acc_i : 1;
+ u32 ovrd_en_ana_en_ctle_i : 1;
+ u32 ovrd_en_ana_ctle_bypass_i : 1;
+ u32 ovrd_en_ana_ctle_cz_cstm_i : 1;
+ u32 ovrd_en_ana_ctle_cload_cstm_i : 1;
+ u32 ovrd_en_ana_test_ctle_i : 1;
+ u32 ovrd_en_ana_lfeq_ctrl_cstm_i : 1;
+ u32 ovrd_en_ana_en_ctlecdr_i : 1;
+ u32 ovrd_en_ana_cdr_ctle_boost_i : 1;
+ u32 ovrd_en_ana_test_ctlecdr_i : 1;
+ u32 ovrd_en_ana_en_vga_i : 1;
+ u32 ovrd_en_ana_vga_gain_cstm_i : 1;
+ u32 ovrd_en_ana_vga_cload_in_cstm_i : 1;
+ u32 ovrd_en_ana_test_vga_i : 1;
+ u32 ovrd_en_ana_en_bbcdr_vco_i : 1;
+ u32 ovrd_en_ana_bbcdr_osc_range_sel_i : 1;
+ u32 ovrd_en_ana_sel_vga_gain_byp_i : 1;
+ u32 ovrd_en_ana_vga2_gain_cstm_i : 1;
+ };
+ u32 reg;
+} E56G__RXS1_ANA_OVRDEN_0;
+//-----MACRO defines for Register:E56G__RXS1_ANA_OVRDEN_0
+#define E56G__RXS1_ANA_OVRDEN_0_ADDR (E56G__BASEADDR+0x28c)
+
+//-----Access structure typedef for Register:E56G__RXS2_ANA_OVRDEN_0
+typedef union {
+ struct {
+ u32 ovrd_en_ana_en_rterm_i : 1;
+ u32 ovrd_en_ana_trim_rterm_i : 1;
+ u32 ovrd_en_ana_en_bias_i : 1;
+ u32 ovrd_en_ana_test_bias_i : 1;
+ u32 ovrd_en_ana_en_ldo_i : 1;
+ u32 ovrd_en_ana_test_ldo_i : 1;
+ u32 ovrd_en_ana_rstn_i : 1;
+ u32 ovrd_en_ana_en_blwc_i : 1;
+ u32 ovrd_en_ana_en_acc_amp_i : 1;
+ u32 ovrd_en_ana_en_acc_dac_i : 1;
+ u32 ovrd_en_ana_en_afe_offset_cal_i : 1;
+ u32 ovrd_en_ana_clk_offsetcal_i : 1;
+ u32 ovrd_en_ana_acc_os_code_i : 1;
+ u32 ovrd_en_ana_acc_os_comp_o : 1;
+ u32 ovrd_en_ana_test_acc_i : 1;
+ u32 ovrd_en_ana_en_ctle_i : 1;
+ u32 ovrd_en_ana_ctle_bypass_i : 1;
+ u32 ovrd_en_ana_ctle_cz_cstm_i : 1;
+ u32 ovrd_en_ana_ctle_cload_cstm_i : 1;
+ u32 ovrd_en_ana_test_ctle_i : 1;
+ u32 ovrd_en_ana_lfeq_ctrl_cstm_i : 1;
+ u32 ovrd_en_ana_en_ctlecdr_i : 1;
+ u32 ovrd_en_ana_cdr_ctle_boost_i : 1;
+ u32 ovrd_en_ana_test_ctlecdr_i : 1;
+ u32 ovrd_en_ana_en_vga_i : 1;
+ u32 ovrd_en_ana_vga_gain_cstm_i : 1;
+ u32 ovrd_en_ana_vga_cload_in_cstm_i : 1;
+ u32 ovrd_en_ana_test_vga_i : 1;
+ u32 ovrd_en_ana_en_bbcdr_vco_i : 1;
+ u32 ovrd_en_ana_bbcdr_osc_range_sel_i : 1;
+ u32 ovrd_en_ana_sel_vga_gain_byp_i : 1;
+ u32 ovrd_en_ana_vga2_gain_cstm_i : 1;
+ };
+ u32 reg;
+} E56G__RXS2_ANA_OVRDEN_0;
+//-----MACRO defines for Register:E56G__RXS2_ANA_OVRDEN_0
+#define E56G__RXS2_ANA_OVRDEN_0_ADDR (E56G__BASEADDR+0x48c)
+
+//-----Access structure typedef for Register:E56G__RXS3_ANA_OVRDEN_0
+typedef union {
+ struct {
+ u32 ovrd_en_ana_en_rterm_i : 1;
+ u32 ovrd_en_ana_trim_rterm_i : 1;
+ u32 ovrd_en_ana_en_bias_i : 1;
+ u32 ovrd_en_ana_test_bias_i : 1;
+ u32 ovrd_en_ana_en_ldo_i : 1;
+ u32 ovrd_en_ana_test_ldo_i : 1;
+ u32 ovrd_en_ana_rstn_i : 1;
+ u32 ovrd_en_ana_en_blwc_i : 1;
+ u32 ovrd_en_ana_en_acc_amp_i : 1;
+ u32 ovrd_en_ana_en_acc_dac_i : 1;
+ u32 ovrd_en_ana_en_afe_offset_cal_i : 1;
+ u32 ovrd_en_ana_clk_offsetcal_i : 1;
+ u32 ovrd_en_ana_acc_os_code_i : 1;
+ u32 ovrd_en_ana_acc_os_comp_o : 1;
+ u32 ovrd_en_ana_test_acc_i : 1;
+ u32 ovrd_en_ana_en_ctle_i : 1;
+ u32 ovrd_en_ana_ctle_bypass_i : 1;
+ u32 ovrd_en_ana_ctle_cz_cstm_i : 1;
+ u32 ovrd_en_ana_ctle_cload_cstm_i : 1;
+ u32 ovrd_en_ana_test_ctle_i : 1;
+ u32 ovrd_en_ana_lfeq_ctrl_cstm_i : 1;
+ u32 ovrd_en_ana_en_ctlecdr_i : 1;
+ u32 ovrd_en_ana_cdr_ctle_boost_i : 1;
+ u32 ovrd_en_ana_test_ctlecdr_i : 1;
+ u32 ovrd_en_ana_en_vga_i : 1;
+ u32 ovrd_en_ana_vga_gain_cstm_i : 1;
+ u32 ovrd_en_ana_vga_cload_in_cstm_i : 1;
+ u32 ovrd_en_ana_test_vga_i : 1;
+ u32 ovrd_en_ana_en_bbcdr_vco_i : 1;
+ u32 ovrd_en_ana_bbcdr_osc_range_sel_i : 1;
+ u32 ovrd_en_ana_sel_vga_gain_byp_i : 1;
+ u32 ovrd_en_ana_vga2_gain_cstm_i : 1;
+ };
+ u32 reg;
+} E56G__RXS3_ANA_OVRDEN_0;
+//-----MACRO defines for Register:E56G__RXS3_ANA_OVRDEN_0
+#define E56G__RXS3_ANA_OVRDEN_0_NUM 1
+#define E56G__RXS3_ANA_OVRDEN_0_ADDR (E56G__BASEADDR+0x68c)
+
+//-----Access structure typedef for Register:E56G__RXS0_ANA_OVRDVAL_3
+typedef union {
+ struct {
+ u32 ana_ctle_cz_cstm_i : 5;
+ u32 rsvd0 : 3;
+ u32 ana_ctle_cload_cstm_i : 5;
+ u32 rsvd1 : 3;
+ u32 ana_test_ctle_i : 2;
+ u32 rsvd2 : 2;
+ u32 ana_lfeq_ctrl_cstm_i : 4;
+ u32 ana_test_ctlecdr_i : 2;
+ u32 rsvd3 : 2;
+ u32 ana_vga_cload_in_cstm_i : 3;
+ u32 rsvd4 : 1;
+ };
+ u32 reg;
+} E56G__RXS0_ANA_OVRDVAL_3;
+//-----MACRO defines for Register:E56G__RXS0_ANA_OVRDVAL_3
+#define E56G__RXS0_ANA_OVRDVAL_3_NUM 1
+#define E56G__RXS0_ANA_OVRDVAL_3_ADDR (E56G__BASEADDR+0xac)
+
+//-----Access structure typedef for Register:E56G__RXS1_ANA_OVRDVAL_3
+typedef union {
+ struct {
+ u32 ana_ctle_cz_cstm_i : 5;
+ u32 rsvd0 : 3;
+ u32 ana_ctle_cload_cstm_i : 5;
+ u32 rsvd1 : 3;
+ u32 ana_test_ctle_i : 2;
+ u32 rsvd2 : 2;
+ u32 ana_lfeq_ctrl_cstm_i : 4;
+ u32 ana_test_ctlecdr_i : 2;
+ u32 rsvd3 : 2;
+ u32 ana_vga_cload_in_cstm_i : 3;
+ u32 rsvd4 : 1;
+ };
+ u32 reg;
+} E56G__RXS1_ANA_OVRDVAL_3;
+//-----MACRO defines for Register:E56G__RXS1_ANA_OVRDVAL_3
+#define E56G__RXS1_ANA_OVRDVAL_3_ADDR (E56G__BASEADDR+0x2ac)
+
+//-----Access structure typedef for Register:E56G__RXS2_ANA_OVRDVAL_3
+typedef union {
+ struct {
+ u32 ana_ctle_cz_cstm_i : 5;
+ u32 rsvd0 : 3;
+ u32 ana_ctle_cload_cstm_i : 5;
+ u32 rsvd1 : 3;
+ u32 ana_test_ctle_i : 2;
+ u32 rsvd2 : 2;
+ u32 ana_lfeq_ctrl_cstm_i : 4;
+ u32 ana_test_ctlecdr_i : 2;
+ u32 rsvd3 : 2;
+ u32 ana_vga_cload_in_cstm_i : 3;
+ u32 rsvd4 : 1;
+ };
+ u32 reg;
+} E56G__RXS2_ANA_OVRDVAL_3;
+//-----MACRO defines for Register:E56G__RXS2_ANA_OVRDVAL_3
+#define E56G__RXS2_ANA_OVRDVAL_3_ADDR (E56G__BASEADDR+0x4ac)
+
+//-----Access structure typedef for Register:E56G__RXS3_ANA_OVRDVAL_3
+typedef union {
+ struct {
+ u32 ana_ctle_cz_cstm_i : 5;
+ u32 rsvd0 : 3;
+ u32 ana_ctle_cload_cstm_i : 5;
+ u32 rsvd1 : 3;
+ u32 ana_test_ctle_i : 2;
+ u32 rsvd2 : 2;
+ u32 ana_lfeq_ctrl_cstm_i : 4;
+ u32 ana_test_ctlecdr_i : 2;
+ u32 rsvd3 : 2;
+ u32 ana_vga_cload_in_cstm_i : 3;
+ u32 rsvd4 : 1;
+ };
+ u32 reg;
+} E56G__RXS3_ANA_OVRDVAL_3;
+//-----MACRO defines for Register:E56G__RXS3_ANA_OVRDVAL_3
+#define E56G__RXS3_ANA_OVRDVAL_3_ADDR (E56G__BASEADDR+0x6ac)
+
+//-----Access structure typedef for Register:E56G__PMD_RXS0_OVRDEN_1
+typedef union {
+ struct {
+ u32 ovrd_en_rxs0_rx0_adc_gain_cal_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_adc_gain_cal_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_adc_gain_cal_error_o : 1;
+ u32 ovrd_en_rxs0_rx0_fe_ofst_cal_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_fe_ofst_cal_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_fe_ofst_cal_error_o : 1;
+ u32 ovrd_en_rxs0_rx0_fom_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_idle_detect_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_idle_o : 1;
+ u32 ovrd_en_rxs0_rx0_txffe_train_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_txffe_coeff_rst_i : 1;
+ u32 ovrd_en_rxs0_rx0_txffe_train_enack_o : 1;
+ u32 ovrd_en_rxs0_rx0_txffe_train_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_txffe_coeff_change_o : 1;
+ u32 ovrd_en_rxs0_rx0_vga_train_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_vga_train_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_ctle_train_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_ctle_train_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_cdr_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_cdr_rdy_o : 1;
+ u32 ovrd_en_rxs0_rx0_ffe_train_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_ffe_train_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_mmpd_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_adc_intl_cal_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_adc_intl_cal_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_adc_intl_cal_error_o : 1;
+ u32 ovrd_en_rxs0_rx0_dfe_train_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_dfe_train_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_vga_adapt_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_vga_adapt_done_o : 1;
+ u32 ovrd_en_rxs0_rx0_ctle_adapt_en_i : 1;
+ u32 ovrd_en_rxs0_rx0_ctle_adapt_done_o : 1;
+ };
+ u32 reg;
+} E56G__PMD_RXS0_OVRDEN_1;
+//-----MACRO defines for Register:E56G__PMD_RXS0_OVRDEN_1
+#define E56G__PMD_RXS0_OVRDEN_1_NUM 1
+#define E56G__PMD_RXS0_OVRDEN_1_ADDR (E56G__BASEADDR+0x1534)
+
+//-----Access structure typedef for Register:E56G__PMD_RXS1_OVRDEN_1
+typedef union {
+ struct {
+ u32 ovrd_en_rxs1_rx0_adc_gain_cal_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_adc_gain_cal_done_o : 1;
+ u32 ovrd_en_rxs1_rx0_adc_gain_cal_error_o : 1;
+ u32 ovrd_en_rxs1_rx0_fe_ofst_cal_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_fe_ofst_cal_done_o : 1;
+ u32 ovrd_en_rxs1_rx0_fe_ofst_cal_error_o : 1;
+ u32 ovrd_en_rxs1_rx0_fom_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_idle_detect_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_idle_o : 1;
+ u32 ovrd_en_rxs1_rx0_txffe_train_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_txffe_coeff_rst_i : 1;
+ u32 ovrd_en_rxs1_rx0_txffe_train_enack_o : 1;
+ u32 ovrd_en_rxs1_rx0_txffe_train_done_o : 1;
+ u32 ovrd_en_rxs1_rx0_txffe_coeff_change_o : 1;
+ u32 ovrd_en_rxs1_rx0_vga_train_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_vga_train_done_o : 1;
+ u32 ovrd_en_rxs1_rx0_ctle_train_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_ctle_train_done_o : 1;
+ u32 ovrd_en_rxs1_rx0_cdr_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_cdr_rdy_o : 1;
+ u32 ovrd_en_rxs1_rx0_ffe_train_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_ffe_train_done_o : 1;
+ u32 ovrd_en_rxs1_rx0_mmpd_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_adc_intl_cal_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_adc_intl_cal_done_o : 1;
+ u32 ovrd_en_rxs1_rx0_adc_intl_cal_error_o : 1;
+ u32 ovrd_en_rxs1_rx0_dfe_train_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_dfe_train_done_o : 1;
+ u32 ovrd_en_rxs1_rx0_vga_adapt_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_vga_adapt_done_o : 1;
+ u32 ovrd_en_rxs1_rx0_ctle_adapt_en_i : 1;
+ u32 ovrd_en_rxs1_rx0_ctle_adapt_done_o : 1;
+ };
+ u32 reg;
+} E56G__PMD_RXS1_OVRDEN_1;
+//-----MACRO defines for Register:E56G__PMD_RXS1_OVRDEN_1
+#define E56G__PMD_RXS1_OVRDEN_1_ADDR (E56G__BASEADDR+0x1560)
+
+//-----Access structure typedef for Register:E56G__PMD_RXS2_OVRDEN_1
+typedef union {
+ struct {
+ u32 ovrd_en_rxs2_rx0_adc_gain_cal_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_adc_gain_cal_done_o : 1;
+ u32 ovrd_en_rxs2_rx0_adc_gain_cal_error_o : 1;
+ u32 ovrd_en_rxs2_rx0_fe_ofst_cal_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_fe_ofst_cal_done_o : 1;
+ u32 ovrd_en_rxs2_rx0_fe_ofst_cal_error_o : 1;
+ u32 ovrd_en_rxs2_rx0_fom_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_idle_detect_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_idle_o : 1;
+ u32 ovrd_en_rxs2_rx0_txffe_train_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_txffe_coeff_rst_i : 1;
+ u32 ovrd_en_rxs2_rx0_txffe_train_enack_o : 1;
+ u32 ovrd_en_rxs2_rx0_txffe_train_done_o : 1;
+ u32 ovrd_en_rxs2_rx0_txffe_coeff_change_o : 1;
+ u32 ovrd_en_rxs2_rx0_vga_train_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_vga_train_done_o : 1;
+ u32 ovrd_en_rxs2_rx0_ctle_train_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_ctle_train_done_o : 1;
+ u32 ovrd_en_rxs2_rx0_cdr_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_cdr_rdy_o : 1;
+ u32 ovrd_en_rxs2_rx0_ffe_train_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_ffe_train_done_o : 1;
+ u32 ovrd_en_rxs2_rx0_mmpd_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_adc_intl_cal_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_adc_intl_cal_done_o : 1;
+ u32 ovrd_en_rxs2_rx0_adc_intl_cal_error_o : 1;
+ u32 ovrd_en_rxs2_rx0_dfe_train_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_dfe_train_done_o : 1;
+ u32 ovrd_en_rxs2_rx0_vga_adapt_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_vga_adapt_done_o : 1;
+ u32 ovrd_en_rxs2_rx0_ctle_adapt_en_i : 1;
+ u32 ovrd_en_rxs2_rx0_ctle_adapt_done_o : 1;
+ };
+ u32 reg;
+} E56G__PMD_RXS2_OVRDEN_1;
+//-----MACRO defines for Register:E56G__PMD_RXS2_OVRDEN_1
+#define E56G__PMD_RXS2_OVRDEN_1_ADDR (E56G__BASEADDR+0x158c)
+
+//-----Access structure typedef for Register:E56G__PMD_RXS3_OVRDEN_1
+typedef union {
+ struct {
+ u32 ovrd_en_rxs3_rx0_adc_gain_cal_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_adc_gain_cal_done_o : 1;
+ u32 ovrd_en_rxs3_rx0_adc_gain_cal_error_o : 1;
+ u32 ovrd_en_rxs3_rx0_fe_ofst_cal_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_fe_ofst_cal_done_o : 1;
+ u32 ovrd_en_rxs3_rx0_fe_ofst_cal_error_o : 1;
+ u32 ovrd_en_rxs3_rx0_fom_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_idle_detect_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_idle_o : 1;
+ u32 ovrd_en_rxs3_rx0_txffe_train_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_txffe_coeff_rst_i : 1;
+ u32 ovrd_en_rxs3_rx0_txffe_train_enack_o : 1;
+ u32 ovrd_en_rxs3_rx0_txffe_train_done_o : 1;
+ u32 ovrd_en_rxs3_rx0_txffe_coeff_change_o : 1;
+ u32 ovrd_en_rxs3_rx0_vga_train_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_vga_train_done_o : 1;
+ u32 ovrd_en_rxs3_rx0_ctle_train_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_ctle_train_done_o : 1;
+ u32 ovrd_en_rxs3_rx0_cdr_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_cdr_rdy_o : 1;
+ u32 ovrd_en_rxs3_rx0_ffe_train_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_ffe_train_done_o : 1;
+ u32 ovrd_en_rxs3_rx0_mmpd_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_adc_intl_cal_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_adc_intl_cal_done_o : 1;
+ u32 ovrd_en_rxs3_rx0_adc_intl_cal_error_o : 1;
+ u32 ovrd_en_rxs3_rx0_dfe_train_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_dfe_train_done_o : 1;
+ u32 ovrd_en_rxs3_rx0_vga_adapt_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_vga_adapt_done_o : 1;
+ u32 ovrd_en_rxs3_rx0_ctle_adapt_en_i : 1;
+ u32 ovrd_en_rxs3_rx0_ctle_adapt_done_o : 1;
+ };
+ u32 reg;
+} E56G__PMD_RXS3_OVRDEN_1;
+//-----MACRO defines for Register:E56G__PMD_RXS3_OVRDEN_1
+#define E56G__PMD_RXS3_OVRDEN_1_ADDR (E56G__BASEADDR+0x15b8)
+
+#define E56G__RXS0_FOM_18__ADDR (E56G__BASEADDR+0x1f8)
+#define E56G__RXS0_FOM_18__DFE_COEFFL_HINT__MSB 11
+#define E56G__RXS0_FOM_18__DFE_COEFFL_HINT__LSB 0
+#define E56G__RXS0_FOM_18__DFE_COEFFH_HINT__MSB 23
+#define E56G__RXS0_FOM_18__DFE_COEFFH_HINT__LSB 12
+#define E56G__RXS0_FOM_18__DFE_COEFF_HINT_LOAD__MSB 25
+#define E56G__RXS0_FOM_18__DFE_COEFF_HINT_LOAD__LSB 25
+
+#define DEFAULT_TEMP 40
+#define HIGH_TEMP 70
+
+#define E56PHY_RX_RDY_ST 0x1B
+
+#define S10G_CMVAR_RANGE_H 0x3
+#define S10G_CMVAR_RANGE_L 0x2
+#define S25G_CMVAR_RANGE_H 0x1
+#define S25G_CMVAR_RANGE_L 0x0
+
+#define S25G_CMVAR_RANGE_H 0x1
+#define S25G_CMVAR_RANGE_L 0x0
+#define S25G_CMVAR_SEC_LOW_TH 0x1A
+#define S25G_CMVAR_SEC_HIGH_TH 0x1D
+#define S25G_CMVAR_UFINE_MAX 0x2
+#define S25G_CMVAR_FINE_MAX 0x7
+#define S25G_CMVAR_COARSE_MAX 0xF
+#define S25G_CMVAR_UFINE_UMAX_WRAP 0x0
+#define S25G_CMVAR_UFINE_FMAX_WRAP 0x0
+#define S25G_CMVAR_FINE_FMAX_WRAP 0x2
+#define S25G_CMVAR_UFINE_MIN 0x0
+#define S25G_CMVAR_FINE_MIN 0x0
+#define S25G_CMVAR_COARSE_MIN 0x1
+#define S25G_CMVAR_UFINE_UMIN_WRAP 0x2
+#define S25G_CMVAR_UFINE_FMIN_WRAP 0x2
+#define S25G_CMVAR_FINE_FMIN_WRAP 0x5
+
+#define S10G_CMVAR_RANGE_H 0x3
+#define S10G_CMVAR_RANGE_L 0x2
+#define S10G_CMVAR_SEC_LOW_TH 0x1A
+#define S10G_CMVAR_SEC_HIGH_TH 0x1D
+#define S10G_CMVAR_UFINE_MAX 0x7
+#define S10G_CMVAR_FINE_MAX 0x7
+#define S10G_CMVAR_COARSE_MAX 0xF
+#define S10G_CMVAR_UFINE_UMAX_WRAP 0x6
+#define S10G_CMVAR_UFINE_FMAX_WRAP 0x7
+#define S10G_CMVAR_FINE_FMAX_WRAP 0x1
+#define S10G_CMVAR_UFINE_MIN 0x0
+#define S10G_CMVAR_FINE_MIN 0x0
+#define S10G_CMVAR_COARSE_MIN 0x1
+#define S10G_CMVAR_UFINE_UMIN_WRAP 0x2
+#define S10G_CMVAR_UFINE_FMIN_WRAP 0x2
+#define S10G_CMVAR_FINE_FMIN_WRAP 0x5
+
+#define S10G_TX_FFE_CFG_MAIN 0x24242424
+#define S10G_TX_FFE_CFG_PRE1 0x0
+#define S10G_TX_FFE_CFG_PRE2 0x0
+#define S10G_TX_FFE_CFG_POST 0x0
+#define S25G_TX_FFE_CFG_MAIN 49
+#define S25G_TX_FFE_CFG_PRE1 4
+#define S25G_TX_FFE_CFG_PRE2 1
+#define S25G_TX_FFE_CFG_POST 9
+
+#define S25G_TX_FFE_CFG_DAC_MAIN 0x2a2a2a2a
+#define S25G_TX_FFE_CFG_DAC_PRE1 0x03
+#define S25G_TX_FFE_CFG_DAC_PRE2 0x0
+#define S25G_TX_FFE_CFG_DAC_POST 0x11
+
+#define BYPASS_CTLE_TAG 0x0
+
+#define S10G_PHY_RX_CTLE_TAPWT_WEIGHT1 0x1
+#define S10G_PHY_RX_CTLE_TAPWT_WEIGHT2 0x0
+#define S10G_PHY_RX_CTLE_TAPWT_WEIGHT3 0x0
+#define S10G_PHY_RX_CTLE_TAP_FRACP1 0x18
+#define S10G_PHY_RX_CTLE_TAP_FRACP2 0x0
+#define S10G_PHY_RX_CTLE_TAP_FRACP3 0x0
+
+#define S25G_PHY_RX_CTLE_TAPWT_WEIGHT1 0x1
+#define S25G_PHY_RX_CTLE_TAPWT_WEIGHT2 0x0
+#define S25G_PHY_RX_CTLE_TAPWT_WEIGHT3 0x0
+#define S25G_PHY_RX_CTLE_TAP_FRACP1 0x18
+#define S25G_PHY_RX_CTLE_TAP_FRACP2 0x0
+#define S25G_PHY_RX_CTLE_TAP_FRACP3 0x0
+
+#define TXGBE_E56_PHY_LINK_UP 0x4
+
+void set_fields_e56(unsigned int *src_data, unsigned int bit_high,
+ unsigned int bit_low, unsigned int set_value);
+int txgbe_e56_rx_rd_second_code_40g(struct txgbe_hw *hw, int *SECOND_CODE, int lane);
+int txgbe_e56_rx_rd_second_code(struct txgbe_hw *hw, int *SECOND_CODE);
+u32 txgbe_e56_cfg_40g(struct txgbe_hw *hw);
+u32 txgbe_e56_cfg_25g(struct txgbe_hw *hw);
+u32 txgbe_e56_cfg_10g(struct txgbe_hw *hw);
+int txgbe_temp_track_seq(struct txgbe_hw *hw, u32 speed);
+int txgbe_e56_get_temp(struct txgbe_hw *hw, int *pTempData);
+int txgbe_set_link_to_amlite(struct txgbe_hw *hw, u32 speed);
+int txgbe_e56_reconfig_rx(struct txgbe_hw *hw, u32 speed);
+s32 txgbe_e56_check_phy_link(struct txgbe_hw *hw, u32 *speed,
+ bool *link_up);
+s32 txgbe_e56_fec_set(struct txgbe_hw *hw);
+s32 txgbe_e56_fec_polling(struct txgbe_hw *hw, bool *link_up);
+
+#endif /* _TXGBE_E56_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_e56_bp.c b/drivers/net/txgbe/base/txgbe_e56_bp.c
new file mode 100644
index 0000000000..e80db9ca0d
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_e56_bp.c
@@ -0,0 +1,2238 @@
+#include "txgbe_e56.h"
+#include "txgbe_hw.h"
+#include "txgbe_osdep.h"
+#include "txgbe_phy.h"
+#include "txgbe_e56_bp.h"
+#include "txgbe.h"
+#include "../txgbe_logs.h"
+
+#define CL74_KRTR_TRAINNING_TIMEOUT 2000
+#define AN74_TRAINNING_MODE 1
+
+typedef union {
+ struct {
+ u32 tx0_cursor_factor : 7;
+ u32 rsvd0 : 1;
+ u32 tx1_cursor_factor : 7;
+ u32 rsvd1 : 1;
+ u32 tx2_cursor_factor : 7;
+ u32 rsvd2 : 1;
+ u32 tx3_cursor_factor : 7;
+ u32 rsvd3 : 1;
+ };
+ u32 reg;
+} E56G__PMD_TX_FFE_CFG_1;
+
+#define E56G__PMD_TX_FFE_CFG_1_NUM 1
+#define E56G__PMD_TX_FFE_CFG_1_ADDR (E56G__BASEADDR+0x141c)
+#define E56G__PMD_TX_FFE_CFG_1_PTR ((volatile E56G__PMD_TX_FFE_CFG_1*)(E56G__PMD_TX_FFE_CFG_1_ADDR))
+#define E56G__PMD_TX_FFE_CFG_1_STRIDE 4
+#define E56G__PMD_TX_FFE_CFG_1_SIZE 32
+#define E56G__PMD_TX_FFE_CFG_1_ACC_SIZE 32
+#define E56G__PMD_TX_FFE_CFG_1_READ_MSB 30
+#define E56G__PMD_TX_FFE_CFG_1_READ_LSB 0
+#define E56G__PMD_TX_FFE_CFG_1_WRITE_MSB 30
+#define E56G__PMD_TX_FFE_CFG_1_WRITE_LSB 0
+#define E56G__PMD_TX_FFE_CFG_1_RESET_VALUE 0x3f3f3f3f
+
+typedef union {
+ struct {
+ u32 tx0_precursor1_factor : 6;
+ u32 rsvd0 : 2;
+ u32 tx1_precursor1_factor : 6;
+ u32 rsvd1 : 2;
+ u32 tx2_precursor1_factor : 6;
+ u32 rsvd2 : 2;
+ u32 tx3_precursor1_factor : 6;
+ u32 rsvd3 : 2;
+ };
+ u32 reg;
+} E56G__PMD_TX_FFE_CFG_2;
+
+#define E56G__PMD_TX_FFE_CFG_2_NUM 1
+#define E56G__PMD_TX_FFE_CFG_2_ADDR (E56G__BASEADDR+0x1420)
+#define E56G__PMD_TX_FFE_CFG_2_PTR ((volatile E56G__PMD_TX_FFE_CFG_2*)(E56G__PMD_TX_FFE_CFG_2_ADDR))
+#define E56G__PMD_TX_FFE_CFG_2_STRIDE 4
+#define E56G__PMD_TX_FFE_CFG_2_SIZE 32
+#define E56G__PMD_TX_FFE_CFG_2_ACC_SIZE 32
+#define E56G__PMD_TX_FFE_CFG_2_READ_MSB 29
+#define E56G__PMD_TX_FFE_CFG_2_READ_LSB 0
+#define E56G__PMD_TX_FFE_CFG_2_WRITE_MSB 29
+#define E56G__PMD_TX_FFE_CFG_2_WRITE_LSB 0
+#define E56G__PMD_TX_FFE_CFG_2_RESET_VALUE 0x0
+
+typedef union {
+ struct {
+ u32 tx0_precursor2_factor : 6;
+ u32 rsvd0 : 2;
+ u32 tx1_precursor2_factor : 6;
+ u32 rsvd1 : 2;
+ u32 tx2_precursor2_factor : 6;
+ u32 rsvd2 : 2;
+ u32 tx3_precursor2_factor : 6;
+ u32 rsvd3 : 2;
+ };
+ u32 reg;
+} E56G__PMD_TX_FFE_CFG_3;
+#define E56G__PMD_TX_FFE_CFG_3_NUM 1
+#define E56G__PMD_TX_FFE_CFG_3_ADDR (E56G__BASEADDR+0x1424)
+#define E56G__PMD_TX_FFE_CFG_3_PTR ((volatile E56G__PMD_TX_FFE_CFG_3*)(E56G__PMD_TX_FFE_CFG_3_ADDR))
+#define E56G__PMD_TX_FFE_CFG_3_STRIDE 4
+#define E56G__PMD_TX_FFE_CFG_3_SIZE 32
+#define E56G__PMD_TX_FFE_CFG_3_ACC_SIZE 32
+#define E56G__PMD_TX_FFE_CFG_3_READ_MSB 29
+#define E56G__PMD_TX_FFE_CFG_3_READ_LSB 0
+#define E56G__PMD_TX_FFE_CFG_3_WRITE_MSB 29
+#define E56G__PMD_TX_FFE_CFG_3_WRITE_LSB 0
+#define E56G__PMD_TX_FFE_CFG_3_RESET_VALUE 0x0
+
+typedef union {
+ struct {
+ u32 tx0_postcursor_factor : 6;
+ u32 rsvd0 : 2;
+ u32 tx1_postcursor_factor : 6;
+ u32 rsvd1 : 2;
+ u32 tx2_postcursor_factor : 6;
+ u32 rsvd2 : 2;
+ u32 tx3_postcursor_factor : 6;
+ u32 rsvd3 : 2;
+ };
+ u32 reg;
+} E56G__PMD_TX_FFE_CFG_4;
+#define E56G__PMD_TX_FFE_CFG_4_NUM 1
+#define E56G__PMD_TX_FFE_CFG_4_ADDR (E56G__BASEADDR+0x1428)
+#define E56G__PMD_TX_FFE_CFG_4_PTR ((volatile E56G__PMD_TX_FFE_CFG_4*)(E56G__PMD_TX_FFE_CFG_4_ADDR))
+#define E56G__PMD_TX_FFE_CFG_4_STRIDE 4
+#define E56G__PMD_TX_FFE_CFG_4_SIZE 32
+#define E56G__PMD_TX_FFE_CFG_4_ACC_SIZE 32
+#define E56G__PMD_TX_FFE_CFG_4_READ_MSB 29
+#define E56G__PMD_TX_FFE_CFG_4_READ_LSB 0
+#define E56G__PMD_TX_FFE_CFG_4_WRITE_MSB 29
+#define E56G__PMD_TX_FFE_CFG_4_WRITE_LSB 0
+#define E56G__PMD_TX_FFE_CFG_4_RESET_VALUE 0x0
+
+typedef union {
+ struct {
+ u32 ana_lcpll_lf_vco_swing_ctrl_i : 4;
+ u32 ana_lcpll_lf_lpf_setcode_calib_i : 5;
+ u32 rsvd0 : 3;
+ u32 ana_lcpll_lf_vco_coarse_bin_i : 5;
+ u32 rsvd1 : 3;
+ u32 ana_lcpll_lf_vco_fine_therm_i : 8;
+ u32 ana_lcpll_lf_clkout_fb_ctrl_i : 2;
+ u32 rsvd2 : 2;
+ };
+ u32 reg;
+} E56G__CMS_ANA_OVRDVAL_7;
+#define E56G__CMS_ANA_OVRDVAL_7_NUM 1
+#define E56G__CMS_ANA_OVRDVAL_7_ADDR (E56G__BASEADDR+0xccc)
+#define E56G__CMS_ANA_OVRDVAL_7_PTR ((volatile E56G__CMS_ANA_OVRDVAL_7*)(E56G__CMS_ANA_OVRDVAL_7_ADDR))
+#define E56G__CMS_ANA_OVRDVAL_7_STRIDE 4
+#define E56G__CMS_ANA_OVRDVAL_7_SIZE 32
+#define E56G__CMS_ANA_OVRDVAL_7_ACC_SIZE 32
+#define E56G__CMS_ANA_OVRDVAL_7_READ_MSB 29
+#define E56G__CMS_ANA_OVRDVAL_7_READ_LSB 0
+#define E56G__CMS_ANA_OVRDVAL_7_WRITE_MSB 29
+#define E56G__CMS_ANA_OVRDVAL_7_WRITE_LSB 0
+#define E56G__CMS_ANA_OVRDVAL_7_RESET_VALUE 0x0
+
+typedef union {
+ struct {
+ u32 ovrd_en_ana_lcpll_hf_vco_amp_status_o : 1;
+ u32 ovrd_en_ana_lcpll_hf_clkout_fb_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_hf_clkdiv_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_hf_en_odiv_i : 1;
+ u32 ovrd_en_ana_lcpll_hf_test_in_i : 1;
+ u32 ovrd_en_ana_lcpll_hf_test_out_o : 1;
+ u32 ovrd_en_ana_lcpll_lf_en_bias_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_en_loop_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_en_cp_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_icp_base_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_icp_fine_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_lpf_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_lpf_setcode_calib_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_set_lpf_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_en_vco_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_vco_sel_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_vco_swing_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_vco_coarse_bin_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_vco_fine_therm_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_vco_amp_status_o : 1;
+ u32 ovrd_en_ana_lcpll_lf_clkout_fb_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_clkdiv_ctrl_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_en_odiv_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_test_in_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_test_out_o : 1;
+ u32 ovrd_en_ana_lcpll_hf_refclk_select_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_refclk_select_i : 1;
+ u32 ovrd_en_ana_lcpll_hf_clk_ref_sel_i : 1;
+ u32 ovrd_en_ana_lcpll_lf_clk_ref_sel_i : 1;
+ u32 ovrd_en_ana_test_bias_i : 1;
+ u32 ovrd_en_ana_test_slicer_i : 1;
+ u32 ovrd_en_ana_test_sampler_i : 1;
+ };
+ u32 reg;
+} E56G__CMS_ANA_OVRDEN_1;
+#define E56G__CMS_ANA_OVRDEN_1_NUM 1
+#define E56G__CMS_ANA_OVRDEN_1_ADDR (E56G__BASEADDR+0xca8)
+#define E56G__CMS_ANA_OVRDEN_1_PTR ((volatile E56G__CMS_ANA_OVRDEN_1*)(E56G__CMS_ANA_OVRDEN_1_ADDR))
+#define E56G__CMS_ANA_OVRDEN_1_STRIDE 4
+#define E56G__CMS_ANA_OVRDEN_1_SIZE 32
+#define E56G__CMS_ANA_OVRDEN_1_ACC_SIZE 32
+#define E56G__CMS_ANA_OVRDEN_1_READ_MSB 31
+#define E56G__CMS_ANA_OVRDEN_1_READ_LSB 0
+#define E56G__CMS_ANA_OVRDEN_1_WRITE_MSB 31
+#define E56G__CMS_ANA_OVRDEN_1_WRITE_LSB 0
+#define E56G__CMS_ANA_OVRDEN_1_RESET_VALUE 0x0
+
+typedef union {
+ struct {
+ u32 ana_lcpll_lf_test_in_i : 32;
+ };
+ u32 reg;
+} E56G__CMS_ANA_OVRDVAL_9;
+#define E56G__CMS_ANA_OVRDVAL_9_NUM 1
+#define E56G__CMS_ANA_OVRDVAL_9_ADDR (E56G__BASEADDR+0xcd4)
+#define E56G__CMS_ANA_OVRDVAL_9_PTR ((volatile E56G__CMS_ANA_OVRDVAL_9*)(E56G__CMS_ANA_OVRDVAL_9_ADDR))
+#define E56G__CMS_ANA_OVRDVAL_9_STRIDE 4
+#define E56G__CMS_ANA_OVRDVAL_9_SIZE 32
+#define E56G__CMS_ANA_OVRDVAL_9_ACC_SIZE 32
+#define E56G__CMS_ANA_OVRDVAL_9_READ_MSB 31
+#define E56G__CMS_ANA_OVRDVAL_9_READ_LSB 0
+#define E56G__CMS_ANA_OVRDVAL_9_WRITE_MSB 31
+#define E56G__CMS_ANA_OVRDVAL_9_WRITE_LSB 0
+#define E56G__CMS_ANA_OVRDVAL_9_RESET_VALUE 0x0
+
+#define SFP2_RS0 5
+#define SFP2_RS1 4
+#define SFP2_TX_DISABLE 1
+#define SFP2_TX_FAULT 0
+#define SFP2_RX_LOS_BIT 3
+#ifdef PHYINIT_TIMEOUT
+#undef PHYINIT_TIMEOUT
+#define PHYINIT_TIMEOUT 2000
+#endif
+
+#define E56PHY_CMS_ANA_OVRDEN_0_ADDR (E56PHY_CMS_BASE_ADDR+0xA4)
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_REFCLK_BUF_DAISY_EN_I 0,0
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_REFCLK_BUF_PAD_EN_I 1,1
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_REFCLK_BUF_PAD_EN_I_LSB 1
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_VDDINOFF_DCORE_DIG_O 2,2
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_BG_EN_I 11,11
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_BG_EN_I_LSB 11
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_BG_TESTIN_I 12,12
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_BG_TESTIN_I_LSB 12
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_RESCAL_I 13,13
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_RESCAL_I_LSB 13
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_RESCAL_COMP_O 14,14
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_RESCAL_COMP_O_LSB 14
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_RESCAL_CODE_I 15,15
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_RESCAL_CODE_I_LSB 15
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_LDO_CORE_I 16,16
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_LDO_CORE_I_LSB 16
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_TEST_LDO_I 17,17
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_TEST_LDO_I_LSB 17
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_ANA_DEBUG_SEL_I 18,18
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_ANA_DEBUG_SEL_I_LSB 18
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_EN_BIAS_I 19,19
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_EN_BIAS_I_LSB 19
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_EN_LOOP_I 20,20
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_EN_LOOP_I_LSB 20
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_EN_CP_I 21,21
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_EN_CP_I_LSB 21
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_ICP_BASE_I 22,22
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_ICP_BASE_I_LSB 22
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_ICP_FINE_I 23,23
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_ICP_FINE_I_LSB 23
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_LPF_CTRL_I 24,24
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_LPF_CTRL_I_LSB 24
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_LPF_SETCODE_CALIB_I 25,25
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_LPF_SETCODE_CALIB_I_LSB 25
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_SET_LPF_I 26,26
+#define E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_VCO_SWING_CTRL_I 29,29
+
+#define E56PHY_CMS_ANA_OVRDVAL_2_ANA_LCPLL_HF_LPF_SETCODE_CALIB_I 20,16
+#define E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_LF_LPF_SETCODE_CALIB_I 12,12
+#define E56PHY_CMS_ANA_OVRDVAL_7_ADDR (E56PHY_CMS_BASE_ADDR+0xCC)
+#define E56PHY_CMS_ANA_OVRDVAL_5_ADDR (E56PHY_CMS_BASE_ADDR+0xC4)
+#define E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_LF_TEST_IN_I 23,23
+#define E56PHY_CMS_ANA_OVRDVAL_9_ADDR (E56PHY_CMS_BASE_ADDR+0xD4)
+#define E56PHY_CMS_ANA_OVRDVAL_10_ADDR (E56PHY_CMS_BASE_ADDR+0xD8)
+#define E56PHY_CMS_ANA_OVRDVAL_7_ANA_LCPLL_LF_LPF_SETCODE_CALIB_I 8,4
+#define E56PHY_CTRL_FSM_CFG_0_CONT_ON_ADC_GAIN_CAL_ERR 5,5
+
+static void
+txgbe_e56_set_rxs_ufine_le_max(struct txgbe_hw *hw, u32 speed)
+{
+ u32 rdata;
+ u32 ULTRAFINE_CODE;
+
+ u32 CMVAR_UFINE_MAX = 0;
+
+ if (speed == 10)
+ CMVAR_UFINE_MAX = S10G_CMVAR_UFINE_MAX;
+ else if (speed == 25)
+ CMVAR_UFINE_MAX = S25G_CMVAR_UFINE_MAX;
+
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ ULTRAFINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i);
+
+ while (ULTRAFINE_CODE > CMVAR_UFINE_MAX) {
+ ULTRAFINE_CODE = ULTRAFINE_CODE - 1;
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i,
+ ULTRAFINE_CODE);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i,
+ 1);
+ msleep(20);
+ }
+}
+
+static int txgbe_e56_rxs_osc_init_for_temp_track_range(struct txgbe_hw *hw,
+ u32 speed)
+{
+ int OFFSET_CENTRE_RANGE_H, OFFSET_CENTRE_RANGE_L, RANGE_FINAL;
+ int RX_COARSE_MID_TD, CMVAR_RANGE_H = 0, CMVAR_RANGE_L = 0;
+ int T = 40;
+ u32 addr, rdata, timer;
+ int status = 0;
+
+ /* 1. Read the temperature T just before RXS is enabled. */
+ txgbe_e56_get_temp(hw, &T);
+
+ /* 2. Define software variable RX_COARSE_MID_TD */
+ if (T < -5)
+ RX_COARSE_MID_TD = 10;
+ else if (T < 30)
+ RX_COARSE_MID_TD = 9;
+ else if (T < 65)
+ RX_COARSE_MID_TD = 8;
+ else if (T < 100)
+ RX_COARSE_MID_TD = 7;
+ else
+ RX_COARSE_MID_TD = 6;
+
+ /* Set CMVAR_RANGE_H/L based on the link speed mode */
+ if (speed == 10 || speed == 40) {
+ CMVAR_RANGE_H = S10G_CMVAR_RANGE_H;
+ CMVAR_RANGE_L = S10G_CMVAR_RANGE_L;
+ } else if (speed == 25) {
+ CMVAR_RANGE_H = S25G_CMVAR_RANGE_H;
+ CMVAR_RANGE_L = S25G_CMVAR_RANGE_L;
+ }
+
+ /* TBD select all lane */
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_5_ANA_BBCDR_OSC_RANGE_SEL_I,
+ CMVAR_RANGE_H);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_BBCDR_OSC_RANGE_SEL_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* 4. Do SEQ::RX_ENABLE to enable RXS */
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_0_RXS0_RX0_SAMP_CAL_DONE_O, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDEN_0_OVRD_EN_RXS0_RX0_SAMP_CAL_DONE_O, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ timer = 0;
+ while ((rdata & 0x3f) != 0x9) {
+ usec_delay(100);
+ rdata = 0;
+ addr = E56PHY_INTR_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if ((rdata & 0x100) == 0x100)
+ break;
+ rdata = 0;
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ return -1;
+ }
+ }
+
+ rdata = 0;
+ addr = E56PHY_RXS_ANA_OVRDVAL_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ OFFSET_CENTRE_RANGE_H = (rdata >> 4) & 0xf;
+ if (OFFSET_CENTRE_RANGE_H > RX_COARSE_MID_TD)
+ OFFSET_CENTRE_RANGE_H = OFFSET_CENTRE_RANGE_H - RX_COARSE_MID_TD;
+ else
+ OFFSET_CENTRE_RANGE_H = RX_COARSE_MID_TD - OFFSET_CENTRE_RANGE_H;
+
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ timer = 0;
+ while (1) {
+ usec_delay(100);
+ rdata = 0;
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if ((rdata & 0x3f) == 0x21)
+ break;
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ return -1;
+ }
+ }
+
+ rdata = 0;
+ addr = E56PHY_INTR_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ wr32_ephy(hw, addr, 0);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_5_ANA_BBCDR_OSC_RANGE_SEL_I,
+ CMVAR_RANGE_L);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_BBCDR_OSC_RANGE_SEL_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_0_RXS0_RX0_SAMP_CAL_DONE_O, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_0_OVRD_EN_RXS0_RX0_SAMP_CAL_DONE_O,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ /* poll CTRL_FSM_RX_ST */
+ timer = 0;
+ while ((rdata & 0x3f) != 0x9) {
+ usec_delay(100);
+ rdata = 0;
+ addr = E56PHY_INTR_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if ((rdata & 0x100) == 0x100)
+ break;
+ rdata = 0;
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ return -1;
+ }
+ }
+
+ rdata = 0;
+ addr = E56PHY_RXS_ANA_OVRDVAL_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ OFFSET_CENTRE_RANGE_L = (rdata >> 4) & 0xf;
+ if (OFFSET_CENTRE_RANGE_L > RX_COARSE_MID_TD)
+ OFFSET_CENTRE_RANGE_L = OFFSET_CENTRE_RANGE_L - RX_COARSE_MID_TD;
+
+ else
+ OFFSET_CENTRE_RANGE_L = RX_COARSE_MID_TD - OFFSET_CENTRE_RANGE_L;
+
+ /*13. Perform below calculation in software. */
+ if (OFFSET_CENTRE_RANGE_L < OFFSET_CENTRE_RANGE_H)
+ RANGE_FINAL = CMVAR_RANGE_L;
+ else
+ RANGE_FINAL = CMVAR_RANGE_H;
+
+ /* 14. SEQ::RX_DISABLE to disable RXS. Poll ALIAS::PDIG::CTRL_FSM_RX_ST */
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0x0);
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ wr32_ephy(hw, addr, rdata);
+
+ timer = 0;
+ while (1) {
+ usec_delay(100);
+ rdata = 0;
+ addr = E56PHY_CTRL_FSM_RX_STAT_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ if ((rdata & 0x3f) == 0x21)
+ break;
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ return -1;
+ }
+ }
+
+ /* 15. Since RX power-up fsm is stopped in RX_SAMP_CAL_ST */
+ rdata = 0;
+ addr = E56PHY_INTR_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ wr32_ephy(hw, addr, 0);
+
+ /* 16. Program ALIAS::RXS::RANGE_SEL = RANGE_FINAL */
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS_ANA_OVRDVAL_5_ANA_BBCDR_OSC_RANGE_SEL_I,
+ RANGE_FINAL);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_RXS0_OVRDEN_0_OVRD_EN_RXS0_RX0_SAMP_CAL_DONE_O,
+ 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0;
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_0_RX_EN_CFG, 0x1);
+ addr = E56PHY_PMD_CFG_0_ADDR;
+ wr32_ephy(hw, addr, rdata);
+
+ return status;
+}
+
+static int txgbe_e56_rxs_post_cdr_lock_temp_track_seq(struct txgbe_hw *hw,
+ u32 speed)
+{
+ int status = 0;
+ u32 rdata;
+ int SECOND_CODE;
+ int COARSE_CODE;
+ int FINE_CODE;
+ int ULTRAFINE_CODE;
+
+ int CMVAR_SEC_LOW_TH ;
+ int CMVAR_UFINE_MAX = 0;
+ int CMVAR_FINE_MAX ;
+ int CMVAR_UFINE_UMAX_WRAP = 0;
+ int CMVAR_COARSE_MAX ;
+ int CMVAR_UFINE_FMAX_WRAP = 0;
+ int CMVAR_FINE_FMAX_WRAP = 0;
+ int CMVAR_SEC_HIGH_TH ;
+ int CMVAR_UFINE_MIN ;
+ int CMVAR_FINE_MIN ;
+ int CMVAR_UFINE_UMIN_WRAP ;
+ int CMVAR_COARSE_MIN ;
+ int CMVAR_UFINE_FMIN_WRAP ;
+ int CMVAR_FINE_FMIN_WRAP ;
+
+ if (speed == 10) {
+ CMVAR_SEC_LOW_TH = S10G_CMVAR_SEC_LOW_TH;
+ CMVAR_UFINE_MAX = S10G_CMVAR_UFINE_MAX;
+ CMVAR_FINE_MAX = S10G_CMVAR_FINE_MAX;
+ CMVAR_UFINE_UMAX_WRAP = S10G_CMVAR_UFINE_UMAX_WRAP;
+ CMVAR_COARSE_MAX = S10G_CMVAR_COARSE_MAX;
+ CMVAR_UFINE_FMAX_WRAP = S10G_CMVAR_UFINE_FMAX_WRAP;
+ CMVAR_FINE_FMAX_WRAP = S10G_CMVAR_FINE_FMAX_WRAP;
+ CMVAR_SEC_HIGH_TH = S10G_CMVAR_SEC_HIGH_TH;
+ CMVAR_UFINE_MIN = S10G_CMVAR_UFINE_MIN;
+ CMVAR_FINE_MIN = S10G_CMVAR_FINE_MIN;
+ CMVAR_UFINE_UMIN_WRAP = S10G_CMVAR_UFINE_UMIN_WRAP;
+ CMVAR_COARSE_MIN = S10G_CMVAR_COARSE_MIN;
+ CMVAR_UFINE_FMIN_WRAP = S10G_CMVAR_UFINE_FMIN_WRAP;
+ CMVAR_FINE_FMIN_WRAP = S10G_CMVAR_FINE_FMIN_WRAP;
+ } else if (speed == 25) {
+ CMVAR_SEC_LOW_TH = S25G_CMVAR_SEC_LOW_TH;
+ CMVAR_UFINE_MAX = S25G_CMVAR_UFINE_MAX;
+ CMVAR_FINE_MAX = S25G_CMVAR_FINE_MAX;
+ CMVAR_UFINE_UMAX_WRAP = S25G_CMVAR_UFINE_UMAX_WRAP;
+ CMVAR_COARSE_MAX = S25G_CMVAR_COARSE_MAX;
+ CMVAR_UFINE_FMAX_WRAP = S25G_CMVAR_UFINE_FMAX_WRAP;
+ CMVAR_FINE_FMAX_WRAP = S25G_CMVAR_FINE_FMAX_WRAP;
+ CMVAR_SEC_HIGH_TH = S25G_CMVAR_SEC_HIGH_TH;
+ CMVAR_UFINE_MIN = S25G_CMVAR_UFINE_MIN;
+ CMVAR_FINE_MIN = S25G_CMVAR_FINE_MIN;
+ CMVAR_UFINE_UMIN_WRAP = S25G_CMVAR_UFINE_UMIN_WRAP;
+ CMVAR_COARSE_MIN = S25G_CMVAR_COARSE_MIN;
+ CMVAR_UFINE_FMIN_WRAP = S25G_CMVAR_UFINE_FMIN_WRAP;
+ CMVAR_FINE_FMIN_WRAP = S25G_CMVAR_FINE_FMIN_WRAP;
+ }
+
+ status |= txgbe_e56_rx_rd_second_code(hw, &SECOND_CODE);
+
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ COARSE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i);
+ FINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i);
+ ULTRAFINE_CODE = EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i);
+
+ if (SECOND_CODE <= CMVAR_SEC_LOW_TH) {
+ if (ULTRAFINE_CODE < CMVAR_UFINE_MAX) {
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i,
+ ULTRAFINE_CODE + 1);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (FINE_CODE < CMVAR_FINE_MAX) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_UMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = FINE_CODE + 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (COARSE_CODE < CMVAR_COARSE_MAX) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_FMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = CMVAR_FINE_FMAX_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i) = COARSE_CODE + 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_coarse_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ }
+ } else if (SECOND_CODE >= CMVAR_SEC_HIGH_TH) {
+ if (ULTRAFINE_CODE > CMVAR_UFINE_MIN) {
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_ultrafine_i,
+ ULTRAFINE_CODE - 1);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (FINE_CODE > CMVAR_FINE_MIN) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_UMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = FINE_CODE - 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ } else if (COARSE_CODE > CMVAR_COARSE_MIN) {
+ EPHY_RREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5,
+ ana_bbcdr_ultrafine_i) = CMVAR_UFINE_FMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_fine_i) = CMVAR_FINE_FMIN_WRAP;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDVAL_5, ana_bbcdr_coarse_i) = COARSE_CODE - 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDVAL_5);
+ EPHY_RREG(E56G__RXS0_ANA_OVRDEN_1);
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_coarse_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_fine_i) = 1;
+ EPHY_XFLD(E56G__RXS0_ANA_OVRDEN_1, ovrd_en_ana_bbcdr_ultrafine_i) = 1;
+ EPHY_WREG(E56G__RXS0_ANA_OVRDEN_1);
+ }
+ }
+
+ return status;
+}
+
+static int txgbe_e56_ctle_bypass_seq(struct txgbe_hw *hw)
+{
+ int status = 0;
+ u32 rdata;
+
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_0, ana_ctle_bypass_i, 1);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_ctle_bypass_i, 1);
+
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDVAL_3, ana_ctle_cz_cstm_i, 0);
+ txgbe_e56_ephy_config(E56G__RXS0_ANA_OVRDEN_0, ovrd_en_ana_ctle_cz_cstm_i, 1);
+
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_en_i) = 0;
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDVAL_1);
+
+ EPHY_RREG(E56G__PMD_RXS0_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_en_i) = 1;
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_done_o) = 1;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDEN_1);
+
+ return status;
+}
+
+static int txgbe_e56_rxs_adc_adapt_seq(struct txgbe_hw *hw, u32 bypass_ctle)
+{
+ u32 rdata, timer, addr;
+ int status = 0, i;
+
+ rdata = 0;
+ timer = 0;
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_cdr_rdy_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(100);
+
+ if (timer++ > PHYINIT_TIMEOUT) {
+ return 1;
+ }
+ }
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_VGA_TRAIN_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_VGA_TRAIN_EN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_CTLE_TRAIN_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_CTLE_TRAIN_EN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDEN_1_OVRD_EN_RXS0_RX0_ADC_INTL_CAL_DONE_O
+ , 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ timer = 0;
+ while (((rdata >> E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_CAL_DONE_O_LSB) & 1)
+ != 1) {
+ rdata = rd32_ephy(hw, addr);
+ usec_delay(100);
+
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ }
+ }
+
+ for (i = 0; i < 16; i++) {
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_2,
+ ovrd_en_rxs0_rx0_adc_ofst_adapt_done_o, 0);
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1,
+ rxs0_rx0_adc_ofst_adapt_done_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(100);
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ }
+ }
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_OFST_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_2,
+ ovrd_en_rxs0_rx0_adc_ofst_adapt_done_o, 0);
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1,
+ rxs0_rx0_adc_gain_adapt_done_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(100);
+
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ }
+ }
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_GAIN_ADAPT_EN_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ }
+
+ addr = E56PHY_RXS0_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS0_OVRDVAL_1_RXS0_RX0_ADC_INTL_ADAPT_EN_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ msleep(10);
+
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_2,
+ ovrd_en_rxs0_rx0_adc_intl_adapt_en_i, 0);
+
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_vga_train_en_i) = 1;
+ if (bypass_ctle == 0)
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_en_i) = 1;
+
+ EPHY_WREG(E56G__PMD_RXS0_OVRDVAL_1);
+
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_1,
+ ovrd_en_rxs0_rx0_vga_train_done_o, 0);
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_vga_train_done_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(100);
+
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ }
+ }
+
+ if (bypass_ctle == 0) {
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_1,
+ ovrd_en_rxs0_rx0_ctle_train_done_o, 0);
+ rdata = 0;
+ timer = 0;
+ while (EPHY_XFLD(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_ctle_train_done_o) != 1) {
+ EPHY_RREG(E56G__PMD_RXS0_OVRDVAL_1);
+ usec_delay(100);
+
+ if (timer++ > PHYINIT_TIMEOUT) {
+ break;
+ }
+ }
+ }
+
+ EPHY_RREG(E56G__PMD_RXS0_OVRDEN_1);
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_vga_train_en_i) = 0;
+ if (bypass_ctle == 0)
+ EPHY_XFLD(E56G__PMD_RXS0_OVRDEN_1, ovrd_en_rxs0_rx0_ctle_train_en_i) = 0;
+ EPHY_WREG(E56G__PMD_RXS0_OVRDEN_1);
+
+ return status;
+}
+
+static int txgbe_e56_phy_rxs_calib_adapt_seq(struct txgbe_hw *hw,
+ u8 by_link_mode, u32 bypass_ctle)
+{
+ int status = 0;
+ u32 rdata;
+
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_adc_ofst_adapt_en_i,
+ 0);
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_2,
+ ovrd_en_rxs0_rx0_adc_ofst_adapt_en_i, 1);
+
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_adc_gain_adapt_en_i,
+ 0);
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_2,
+ ovrd_en_rxs0_rx0_adc_gain_adapt_en_i, 1);
+
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_adc_intl_cal_en_i, 0);
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_1,
+ ovrd_en_rxs0_rx0_adc_intl_cal_en_i, 1);
+
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_adc_intl_cal_done_o,
+ 1);
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_1,
+ ovrd_en_rxs0_rx0_adc_intl_cal_done_o, 1);
+
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDVAL_1, rxs0_rx0_adc_intl_adapt_en_i,
+ 0);
+ txgbe_e56_ephy_config(E56G__PMD_RXS0_OVRDEN_2,
+ ovrd_en_rxs0_rx0_adc_intl_adapt_en_i, 1);
+
+ if (bypass_ctle != 0)
+ status |= txgbe_e56_ctle_bypass_seq(hw);
+
+ status |= txgbe_e56_rxs_osc_init_for_temp_track_range(hw, by_link_mode);
+
+ /* Wait an fsm_rx_sts 25G */
+ status |= kr_read_poll(rd32_ephy, rdata, ((rdata & 0x3f) == 0x1b), 1000,
+ 500000, hw, E56PHY_CTRL_FSM_RX_STAT_0_ADDR);
+
+ return status;
+}
+
+static int txgbe_e56_cms_cfg_for_temp_track_range(struct txgbe_hw *hw,
+ u8 by_link_mode)
+{
+ UNREFERENCED_PARAMETER(by_link_mode);
+ int status = 0, T = 40;
+ u32 addr, rdata;
+
+ status = txgbe_e56_get_temp(hw, &T);
+ if (T < 40) {
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDVAL_2_ANA_LCPLL_HF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_LF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDVAL_7_ANA_LCPLL_LF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ } else if (T > 70) {
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDVAL_2_ANA_LCPLL_HF_LPF_SETCODE_CALIB_I, 0x3);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_LF_LPF_SETCODE_CALIB_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDVAL_7_ANA_LCPLL_LF_LPF_SETCODE_CALIB_I, 0x3);
+ wr32_ephy(hw, addr, rdata);
+ } else {
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_HF_TEST_IN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 24, 24, 0x1);
+ set_fields_e56(&rdata, 31, 29, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 1, 0, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_LF_TEST_IN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_9_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 24, 24, 0x1);
+ set_fields_e56(&rdata, 31, 29, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_10_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 1, 0, 0x0);
+ wr32_ephy(hw, addr, rdata);
+ }
+ return status;
+}
+
+static int txgbe_e56_tx_ffe_cfg(struct txgbe_hw *hw)
+{
+ /* Setting the TX EQ main/pre1/pre2/post value */
+ wr32_ephy(hw, 0x141c, S25G_TX_FFE_CFG_DAC_MAIN);
+ wr32_ephy(hw, 0x1420, S25G_TX_FFE_CFG_DAC_PRE1);
+ wr32_ephy(hw, 0x1424, S25G_TX_FFE_CFG_DAC_PRE2);
+ wr32_ephy(hw, 0x1428, S25G_TX_FFE_CFG_DAC_POST);
+
+ return 0;
+}
+
+static int txgbe_e56_bp_cfg_25g(struct txgbe_hw *hw)
+{
+ u32 addr, rdata;
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_PIN_OVRDVAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_PIN_OVRDVAL_0_INT_PLL0_TX_SIGNAL_TYPE_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_PIN_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_PIN_OVRDEN_0_OVRD_EN_PLL0_TX_SIGNAL_TYPE_I,
+ 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_ANA_OVRDVAL_2_ANA_LCPLL_HF_VCO_SWING_CTRL_I,
+ 0xf);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata,
+ E56PHY_CMS_ANA_OVRDEN_0_OVRD_EN_ANA_LCPLL_HF_VCO_SWING_CTRL_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDVAL_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 23, 0, 0x260000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CMS_ANA_OVRDEN_1_OVRD_EN_ANA_LCPLL_HF_TEST_IN_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_TXS_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_TXS_CFG_1_ADAPTATION_WAIT_CNT_X256, 0xf);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_WKUP_CNT_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTLDO_WKUP_CNT_X32, 0xff);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTDCC_WKUP_CNT_X32, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_PIN_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 27, 24, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_PIN_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_PIN_OVRDEN_0_OVRD_EN_TX0_EFUSE_BITS_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_ANA_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDVAL_1_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDEN_0_OVRD_EN_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ txgbe_e56_tx_ffe_cfg(hw);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_RXS_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_DSER_DATA_SEL, 0x0);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_TRAIN_CLK_GATE_BYPASS_EN, 0x1fff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_1_PREDIV1, 0x700);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_1_TARGET_CNT1, 0x2418);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_OSC_RANGE_SEL1, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_VCO_CODE_INIT, 0x7fb);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_OSC_CURRENT_BOOST_EN1, 0x0);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_4_BBCDR_CURRENT_BOOST1, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_SDM_WIDTH, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_POSTLOCK,
+ 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_POSTLOCK,
+ 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BBCDR_RDY_CNT, 0x3);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_PRELOCK, 0x7);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_POSTLOCK, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_INTL_CONFIG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_INTL_CONFIG_0_ADC_INTL2SLICE_DELAY1, 0x3333);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_INTL_CONFIG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_INTL_CONFIG_2_INTERLEAVER_HBW_DISABLE1, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_LTH, 0x56);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_UTH, 0x6a);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_LTH, 0x1f8);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_UTH, 0xf0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_LTH, 0x100);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_UTH, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_LTH, 0x4);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_UTH, 0x37);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_TXFFE_TRAIN_MOD_TYPE, 0x38);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56G__RXS0_FOM_18__ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56G__RXS0_FOM_18__DFE_COEFFL_HINT__MSB,
+ E56G__RXS0_FOM_18__DFE_COEFFL_HINT__LSB, 0x0);
+ set_fields_e56(&rdata, E56G__RXS0_FOM_18__DFE_COEFFH_HINT__MSB,
+ E56G__RXS0_FOM_18__DFE_COEFFH_HINT__LSB, 0x0);
+ set_fields_e56(&rdata, E56G__RXS0_FOM_18__DFE_COEFF_HINT_LOAD__MSB,
+ E56G__RXS0_FOM_18__DFE_COEFF_HINT_LOAD__LSB, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_0_VGA_TARGET, 0x34);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT123, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT123, 0xa);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT0, 0x9);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT123, 0x9);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_1_LFEQ_LUT, 0x1ffffea);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P1, 18);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P2, 0);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P3, 0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P1, 1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P2, 0);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P3, 0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_SLICE_DATA_AVG_CNT,
+ 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_DATA_AVG_CNT, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_FE_OFFSET_DAC_CLK_CNT_X8,
+ 0xc);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_1_SAMP_ADAPT_CFG, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_FFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_FFE_TRAINING_0_FFE_TAP_EN, 0xf9ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_IDLE_DETECT_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MAX, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MIN, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x6cc;
+ rdata = 0x8020000;
+ wr32_ephy(hw, addr, rdata);
+ addr = 0x94;
+ rdata = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_0_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 4, 0, 0x0);
+ set_fields_e56(&rdata, 14, 13, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_BBCDR_VCOFILT_BYP_I,
+ 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_TEST_BBCDR_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 2, 0, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_17_ANA_VGA2_BOOST_CSTM_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_ANABS_CONFIG_I, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_VGA2_BOOST_CSTM_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_EYE_SCAN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_EYE_SCAN_1_EYE_SCAN_REF_TIMER, 0x400);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_RINGO_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 21, 12, 0x366);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_3_CTRL_FSM_TIMEOUT_X64K, 0x80);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_ON_PERIOD_X64K, 0x18);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_PERIOD_X512K, 0x3e);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_5_USE_RECENT_MARKER_OFFSET, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_CONT_ON_ADC_GAIN_CAL_ERR, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_DO_RX_ADC_OFST_CAL, 0x3);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_RX_ERR_ACTION_EN, 0x40);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST0_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST1_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST2_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST3_WAIT_CNT_X4096, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST4_WAIT_CNT_X4096, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST5_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST6_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST7_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST8_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST9_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST10_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST11_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST12_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST13_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST14_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST15_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST4_EN, 0x4bf);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST5_EN, 0xc4bf);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_8_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_8_TRAIN_ST7_EN, 0x47ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_12_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_12_TRAIN_ST15_EN, 0x67ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_13_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST0_DONE_EN, 0x8001);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST1_DONE_EN, 0x8002);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_14_TRAIN_ST3_DONE_EN, 0x8008);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_15_TRAIN_ST4_DONE_EN, 0x8004);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_17_TRAIN_ST8_DONE_EN, 0x20c0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_18_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_18_TRAIN_ST10_DONE_EN, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_29_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_29_TRAIN_ST15_DC_EN, 0x3f6d);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_33_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN0_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN1_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_34_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN2_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN3_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_KRT_TFSM_CFG_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X1000K, 0x49);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X8000K, 0x37);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_HOLDOFF_TIMER_X256K, 0x2f);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_FETX_FFE_TRAIN_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_FETX_FFE_TRAIN_CFG_0_KRT_FETX_INIT_FFE_CFG_2,
+ 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ return 0;
+}
+
+static int txgbe_e56_bp_cfg_10g(struct txgbe_hw *hw)
+{
+ u32 addr, rdata;
+
+ rdata = 0x0000;
+ addr = E56G__CMS_ANA_OVRDVAL_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G__CMS_ANA_OVRDVAL_7 *)&rdata)->ana_lcpll_lf_vco_swing_ctrl_i = 0xf;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56G__CMS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G__CMS_ANA_OVRDEN_1 *)&rdata)->ovrd_en_ana_lcpll_lf_vco_swing_ctrl_i = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56G__CMS_ANA_OVRDVAL_9_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 23, 0, 0x260000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56G__RXS0_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G__CMS_ANA_OVRDEN_1 *)&rdata)->ovrd_en_ana_lcpll_lf_test_in_i = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_TXS_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_TXS_CFG_1_ADAPTATION_WAIT_CNT_X256, 0xf);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_WKUP_CNT_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTLDO_WKUP_CNT_X32, 0xff);
+ set_fields_e56(&rdata, E56PHY_TXS_WKUP_CNTDCC_WKUP_CNT_X32, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_PIN_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 19, 16, 0x6);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_PIN_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_PIN_OVRDEN_0_OVRD_EN_TX0_EFUSE_BITS_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_ANA_OVRDVAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDVAL_1_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_TXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_TXS_ANA_OVRDEN_0_OVRD_EN_ANA_TEST_DAC_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ txgbe_e56_tx_ffe_cfg(hw);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_RXS_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_DSER_DATA_SEL, 0x0);
+ set_fields_e56(&rdata, E56PHY_RXS_RXS_CFG_0_TRAIN_CLK_GATE_BYPASS_EN, 0x1fff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_OSC_CAL_N_CDR_0 *)&rdata)->prediv0 = 0xfa0;
+ ((E56G_RXS0_OSC_CAL_N_CDR_0 *)&rdata)->target_cnt0 = 0x203a;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->osc_range_sel0 = 0x2;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->vco_code_init = 0x7ff;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->osc_current_boost_en0 = 0x1;
+ ((E56G_RXS0_OSC_CAL_N_CDR_4 *)&rdata)->bbcdr_current_boost0 = 0x0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_SDM_WIDTH, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_PROP_STEP_POSTLOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_POSTLOCK,
+ 0xc);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BB_CDR_GAIN_CTRL_PRELOCK,
+ 0xf);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_5_BBCDR_RDY_CNT, 0x3);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OSC_CAL_N_CDR_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_PRELOCK, 0x7);
+ set_fields_e56(&rdata, E56PHY_RXS_OSC_CAL_N_CDR_6_PI_GAIN_CTRL_POSTLOCK, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_INTL_CONFIG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_INTL_CONFIG_0 *)&rdata)->adc_intl2slice_delay0 = 0x5555;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_INTL_CONFIG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ ((E56G_RXS0_INTL_CONFIG_2 *)&rdata)->interleaver_hbw_disable0 = 0x1;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_LTH, 0x56);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_0_ADC_DATA_PEAK_UTH, 0x6a);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_LTH, 0x1e8);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_1_C1_UTH, 0x78);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_LTH, 0x100);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_2_CM1_UTH, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_TXFFE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_LTH, 0x4);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_CM2_UTH, 0x37);
+ set_fields_e56(&rdata, E56PHY_RXS_TXFFE_TRAINING_3_TXFFE_TRAIN_MOD_TYPE, 0x38);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_0_VGA_TARGET, 0x34);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_VGA_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT0, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA1_CODE_INIT123, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_VGA_TRAINING_1_VGA2_CODE_INIT123, 0xa);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT0, 0x9);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_0_CTLE_CODE_INIT123, 0x9);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_1_LFEQ_LUT, 0x1ffffea);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P1, 0x18);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P2, 0);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_2_ISI_TH_FRAC_P3, 0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_CTLE_TRAINING_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P1, 1);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P2, 0);
+ set_fields_e56(&rdata, E56PHY_RXS_CTLE_TRAINING_3_TAP_WEIGHT_P3, 0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_SLICE_DATA_AVG_CNT,
+ 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_ADC_DATA_AVG_CNT, 0x3);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_0_FE_OFFSET_DAC_CLK_CNT_X8,
+ 0xc);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_OFFSET_N_GAIN_CAL_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_OFFSET_N_GAIN_CAL_1_SAMP_ADAPT_CFG, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_FFE_TRAINING_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_FFE_TRAINING_0_FFE_TAP_EN, 0xf9ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_IDLE_DETECT_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MAX, 0xa);
+ set_fields_e56(&rdata, E56PHY_RXS_IDLE_DETECT_1_IDLE_TH_ADC_PEAK_MIN, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ addr = 0x6cc;
+ rdata = 0x8020000;
+ wr32_ephy(hw, addr, rdata);
+ addr = 0x94;
+ rdata = 0;
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_0_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_0_OVRD_EN_ANA_EN_RTERM_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_6_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 4, 0, 0x6);
+ set_fields_e56(&rdata, 14, 13, 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_BBCDR_VCOFILT_BYP_I,
+ 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_1_OVRD_EN_ANA_TEST_BBCDR_I, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 2, 0, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDVAL_17_ANA_VGA2_BOOST_CSTM_I, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_ANABS_CONFIG_I, 0x1);
+ set_fields_e56(&rdata, E56PHY_RXS_ANA_OVRDEN_3_OVRD_EN_ANA_VGA2_BOOST_CSTM_I,
+ 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDVAL_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_ANA_OVRDEN_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 13, 13, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_EYE_SCAN_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_RXS_EYE_SCAN_1_EYE_SCAN_REF_TIMER, 0x400);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_RXS_RINGO_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 21, 12, 0x366);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_3_CTRL_FSM_TIMEOUT_X64K, 0x80);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_ON_PERIOD_X64K, 0x18);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_4_TRAIN_DC_PERIOD_X512K, 0x3e);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_PMD_CFG_5_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_PMD_CFG_5_USE_RECENT_MARKER_OFFSET, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_CONT_ON_ADC_GAIN_CAL_ERR, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_DO_RX_ADC_OFST_CAL, 0x3);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_0_RX_ERR_ACTION_EN, 0x40);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_1_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST0_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST1_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST2_WAIT_CNT_X4096, 0xff);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_1_TRAIN_ST3_WAIT_CNT_X4096, 0xff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_2_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST4_WAIT_CNT_X4096, 0x1);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST5_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST6_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_2_TRAIN_ST7_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_3_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST8_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST9_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST10_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_3_TRAIN_ST11_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_4_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST12_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST13_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST14_WAIT_CNT_X4096, 0x4);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_4_TRAIN_ST15_WAIT_CNT_X4096, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_7_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST4_EN, 0x4bf);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_7_TRAIN_ST5_EN, 0xc4bf);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_8_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_8_TRAIN_ST7_EN, 0x47ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_12_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_12_TRAIN_ST15_EN, 0x67ff);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_13_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST0_DONE_EN, 0x8001);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_13_TRAIN_ST1_DONE_EN, 0x8002);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_14_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_14_TRAIN_ST3_DONE_EN, 0x8008);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_15_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_15_TRAIN_ST4_DONE_EN, 0x8004);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_17_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_17_TRAIN_ST8_DONE_EN, 0x20c0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_18_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_18_TRAIN_ST10_DONE_EN, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_29_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_29_TRAIN_ST15_DC_EN, 0x3f6d);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_33_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN0_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_33_TRAIN1_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_CTRL_FSM_CFG_34_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN2_RATE_SEL, 0x8000);
+ set_fields_e56(&rdata, E56PHY_CTRL_FSM_CFG_34_TRAIN3_RATE_SEL, 0x8000);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_KRT_TFSM_CFG_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X1000K, 0x49);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_MAX_WAIT_TIMER_X8000K, 0x37);
+ set_fields_e56(&rdata, E56PHY_KRT_TFSM_CFGKRT_TFSM_HOLDOFF_TIMER_X256K, 0x2f);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = E56PHY_FETX_FFE_TRAIN_CFG_0_ADDR;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, E56PHY_FETX_FFE_TRAIN_CFG_0_KRT_FETX_INIT_FFE_CFG_2,
+ 0x2);
+ wr32_ephy(hw, addr, rdata);
+
+ return 0;
+}
+
+static int txgbe_set_phy_link_mode(struct txgbe_hw *hw,
+ u8 by_link_mode)
+{
+ int status = 0;
+ u32 addr, rdata;
+
+ rdata = 0x0000;
+ addr = 0x030000;
+ rdata = rd32_epcs(hw, addr);
+ /* 10G mode */
+ if (by_link_mode == 10)
+ set_fields_e56(&rdata, 5, 2, 0);
+ /* 25G mode */
+ else if (by_link_mode == 25)
+ set_fields_e56(&rdata, 5, 2, 5);
+ wr32_epcs(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0x030007;
+ rdata = rd32_epcs(hw, addr);
+ /* 10G mode */
+ if (by_link_mode == 10)
+ set_fields_e56(&rdata, 3, 0, 0);
+ /* 25G mode */
+ else if (by_link_mode == 25)
+ set_fields_e56(&rdata, 3, 0, 7);
+ wr32_epcs(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0x010007;
+ rdata = rd32_epcs(hw, addr);
+ /* 10G mode */
+ if (by_link_mode == 10)
+ set_fields_e56(&rdata, 6, 0, 0xb);
+ /* 25G mode */
+ else if (by_link_mode == 25)
+ set_fields_e56(&rdata, 6, 0, 0x39);
+ wr32_epcs(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0xcb0;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 29, 29, 0x1);
+ set_fields_e56(&rdata, 1, 1, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0xcc4;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 24, 24, 0x0);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0xca4;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 1, 1, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0xca8;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 30, 30, 0x1);
+ set_fields_e56(&rdata, 25, 25, 0x1);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0xc10;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 25, 24, 0x1);
+ set_fields_e56(&rdata, 17, 16, 0x3);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0xc18;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 12, 8, 0x4);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0xc48;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 25, 24, 0x1);
+ set_fields_e56(&rdata, 17, 16, 0x3);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0xc50;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 12, 8, 0x8);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0xc1c;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 18, 8, 0x294);
+ set_fields_e56(&rdata, 4, 0, 0x8);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0x142c;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 30, 28, 0x7);
+ set_fields_e56(&rdata, 26, 24, 0x5);
+ if (by_link_mode == 10)
+ set_fields_e56(&rdata, 18, 16, 0x5);
+ else if (by_link_mode == 25)
+ set_fields_e56(&rdata, 18, 16, 0x3);
+ set_fields_e56(&rdata, 14, 12, 0x5);
+ set_fields_e56(&rdata, 10, 8, 0x5);
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0x1430;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 26, 24, 0x5);
+ set_fields_e56(&rdata, 10, 8, 0x5);
+ if (by_link_mode == 10) {
+ set_fields_e56(&rdata, 18, 16, 0x5);
+ set_fields_e56(&rdata, 2, 0, 0x5);
+ } else if (by_link_mode == 25) {
+ set_fields_e56(&rdata, 18, 16, 0x3);
+ set_fields_e56(&rdata, 2, 0, 0x3);
+ }
+ wr32_ephy(hw, addr, rdata);
+
+ rdata = 0x0000;
+ addr = 0x1438;
+ rdata = rd32_ephy(hw, addr);
+ if (by_link_mode == 10)
+ set_fields_e56(&rdata, 4, 0, 0x2);
+ else if (by_link_mode == 25)
+ set_fields_e56(&rdata, 4, 0, 0x9);
+ wr32_ephy(hw, addr, rdata);
+
+ status = txgbe_e56_cms_cfg_for_temp_track_range(hw, by_link_mode);
+
+ if (by_link_mode == 10)
+ txgbe_e56_bp_cfg_10g(hw);
+ else
+ txgbe_e56_bp_cfg_25g(hw);
+
+ if (by_link_mode == 10) {
+ rdata = 0x0000;
+ addr = 0x1400;
+ rdata = rd32_ephy(hw, addr);
+ set_fields_e56(&rdata, 21, 20, 0x3); /* pll en */
+ set_fields_e56(&rdata, 19, 12, 0x1); /* tx/rx en */
+ set_fields_e56(&rdata, 8, 8, 0x0); /* pmd mode */
+ set_fields_e56(&rdata, 1, 1, 0x1); /* pmd en */
+ wr32_ephy(hw, addr, rdata);
+ }
+
+ return status;
+}
+
+int txgbe_e56_set_link_to_kr(struct txgbe_hw *hw)
+{
+ int status = 0;
+ u32 rdata;
+
+ /* pcs + phy rst */
+ rdata = rd32(hw, 0x1000c);
+ if (hw->bus.lan_id == 1)
+ rdata |= BIT(16);
+ else
+ rdata |= BIT(19);
+ wr32(hw, 0x1000c, rdata);
+ msleep(20);
+
+ /* enable pcs intr */
+ wr32_epcs(hw, VR_AN_INTR_MSK, 0xf);
+
+ /* clear interrupt */
+ wr32_epcs(hw, 0x070000, 0);
+ wr32_epcs(hw, 0x078002, 0x0000);
+ wr32_epcs(hw, 0x030000, 0x8000);
+ rdata = rd32_epcs(hw, 0x070000);
+ set_fields_e56(&rdata, 12, 12, 0x1);
+ wr32_epcs(hw, 0x070000, rdata);
+ wr32_epcs(hw, 0x070010, 0x0001);
+ /* 25KR */
+ wr32_epcs(hw, 0x070011, 0xC080);
+
+ /* BASE-R FEC */
+ wr32_epcs(hw, 0x070012, 0xc000);
+ wr32_epcs(hw, 0x070016, 0x0000);
+ wr32_epcs(hw, 0x070017, 0x0);
+ wr32_epcs(hw, 0x070018, 0x0);
+
+ /* config timer */
+ wr32_epcs(hw, 0x078004, 0x003c);
+ wr32_epcs(hw, 0x078005, CL74_KRTR_TRAINNING_TIMEOUT);
+ wr32_epcs(hw, 0x078006, 25);
+ wr32_epcs(hw, 0x078000, 0x0008);
+
+ rdata = rd32_epcs(hw, 0x038000);
+ wr32_epcs(hw, 0x038000, rdata | BIT(15));
+
+ status = kr_read_poll(rd32_epcs, rdata,
+ (((rdata >> 15) & 1) == 0), 100,
+ 200000, hw,
+ 0x038000);
+ if (status)
+ return status;
+
+ /* wait rx/tx/cm powerdn_st */
+ msleep(20);
+ /* set phy an status to 0 */
+ wr32_ephy(hw, 0x1640, 0x0000);
+ rdata = rd32_ephy(hw, 0x1434);
+ set_fields_e56(&rdata, 7, 4, 0xe);
+ wr32_ephy(hw, 0x1434, rdata);
+
+ status = txgbe_set_phy_link_mode(hw, 10);
+ if (status)
+ return status;
+
+ status = txgbe_e56_rxs_osc_init_for_temp_track_range(hw, 10);
+ if (status)
+ return status;
+
+ /* Wait an 10g fsm_rx_sts */
+ status = kr_read_poll(rd32_ephy, rdata,
+ ((rdata & 0x3f) == 0xb), 1000,
+ 200000, hw,
+ E56PHY_CTRL_FSM_RX_STAT_0_ADDR);
+
+ return status;
+}
+
+static int txgbe_e56_cl72_trainning(struct txgbe_hw *hw)
+{
+ u32 bylinkmode = hw->bp_link_mode;
+ int status = 0, pTempData = 0;
+ u8 bypassCtle = 0;
+ u32 rdata;
+
+ status = txgbe_set_phy_link_mode(hw, bylinkmode);
+
+ /* set phy an status to 1 */
+ rdata = rd32_ephy(hw, 0x1434);
+ set_fields_e56(&rdata, 7, 4, 0xf);
+ wr32_ephy(hw, 0x1434, rdata);
+
+ /* kr training */
+ rdata = rd32_ephy(hw, 0x1640);
+ set_fields_e56(&rdata, 7, 0, 0x3);
+ wr32_ephy(hw, 0x1640, rdata);
+
+ /* enable CMS and its internal PLL and tx enable */
+ rdata = rd32_ephy(hw, 0x1400);
+ set_fields_e56(&rdata, 21, 20, 0x3);//pll en
+ set_fields_e56(&rdata, 19, 12, 0x1);// tx/rx en
+ set_fields_e56(&rdata, 8, 8, 0x0);// pmd mode
+ set_fields_e56(&rdata, 1, 1, 0x1);// pmd en
+ wr32_ephy(hw, 0x1400, rdata);
+
+ status = txgbe_e56_phy_rxs_calib_adapt_seq(hw, bylinkmode, bypassCtle);
+
+ txgbe_e56_set_rxs_ufine_le_max(hw, bylinkmode);
+
+ status = txgbe_e56_get_temp(hw, &pTempData);
+ status = txgbe_e56_rxs_post_cdr_lock_temp_track_seq(hw, bylinkmode);
+
+ status = kr_read_poll(rd32_ephy, rdata, (rdata & BIT(1)), 100,
+ 200000, hw, 0x163c);
+
+ status = txgbe_e56_rxs_adc_adapt_seq(hw, bypassCtle);
+
+ /* Wait an RLU */
+ status = kr_read_poll(rd32_epcs, rdata, (rdata & BIT(2)),
+ 100, 500000, hw, 0x30001);
+
+ return status;
+}
+
+int handle_e56_bkp_an73_flow(struct txgbe_hw *hw)
+{
+ int status = 0;
+
+ status = txgbe_e56_cl72_trainning(hw);
+ return status;
+}
+
+void txgbe_e65_bp_down_event(struct txgbe_hw *hw)
+{
+ if (!(hw->devarg.auto_neg == 1))
+ return;
+}
diff --git a/drivers/net/txgbe/base/txgbe_e56_bp.h b/drivers/net/txgbe/base/txgbe_e56_bp.h
new file mode 100644
index 0000000000..f959b58ff7
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_e56_bp.h
@@ -0,0 +1,13 @@
+#ifndef _TXGBE_E56_BP_H_
+#define _TXGBE_E56_BP_H_
+
+#define TXGBE_10G_FEC_REQ BIT(15)
+#define TXGBE_10G_FEC_ABL BIT(14)
+#define TXGBE_25G_BASE_FEC_REQ BIT(13)
+#define TXGBE_25G_RS_FEC_REQ BIT(12)
+
+int txgbe_e56_set_link_to_kr(struct txgbe_hw *hw);
+void txgbe_e65_bp_down_event(struct txgbe_hw *hw);
+int handle_e56_bkp_an73_flow(struct txgbe_hw *hw);
+
+#endif
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 85dbbc5eff..4750b84802 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -11,6 +11,10 @@
#include "txgbe_eeprom.h"
#include "txgbe_mng.h"
#include "txgbe_hw.h"
+#include "txgbe_e56.h"
+#include "txgbe_e56_bp.h"
+#include "txgbe_aml.h"
+#include "txgbe_aml40.h"
#define TXGBE_RAPTOR_MAX_TX_QUEUES 128
#define TXGBE_RAPTOR_MAX_RX_QUEUES 128
@@ -2469,9 +2473,7 @@ s32 txgbe_init_shared_code(struct txgbe_hw *hw)
txgbe_init_ops_dummy(hw);
switch (hw->mac.type) {
case txgbe_mac_raptor:
- case txgbe_mac_aml:
- case txgbe_mac_aml40:
- status = txgbe_init_ops_pf(hw);
+ status = txgbe_init_ops_sp(hw);
break;
case txgbe_mac_raptor_vf:
status = txgbe_init_ops_vf(hw);
@@ -2781,7 +2783,7 @@ s32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr, u32 *data)
* Initialize the function pointers and assign the MAC type.
* Does not touch the hardware.
**/
-s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
+s32 txgbe_init_ops_sp(struct txgbe_hw *hw)
{
struct txgbe_bus_info *bus = &hw->bus;
struct txgbe_mac_info *mac = &hw->mac;
diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h
index 1ed2892f61..79355ee9a3 100644
--- a/drivers/net/txgbe/base/txgbe_hw.h
+++ b/drivers/net/txgbe/base/txgbe_hw.h
@@ -86,7 +86,7 @@ s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg,
u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
s32 txgbe_init_shared_code(struct txgbe_hw *hw);
s32 txgbe_set_mac_type(struct txgbe_hw *hw);
-s32 txgbe_init_ops_pf(struct txgbe_hw *hw);
+s32 txgbe_init_ops_sp(struct txgbe_hw *hw);
s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
u32 *speed, bool *autoneg);
u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw);
diff --git a/drivers/net/txgbe/base/txgbe_osdep.h b/drivers/net/txgbe/base/txgbe_osdep.h
index a1477653e2..d8c0e10552 100644
--- a/drivers/net/txgbe/base/txgbe_osdep.h
+++ b/drivers/net/txgbe/base/txgbe_osdep.h
@@ -164,6 +164,10 @@ static inline u64 REVERT_BIT_MASK64(u64 mask)
#define IOMEM
+#ifndef BIT
+#define BIT(nr) (1UL << (nr))
+#endif
+
#define prefetch(x) rte_prefetch0(x)
#define ARRAY_SIZE(x) ((int32_t)RTE_DIM(x))
diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h
index 4dfe18930c..cf9142dc0c 100644
--- a/drivers/net/txgbe/base/txgbe_phy.h
+++ b/drivers/net/txgbe/base/txgbe_phy.h
@@ -105,6 +105,8 @@
#define VR_AN_INTR_CMPLT MS16(0, 0x1)
#define VR_AN_INTR_LINK MS16(1, 0x1)
#define VR_AN_INTR_PG_RCV MS16(2, 0x1)
+#define TXGBE_E56_AN_TXDIS MS16(3, 0x1)
+#define TXGBE_E56_AN_PG_RCV MS16(4, 0x1)
#define VR_AN_KR_MODE_CL 0x078003
#define VR_AN_KR_MODE_CL_PDET MS16(0, 0x1)
#define VR_XS_OR_PCS_MMD_DIGI_CTL1 0x038000
@@ -405,6 +407,21 @@
#define TXGBE_BP_M_NAUTO 0
#define TXGBE_BP_M_AUTO 1
+#define kr_read_poll(op, val, cond, sleep_us, \
+ times, args...) \
+({ \
+ unsigned long __sleep_us = (sleep_us); \
+ u32 __times = (times); \
+ u32 i; \
+ for (i = 0; i < __times; i++) { \
+ (val) = op(args); \
+ if (cond) \
+ break; \
+ usleep(__sleep_us);\
+ } \
+ (cond) ? 0 : -1; \
+})
+
#ifndef CL72_KRTR_PRBS_MODE_EN
#define CL72_KRTR_PRBS_MODE_EN 0xFFFF /* open kr prbs check */
#endif
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index a27860ac84..ac21c14d37 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -156,6 +156,12 @@
#define TXGBE_LOCKPF 0x010008
#define TXGBE_RST 0x01000C
#define TXGBE_RST_SW MS(0, 0x1)
+#define TXGBE_RST_FW MS(3, 0x1)
+#define TXGBE_RST_DMA MS(4, 0x1)
+#define TXGBE_RST_EPHY_LAN_1 MS(16, 0x1)
+#define TXGBE_RST_EPHY_LAN_0 MS(19, 0x1)
+#define TXGBE_RST_MAC_LAN_1 MS(17, 0x1)
+#define TXGBE_RST_MAC_LAN_0 MS(20, 0x1)
#define TXGBE_RST_LAN(i) MS(((i) + 1), 0x1)
#define TXGBE_RST_FW MS(3, 0x1)
#define TXGBE_RST_ETH(i) MS(((i) + 29), 0x1)
@@ -1570,6 +1576,13 @@ enum txgbe_5tuple_protocol {
#define TXGBE_PORTSTAT_BW_100M MS(3, 0x1)
#define TXGBE_PORTSTAT_ID(r) RS(r, 8, 0x1)
+/* amlite: diff from sapphire */
+#define TXGBE_CFG_PORT_ST_AML_LINK_MASK MS(1, 0xF)
+#define TXGBE_CFG_PORT_ST_AML_LINK_10G MS(4, 0x1)
+#define TXGBE_CFG_PORT_ST_AML_LINK_25G MS(3, 0x1)
+#define TXGBE_CFG_PORT_ST_AML_LINK_40G MS(2, 0x1)
+#define TXGBE_CFG_PORT_ST_AML_LINK_50G MS(1, 0x1)
+
#define TXGBE_VXLAN 0x014410
#define TXGBE_VXLAN_GPE 0x014414
#define TXGBE_GENEVE 0x014418
@@ -1594,7 +1607,10 @@ enum txgbe_5tuple_protocol {
#define TXGBE_GPIOINTSTAT 0x014840
#define TXGBE_GPIORAWINTSTAT 0x014844
#define TXGBE_GPIOEOI 0x01484C
-
+#define TXGBE_GPIOEXT 0x014850
+#define TXGBE_SFP1_MOD_PRST_LS 0x00000010U /* GPIO_EXT SFP ABSENT*/
+#define TXGBE_SFP1_MOD_ABS_LS 0x00000004U /* GPIO_EXT SFP ABSENT*/
+#define TXGBE_SFP1_RX_LOS_LS 0x00000008U /* GPIO_EXT RX LOSS */
#define TXGBE_ARBPOOLIDX 0x01820C
#define TXGBE_ARBTXRATE 0x018404
@@ -1689,6 +1705,9 @@ enum txgbe_5tuple_protocol {
#define TXGBE_MACTXCFG_SPEED_10G LS(0, 29, 0x3)
#define TXGBE_MACTXCFG_SPEED_1G LS(3, 29, 0x3)
+#define TXGBE_EPHY_STAT 0x13404
+#define TXGBE_EPHY_STAT_PPL_LOCK 0x3
+
#define TXGBE_ISBADDRL 0x000160
#define TXGBE_ISBADDRH 0x000164
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 1a5e4326a7..8d6491e053 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -214,6 +214,18 @@ enum txgbe_sfp_type {
txgbe_sfp_type_1g_sx_core1,
txgbe_sfp_type_1g_lx_core0,
txgbe_sfp_type_1g_lx_core1,
+ txgbe_sfp_type_25g_sr_core0,
+ txgbe_sfp_type_25g_sr_core1,
+ txgbe_sfp_type_25g_lr_core0,
+ txgbe_sfp_type_25g_lr_core1,
+ txgbe_sfp_type_25g_da_cu_core0,
+ txgbe_sfp_type_25g_da_cu_core1,
+ txgbe_sfp_type_25g_fcpi4_lmt_core0,
+ txgbe_sfp_type_25g_fcpi4_lmt_core1,
+ txgbe_sfp_type_25g_5m_da_cu_core0,
+ txgbe_sfp_type_25g_5m_da_cu_core1,
+ txgbe_sfp_type_40g_core0,
+ txgbe_sfp_type_40g_core1,
txgbe_sfp_type_not_present = 0xFFFE,
txgbe_sfp_type_not_known = 0xFFFF
};
@@ -539,6 +551,7 @@ struct txgbe_mac_info {
s32 (*prot_autoc_read)(struct txgbe_hw *hw, bool *locked, u64 *value);
s32 (*prot_autoc_write)(struct txgbe_hw *hw, bool locked, u64 value);
s32 (*negotiate_api_version)(struct txgbe_hw *hw, int api);
+ void (*init_mac_link_ops)(struct txgbe_hw *hw);
/* Link */
void (*disable_tx_laser)(struct txgbe_hw *hw);
@@ -765,6 +778,12 @@ struct txgbe_devargs {
u16 sgmii;
};
+#define TXGBE_PHY_FEC_RS MS(0, 0x1)
+#define TXGBE_PHY_FEC_BASER MS(1, 0x1)
+#define TXGBE_PHY_FEC_OFF MS(2, 0x1)
+#define TXGBE_PHY_FEC_AUTO (TXGBE_PHY_FEC_OFF | TXGBE_PHY_FEC_BASER |\
+ TXGBE_PHY_FEC_RS)
+
struct txgbe_hw {
void IOMEM *hw_addr;
void *back;
@@ -821,6 +840,20 @@ struct txgbe_hw {
u64 tx_qp_bytes;
u64 rx_qp_mc_packets;
} qp_last[TXGBE_MAX_QP];
+
+ rte_spinlock_t phy_lock;
+ /*amlite: new SW-FW mbox */
+ u8 swfw_index;
+ rte_atomic32_t swfw_busy;
+ bool link_valid;
+ bool reconfig_rx;
+ /* workaround for temperature alarm */
+ bool overheat;
+ u32 fec_mode;
+ u32 cur_fec_link;
+ int temperature;
+ u32 tx_speed;
+ u32 bp_link_mode;
};
struct txgbe_backplane_ability {
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 00/15] Wangxun new NIC support
2025-04-18 9:41 [PATCH 0/2] *** Wangxun new NIC support *** Zaiyu Wang
2025-04-18 9:41 ` [PATCH 1/2] net/txgbe: add support for Wangxun new NIC Amber-Lite 25g/40g Zaiyu Wang
2025-04-18 9:41 ` [PATCH 2/2] net/txgbe: add basic code for Amber-Liter NIC configuration Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 01/15] net/txgbe: add basic information for Amber-Lite 25G/40G NICs Zaiyu Wang
` (14 more replies)
2 siblings, 15 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang
We have released a new NIC series: Amber-Lite, with two models
supporting 10G/25G and 40G rates. Due to minimal hardware
differences from existing 10G NICs, it remains supported within
the txgbe driver.
Zaiyu Wang (15):
net/txgbe: add basic information for Amber-Lite 25G/40G NICs
net/txgbe: add new SW-FW mailbox interface
net/txgbe: add identification support for new SFP/QSFP modules
net/txgbe: add basic link configuration for Amber-Lite NICs
net/txgbe: add support for PHY configuration via SW-FW mailbox
net/txgbe: add RX&TX support for Amber-Lite NICs
net/txgbe: add hardware reset change for Amber-Lite NICs
net/txgbe: add MAC reconfiguration to avoid packet loss
net/txgbe: add TX head Write-Back mode for Amber-Lite NICs
net/txgbe: add RX desc merge mode for Amber-Lite NICs
net/txgbe: add FEC support for Amber-Lite 25G NICs
net/txgbe: add GPIO configuration
net/txgbe: disable unstable features
net/txgbe: add other hardware-related changes
doc: update for txgbe
doc/guides/nics/txgbe.rst | 8 +-
drivers/net/txgbe/base/meson.build | 2 +
drivers/net/txgbe/base/txgbe_aml.c | 355 ++++++++++++++++++++
drivers/net/txgbe/base/txgbe_aml.h | 22 ++
drivers/net/txgbe/base/txgbe_aml40.c | 159 +++++++++
drivers/net/txgbe/base/txgbe_aml40.h | 20 ++
drivers/net/txgbe/base/txgbe_devids.h | 9 +
drivers/net/txgbe/base/txgbe_eeprom.c | 7 +-
drivers/net/txgbe/base/txgbe_eeprom.h | 2 +
drivers/net/txgbe/base/txgbe_hw.c | 355 +++++++++++++++++---
drivers/net/txgbe/base/txgbe_hw.h | 16 +-
drivers/net/txgbe/base/txgbe_mng.c | 252 +++++++++++----
drivers/net/txgbe/base/txgbe_mng.h | 34 +-
drivers/net/txgbe/base/txgbe_osdep.h | 2 +
drivers/net/txgbe/base/txgbe_phy.c | 127 +++++++-
drivers/net/txgbe/base/txgbe_phy.h | 24 ++
drivers/net/txgbe/base/txgbe_regs.h | 95 +++++-
drivers/net/txgbe/base/txgbe_type.h | 66 ++++
drivers/net/txgbe/txgbe_ethdev.c | 373 ++++++++++++++++++++--
drivers/net/txgbe/txgbe_rxtx.c | 201 +++++++++---
drivers/net/txgbe/txgbe_rxtx.h | 3 +
drivers/net/txgbe/txgbe_rxtx_vec_common.h | 27 +-
22 files changed, 1945 insertions(+), 214 deletions(-)
create mode 100644 drivers/net/txgbe/base/txgbe_aml.c
create mode 100644 drivers/net/txgbe/base/txgbe_aml.h
create mode 100644 drivers/net/txgbe/base/txgbe_aml40.c
create mode 100644 drivers/net/txgbe/base/txgbe_aml40.h
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 01/15] net/txgbe: add basic information for Amber-Lite 25G/40G NICs
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 02/15] net/txgbe: add new SW-FW mailbox interface Zaiyu Wang
` (13 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Add device IDs, speed and other basic information for Wangxun's
new Amber-Lite NICs: aml (10G/25G) and aml40 (40G).
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_devids.h | 9 +++++++
drivers/net/txgbe/base/txgbe_hw.c | 17 +++++++++++++
drivers/net/txgbe/base/txgbe_regs.h | 4 ++-
drivers/net/txgbe/base/txgbe_type.h | 3 +++
drivers/net/txgbe/txgbe_ethdev.c | 35 ++++++++++++++++++++-------
5 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_devids.h b/drivers/net/txgbe/base/txgbe_devids.h
index a3f26eabf6..b7133c7d54 100644
--- a/drivers/net/txgbe/base/txgbe_devids.h
+++ b/drivers/net/txgbe/base/txgbe_devids.h
@@ -19,6 +19,15 @@
#define TXGBE_DEV_ID_WX1820 0x2001
#define TXGBE_DEV_ID_SP1000_VF 0x1000
#define TXGBE_DEV_ID_WX1820_VF 0x2000
+#define TXGBE_DEV_ID_AML 0x5000
+#define TXGBE_DEV_ID_AML5025 0x5025
+#define TXGBE_DEV_ID_AML5125 0x5125
+#define TXGBE_DEV_ID_AML5040 0x5040
+#define TXGBE_DEV_ID_AML5140 0x5140
+
+#define TXGBE_DEV_ID_AML_VF 0x5001
+#define TXGBE_DEV_ID_AML5024_VF 0x5024
+#define TXGBE_DEV_ID_AML5124_VF 0x5124
/*
* Subsystem IDs
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index dd5d3ea1fe..85dbbc5eff 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -2469,6 +2469,8 @@ s32 txgbe_init_shared_code(struct txgbe_hw *hw)
txgbe_init_ops_dummy(hw);
switch (hw->mac.type) {
case txgbe_mac_raptor:
+ case txgbe_mac_aml:
+ case txgbe_mac_aml40:
status = txgbe_init_ops_pf(hw);
break;
case txgbe_mac_raptor_vf:
@@ -2506,11 +2508,26 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw)
case TXGBE_DEV_ID_WX1820:
hw->mac.type = txgbe_mac_raptor;
break;
+ case TXGBE_DEV_ID_AML:
+ case TXGBE_DEV_ID_AML5025:
+ case TXGBE_DEV_ID_AML5125:
+ hw->mac.type = txgbe_mac_aml;
+ break;
+ case TXGBE_DEV_ID_AML5040:
+ case TXGBE_DEV_ID_AML5140:
+ hw->mac.type = txgbe_mac_aml40;
+ break;
case TXGBE_DEV_ID_SP1000_VF:
case TXGBE_DEV_ID_WX1820_VF:
hw->phy.media_type = txgbe_media_type_virtual;
hw->mac.type = txgbe_mac_raptor_vf;
break;
+ case TXGBE_DEV_ID_AML_VF:
+ case TXGBE_DEV_ID_AML5024_VF:
+ case TXGBE_DEV_ID_AML5124_VF:
+ hw->phy.media_type = txgbe_media_type_virtual;
+ hw->mac.type = txgbe_mac_aml_vf;
+ break;
default:
err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
DEBUGOUT("Unsupported device id: %x", hw->device_id);
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index 7a9ba6976f..a27860ac84 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -97,7 +97,9 @@
#define TXGBE_LINK_SPEED_2_5GB_FULL 0x0400
#define TXGBE_LINK_SPEED_5GB_FULL 0x0800
#define TXGBE_LINK_SPEED_10GB_FULL 0x0080
-#define TXGBE_LINK_SPEED_40GB_FULL 0x0100
+#define TXGBE_LINK_SPEED_25GB_FULL 0x0100
+#define TXGBE_LINK_SPEED_40GB_FULL 0x0040
+#define TXGBE_LINK_SPEED_50GB_FULL 0x0200
#define TXGBE_AUTOC_AUTONEG MS64(63, 0x1)
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 4371876649..1a5e4326a7 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -148,7 +148,10 @@ enum txgbe_eeprom_type {
enum txgbe_mac_type {
txgbe_mac_unknown = 0,
txgbe_mac_raptor,
+ txgbe_mac_aml,
+ txgbe_mac_aml40,
txgbe_mac_raptor_vf,
+ txgbe_mac_aml_vf,
txgbe_num_macs
};
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index ea9faba2c0..2431057485 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -145,6 +145,11 @@ static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
static const struct rte_pci_id pci_id_txgbe_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5025) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5125) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5040) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_AML5140) },
{ .vendor_id = 0, /* sentinel */ },
};
@@ -1829,8 +1834,13 @@ txgbe_dev_start(struct rte_eth_dev *dev)
if (err)
goto error;
- allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G |
- RTE_ETH_LINK_SPEED_10G;
+ if (hw->mac.type == txgbe_mac_aml40)
+ allowed_speeds = RTE_ETH_LINK_SPEED_40G;
+ else if (hw->mac.type == txgbe_mac_aml)
+ allowed_speeds = RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G;
+ else
+ allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G |
+ RTE_ETH_LINK_SPEED_10G;
link_speeds = &dev->data->dev_conf.link_speeds;
if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
@@ -1840,17 +1850,24 @@ txgbe_dev_start(struct rte_eth_dev *dev)
speed = 0x0;
if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
- speed = (TXGBE_LINK_SPEED_100M_FULL |
- TXGBE_LINK_SPEED_1GB_FULL |
- TXGBE_LINK_SPEED_10GB_FULL);
+ if (hw->mac.type == txgbe_mac_aml40) {
+ speed = TXGBE_LINK_SPEED_40GB_FULL;
+ } else if (hw->mac.type == txgbe_mac_aml) {
+ speed = (TXGBE_LINK_SPEED_10GB_FULL |
+ TXGBE_LINK_SPEED_25GB_FULL);
+ } else {
+ speed = (TXGBE_LINK_SPEED_100M_FULL |
+ TXGBE_LINK_SPEED_1GB_FULL |
+ TXGBE_LINK_SPEED_10GB_FULL);
+ }
hw->autoneg = true;
} else {
+ if (*link_speeds & RTE_ETH_LINK_SPEED_40G)
+ speed |= TXGBE_LINK_SPEED_40GB_FULL;
+ if (*link_speeds & RTE_ETH_LINK_SPEED_25G)
+ speed |= TXGBE_LINK_SPEED_25GB_FULL;
if (*link_speeds & RTE_ETH_LINK_SPEED_10G)
speed |= TXGBE_LINK_SPEED_10GB_FULL;
- if (*link_speeds & RTE_ETH_LINK_SPEED_5G)
- speed |= TXGBE_LINK_SPEED_5GB_FULL;
- if (*link_speeds & RTE_ETH_LINK_SPEED_2_5G)
- speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
if (*link_speeds & RTE_ETH_LINK_SPEED_1G)
speed |= TXGBE_LINK_SPEED_1GB_FULL;
if (*link_speeds & RTE_ETH_LINK_SPEED_100M)
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 02/15] net/txgbe: add new SW-FW mailbox interface
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 01/15] net/txgbe: add basic information for Amber-Lite 25G/40G NICs Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 03/15] net/txgbe: add identification support for new SFP/QSFP modules Zaiyu Wang
` (12 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Amber-Lite NICs adopt new mailbox interface for software-firmware
interaion to enable enhanced functionality.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_eeprom.c | 7 +-
drivers/net/txgbe/base/txgbe_eeprom.h | 2 +
drivers/net/txgbe/base/txgbe_mng.c | 216 +++++++++++++++++++-------
drivers/net/txgbe/base/txgbe_mng.h | 17 +-
drivers/net/txgbe/base/txgbe_regs.h | 7 +
drivers/net/txgbe/base/txgbe_type.h | 4 +
6 files changed, 193 insertions(+), 60 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_eeprom.c b/drivers/net/txgbe/base/txgbe_eeprom.c
index aeeae06dfc..eb53b35a19 100644
--- a/drivers/net/txgbe/base/txgbe_eeprom.c
+++ b/drivers/net/txgbe/base/txgbe_eeprom.c
@@ -366,8 +366,13 @@ s32 txgbe_calc_eeprom_checksum(struct txgbe_hw *hw)
err = hw->rom.readw_buffer(hw, i, seg, buffer);
if (err)
return err;
- for (j = 0; j < seg; j++)
+ for (j = 0; j < seg; j++) {
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
+ if (((i + j) >= (TXGBE_SHOWROM_I2C_PTR / 2)) &&
+ ((i + j) < (TXGBE_SHOWROM_I2C_END / 2)))
+ buffer[j] = 0xffff;
checksum += buffer[j];
+ }
}
checksum = (u16)TXGBE_EEPROM_SUM - checksum + read_checksum;
diff --git a/drivers/net/txgbe/base/txgbe_eeprom.h b/drivers/net/txgbe/base/txgbe_eeprom.h
index c10ad45ec8..26cc53ab42 100644
--- a/drivers/net/txgbe/base/txgbe_eeprom.h
+++ b/drivers/net/txgbe/base/txgbe_eeprom.h
@@ -20,6 +20,8 @@
#define TXGBE_PBANUM0_PTR 0x05
#define TXGBE_PBANUM1_PTR 0x06
#define TXGBE_SW_REGION_PTR 0x1C
+#define TXGBE_SHOWROM_I2C_PTR 0xB00
+#define TXGBE_SHOWROM_I2C_END 0xF00
#define TXGBE_EE_CSUM_MAX 0x800
#define TXGBE_EEPROM_CHECKSUM 0x2F
diff --git a/drivers/net/txgbe/base/txgbe_mng.c b/drivers/net/txgbe/base/txgbe_mng.c
index 7dc8f21183..8327c5fa01 100644
--- a/drivers/net/txgbe/base/txgbe_mng.c
+++ b/drivers/net/txgbe/base/txgbe_mng.c
@@ -45,17 +45,6 @@ txgbe_hic_unlocked(struct txgbe_hw *hw, u32 *buffer, u32 length, u32 timeout)
u32 value, loop;
u16 i, dword_len;
- if (!length || length > TXGBE_PMMBX_BSIZE) {
- DEBUGOUT("Buffer length failure buffersize=%d.", length);
- return TXGBE_ERR_HOST_INTERFACE_COMMAND;
- }
-
- /* Calculate length in DWORDs. We must be DWORD aligned */
- if (length % sizeof(u32)) {
- DEBUGOUT("Buffer length failure, not aligned to dword");
- return TXGBE_ERR_INVALID_ARGUMENT;
- }
-
dword_len = length >> 2;
txgbe_flush(hw);
@@ -113,54 +102,148 @@ txgbe_host_interface_command(struct txgbe_hw *hw, u32 *buffer,
{
u32 hdr_size = sizeof(struct txgbe_hic_hdr);
struct txgbe_hic_hdr *resp = (struct txgbe_hic_hdr *)buffer;
+ struct txgbe_hic_hdr *recv_hdr;
u16 buf_len;
- s32 err;
- u32 bi;
+ s32 err = 0;
+ u32 bi, i;
u32 dword_len;
+ u8 send_cmd;
if (length == 0 || length > TXGBE_PMMBX_BSIZE) {
DEBUGOUT("Buffer length failure buffersize=%d.", length);
return TXGBE_ERR_HOST_INTERFACE_COMMAND;
}
- /* Take management host interface semaphore */
- err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWMBX);
- if (err)
- return err;
+ /* Calculate length in DWORDs. We must be DWORD aligned */
+ if (length % sizeof(u32)) {
+ DEBUGOUT("Buffer length failure, not aligned to dword");
+ return TXGBE_ERR_INVALID_ARGUMENT;
+ }
- err = txgbe_hic_unlocked(hw, buffer, length, timeout);
- if (err)
- goto rel_out;
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) {
+ /* try to get lock */
+ while (rte_atomic32_test_and_set(&hw->swfw_busy)) {
+ timeout--;
+ if (!timeout)
+ return TXGBE_ERR_TIMEOUT;
+ usec_delay(1000);
+ }
+
+ /* index to unique seq id for each mbox message */
+ resp->cksum_or_index.index = hw->swfw_index;
+ send_cmd = resp->cmd;
+
+ /* Calculate length in DWORDs */
+ dword_len = length >> 2;
+
+ /* write data to SW-FW mbox array */
+ for (i = 0; i < dword_len; i++) {
+ wr32a(hw, TXGBE_AML_MNG_MBOX_SW2FW,
+ i, rte_cpu_to_le_32(buffer[i]));
+ /* write flush */
+ rd32a(hw, TXGBE_AML_MNG_MBOX_SW2FW, i);
+ }
+
+ /* amlite: generate interrupt to notify FW */
+ wr32m(hw, TXGBE_AML_MNG_MBOX_CTL_SW2FW,
+ TXGBE_AML_MNG_MBOX_NOTIFY, 0);
+ wr32m(hw, TXGBE_AML_MNG_MBOX_CTL_SW2FW,
+ TXGBE_AML_MNG_MBOX_NOTIFY, TXGBE_AML_MNG_MBOX_NOTIFY);
+
+ /* Calculate length in DWORDs */
+ dword_len = hdr_size >> 2;
+
+ /* polling reply from FW */
+ timeout = 50;
+ do {
+ timeout--;
+ usec_delay(1000);
+
+ /* read hdr */
+ for (bi = 0; bi < dword_len; bi++)
+ buffer[bi] = rd32a(hw, TXGBE_AML_MNG_MBOX_FW2SW, bi);
+
+ /* check hdr */
+ recv_hdr = (struct txgbe_hic_hdr *)buffer;
+
+ if ((recv_hdr->cmd == send_cmd) &&
+ (recv_hdr->cksum_or_index.index == hw->swfw_index))
+ break;
+ } while (timeout);
+
+ if (!timeout) {
+ PMD_DRV_LOG(ERR, "Polling from FW messages timeout, cmd is 0x%x, index is %d",
+ send_cmd, hw->swfw_index);
+ err = TXGBE_ERR_TIMEOUT;
+ goto rel_out;
+ }
+
+ /* expect no reply from FW then return */
+ /* release lock if return */
+ if (!return_data)
+ goto rel_out;
+
+ /* If there is any thing in data position pull it in */
+ buf_len = recv_hdr->buf_len;
+ if (buf_len == 0)
+ goto rel_out;
+
+ if (length < buf_len + hdr_size) {
+ DEBUGOUT("Buffer not large enough for reply message.");
+ err = TXGBE_ERR_HOST_INTERFACE_COMMAND;
+ goto rel_out;
+ }
- if (!return_data)
- goto rel_out;
+ /* Calculate length in DWORDs, add 3 for odd lengths */
+ dword_len = (buf_len + 3) >> 2;
+ for (; bi <= dword_len; bi++)
+ buffer[bi] = rd32a(hw, TXGBE_AML_MNG_MBOX_FW2SW, bi);
+ } else {
+ /* Take management host interface semaphore */
+ err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWMBX);
+ if (err)
+ return err;
- /* Calculate length in DWORDs */
- dword_len = hdr_size >> 2;
+ err = txgbe_hic_unlocked(hw, buffer, length, timeout);
+ if (err)
+ goto rel_out;
- /* first pull in the header so we know the buffer length */
- for (bi = 0; bi < dword_len; bi++)
- buffer[bi] = rd32a(hw, TXGBE_MNGMBX, bi);
+ if (!return_data)
+ goto rel_out;
- buf_len = resp->buf_len;
- if (!buf_len)
- goto rel_out;
+ /* Calculate length in DWORDs */
+ dword_len = hdr_size >> 2;
- if (length < buf_len + hdr_size) {
- DEBUGOUT("Buffer not large enough for reply message.");
- err = TXGBE_ERR_HOST_INTERFACE_COMMAND;
- goto rel_out;
- }
+ /* first pull in the header so we know the buffer length */
+ for (bi = 0; bi < dword_len; bi++)
+ buffer[bi] = rd32a(hw, TXGBE_MNGMBX, bi);
+
+ buf_len = resp->buf_len;
+ if (!buf_len)
+ goto rel_out;
- /* Calculate length in DWORDs, add 3 for odd lengths */
- dword_len = (buf_len + 3) >> 2;
+ if (length < buf_len + hdr_size) {
+ DEBUGOUT("Buffer not large enough for reply message.");
+ err = TXGBE_ERR_HOST_INTERFACE_COMMAND;
+ goto rel_out;
+ }
- /* Pull in the rest of the buffer (bi is where we left off) */
- for (; bi <= dword_len; bi++)
- buffer[bi] = rd32a(hw, TXGBE_MNGMBX, bi);
+ /* Calculate length in DWORDs, add 3 for odd lengths */
+ dword_len = (buf_len + 3) >> 2;
+ /* Pull in the rest of the buffer (bi is where we left off) */
+ for (; bi <= dword_len; bi++)
+ buffer[bi] = rd32a(hw, TXGBE_MNGMBX, bi);
+ }
rel_out:
- hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWMBX);
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) {
+ /* index++, index replace txgbe_hic_hdr.checksum */
+ hw->swfw_index = resp->cksum_or_index.index == TXGBE_HIC_HDR_INDEX_MAX ?
+ 0 : resp->cksum_or_index.index + 1;
+ rte_atomic32_clear(&hw->swfw_busy);
+ } else {
+ hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWMBX);
+ }
return err;
}
@@ -179,6 +262,12 @@ s32 txgbe_hic_sr_read(struct txgbe_hw *hw, u32 addr, u8 *buf, int len)
struct txgbe_hic_read_shadow_ram command;
u32 value;
int err, i = 0, j = 0;
+ u32 mngmbx_addr;
+
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
+ mngmbx_addr = TXGBE_AML_MNG_MBOX_FW2SW;
+ else
+ mngmbx_addr = TXGBE_MNGMBX;
if (len > TXGBE_PMMBX_DATA_SIZE)
return TXGBE_ERR_HOST_INTERFACE_COMMAND;
@@ -187,22 +276,27 @@ s32 txgbe_hic_sr_read(struct txgbe_hw *hw, u32 addr, u8 *buf, int len)
command.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
command.hdr.req.buf_lenh = 0;
command.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
- command.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
command.address = cpu_to_be32(addr);
command.length = cpu_to_be16(len);
+ if (hw->mac.type == txgbe_mac_raptor)
+ command.hdr.req.cksum_or_index.checksum = FW_DEFAULT_CHECKSUM;
- err = txgbe_hic_unlocked(hw, (u32 *)&command,
- sizeof(command), TXGBE_HI_COMMAND_TIMEOUT);
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
+ err = txgbe_host_interface_command(hw, (u32 *)&command,
+ sizeof(command), TXGBE_HI_COMMAND_TIMEOUT, false);
+ else
+ err = txgbe_hic_unlocked(hw, (u32 *)&command,
+ sizeof(command), TXGBE_HI_COMMAND_TIMEOUT);
if (err)
return err;
while (i < (len >> 2)) {
- value = rd32a(hw, TXGBE_MNGMBX, FW_NVM_DATA_OFFSET + i);
+ value = rd32a(hw, mngmbx_addr, FW_NVM_DATA_OFFSET + i);
((u32 *)buf)[i] = value;
i++;
}
- value = rd32a(hw, TXGBE_MNGMBX, FW_NVM_DATA_OFFSET + i);
+ value = rd32a(hw, mngmbx_addr, FW_NVM_DATA_OFFSET + i);
for (i <<= 2; i < len; i++)
((u8 *)buf)[i] = ((u8 *)&value)[j++];
@@ -230,9 +324,10 @@ s32 txgbe_hic_sr_write(struct txgbe_hw *hw, u32 addr, u8 *buf, int len)
command.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
command.hdr.req.buf_lenh = 0;
command.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
- command.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
command.address = cpu_to_be32(addr);
command.length = cpu_to_be16(len);
+ if (hw->mac.type == txgbe_mac_raptor)
+ command.hdr.req.cksum_or_index.checksum = FW_DEFAULT_CHECKSUM;
while (i < (len >> 2)) {
value = ((u32 *)buf)[i];
@@ -259,7 +354,8 @@ s32 txgbe_close_notify(struct txgbe_hw *hw)
buffer.hdr.req.cmd = FW_DW_CLOSE_NOTIFY;
buffer.hdr.req.buf_lenh = 0;
buffer.hdr.req.buf_lenl = 0;
- buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
+ if (hw->mac.type == txgbe_mac_raptor)
+ buffer.hdr.req.cksum_or_index.checksum = FW_DEFAULT_CHECKSUM;
/* one word */
buffer.length = 0;
@@ -289,7 +385,8 @@ s32 txgbe_open_notify(struct txgbe_hw *hw)
buffer.hdr.req.cmd = FW_DW_OPEN_NOTIFY;
buffer.hdr.req.buf_lenh = 0;
buffer.hdr.req.buf_lenl = 0;
- buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
+ if (hw->mac.type == txgbe_mac_raptor)
+ buffer.hdr.req.cksum_or_index.checksum = FW_DEFAULT_CHECKSUM;
/* one word */
buffer.length = 0;
@@ -343,11 +440,14 @@ s32 txgbe_hic_set_drv_ver(struct txgbe_hw *hw, u8 maj, u8 min,
fw_cmd.ver_min = min;
fw_cmd.ver_build = build;
fw_cmd.ver_sub = sub;
- fw_cmd.hdr.checksum = 0;
fw_cmd.pad = 0;
fw_cmd.pad2 = 0;
- fw_cmd.hdr.checksum = txgbe_calculate_checksum((u8 *)&fw_cmd,
+ if (hw->mac.type == txgbe_mac_raptor) {
+ fw_cmd.hdr.cksum_or_index.checksum = 0;
+ fw_cmd.hdr.cksum_or_index.checksum = txgbe_calculate_checksum((u8 *)&fw_cmd,
(FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
+ }
+
for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
ret_val = txgbe_host_interface_command(hw, (u32 *)&fw_cmd,
@@ -390,9 +490,11 @@ txgbe_hic_reset(struct txgbe_hw *hw)
reset_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
reset_cmd.lan_id = hw->bus.lan_id;
reset_cmd.reset_type = (u16)hw->reset_type;
- reset_cmd.hdr.checksum = 0;
- reset_cmd.hdr.checksum = txgbe_calculate_checksum((u8 *)&reset_cmd,
- (FW_CEM_HDR_LEN + reset_cmd.hdr.buf_len));
+ if (hw->mac.type == txgbe_mac_raptor) {
+ reset_cmd.hdr.cksum_or_index.checksum = 0;
+ reset_cmd.hdr.cksum_or_index.checksum = txgbe_calculate_checksum((u8 *)&reset_cmd,
+ (FW_CEM_HDR_LEN + reset_cmd.hdr.buf_len));
+ }
for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
err = txgbe_host_interface_command(hw, (u32 *)&reset_cmd,
@@ -449,7 +551,8 @@ s32 txgbe_hic_get_lldp(struct txgbe_hw *hw)
buffer.hdr.cmd = FW_LLDP_GET_CMD;
buffer.hdr.buf_len = 0x1;
buffer.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
- buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
+ if (hw->mac.type == txgbe_mac_raptor)
+ buffer.hdr.cksum_or_index.checksum = FW_DEFAULT_CHECKSUM;
buffer.func = hw->bus.lan_id;
err = txgbe_host_interface_command(hw, (u32 *)&buffer, sizeof(buffer),
@@ -480,7 +583,8 @@ s32 txgbe_hic_set_lldp(struct txgbe_hw *hw, bool on)
buffer.hdr.cmd = FW_LLDP_SET_CMD_OFF;
buffer.hdr.buf_len = 0x1;
buffer.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
- buffer.hdr.checksum = FW_DEFAULT_CHECKSUM;
+ if (hw->mac.type == txgbe_mac_raptor)
+ buffer.hdr.cksum_or_index.checksum = FW_DEFAULT_CHECKSUM;
buffer.func = hw->bus.lan_id;
return txgbe_host_interface_command(hw, (u32 *)&buffer, sizeof(buffer),
diff --git a/drivers/net/txgbe/base/txgbe_mng.h b/drivers/net/txgbe/base/txgbe_mng.h
index 16775862d6..5300970912 100644
--- a/drivers/net/txgbe/base/txgbe_mng.h
+++ b/drivers/net/txgbe/base/txgbe_mng.h
@@ -60,6 +60,8 @@
#define TXGBE_CHECKSUM_CAP_ST_PASS 0x80658383
#define TXGBE_CHECKSUM_CAP_ST_FAIL 0x70657376
+#define TXGBE_HIC_HDR_INDEX_MAX 255
+
/* Host Interface Command Structures */
struct txgbe_hic_hdr {
u8 cmd;
@@ -68,21 +70,30 @@ struct txgbe_hic_hdr {
u8 cmd_resv;
u8 ret_status;
} cmd_or_resp;
- u8 checksum;
+ union {
+ u8 checksum;
+ u8 index;
+ } cksum_or_index;
};
struct txgbe_hic_hdr2_req {
u8 cmd;
u8 buf_lenh;
u8 buf_lenl;
- u8 checksum;
+ union {
+ u8 checksum;
+ u8 index;
+ } cksum_or_index;
};
struct txgbe_hic_hdr2_rsp {
u8 cmd;
u8 buf_lenl;
u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
- u8 checksum;
+ union {
+ u8 checksum;
+ u8 index;
+ } cksum_or_index;
};
union txgbe_hic_hdr2 {
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index a27860ac84..a608206f28 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -263,6 +263,13 @@
#define TXGBE_MNGMBXCTL_FWACK MS(3, 0x1)
#define TXGBE_MNGMBX 0x01E100
+/* amlite: swfw mailbox changes */
+#define TXGBE_AML_MNG_MBOX_CTL_SW2FW 0x01E0A0
+#define TXGBE_AML_MNG_MBOX_SW2FW 0x01E200
+#define TXGBE_AML_MNG_MBOX_CTL_FW2SW 0x01E0A4
+#define TXGBE_AML_MNG_MBOX_FW2SW 0x01E300
+#define TXGBE_AML_MNG_MBOX_NOTIFY MS(31, 0x1)
+
/******************************************************************************
* Port Registers
******************************************************************************/
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 1a5e4326a7..ab7e45a0bf 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -821,6 +821,10 @@ struct txgbe_hw {
u64 tx_qp_bytes;
u64 rx_qp_mc_packets;
} qp_last[TXGBE_MAX_QP];
+
+ /*amlite: new SW-FW mbox */
+ u8 swfw_index;
+ rte_atomic32_t swfw_busy;
};
struct txgbe_backplane_ability {
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 03/15] net/txgbe: add identification support for new SFP/QSFP modules
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 01/15] net/txgbe: add basic information for Amber-Lite 25G/40G NICs Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 02/15] net/txgbe: add new SW-FW mailbox interface Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 04/15] net/txgbe: add basic link configuration for Amber-Lite NICs Zaiyu Wang
` (11 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Add identification support for new SFP/QSFP module types (e.g., 25G
SR/CR) in the Amber-Lite NIC configuration flow.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_phy.c | 92 ++++++++++++++++++++++++-----
drivers/net/txgbe/base/txgbe_phy.h | 23 ++++++++
drivers/net/txgbe/base/txgbe_regs.h | 5 +-
drivers/net/txgbe/base/txgbe_type.h | 12 ++++
4 files changed, 117 insertions(+), 15 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index ce6882e262..81e9aee295 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -774,10 +774,21 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
u8 identifier = 0;
u8 comp_codes_1g = 0;
u8 comp_codes_10g = 0;
+ u8 comp_codes_25g = 0;
+ u8 comp_copper_len = 0;
u8 oui_bytes[3] = {0, 0, 0};
u8 cable_tech = 0;
u8 cable_spec = 0;
u16 enforce_sfp = 0;
+ u32 value;
+
+ if (hw->mac.type == txgbe_mac_aml) {
+ value = rd32(hw, TXGBE_GPIOEXT);
+ if (value & TXGBE_SFP1_MOD_ABS_LS) {
+ hw->phy.sfp_type = txgbe_sfp_type_not_present;
+ return TXGBE_ERR_SFP_NOT_PRESENT;
+ }
+ }
if (hw->phy.media_type != txgbe_media_type_fiber) {
hw->phy.sfp_type = txgbe_sfp_type_not_present;
@@ -811,6 +822,16 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
if (err != 0)
goto ERR_I2C;
+ err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_25GBE_COMP_CODES,
+ &comp_codes_25g);
+ if (err != 0)
+ goto ERR_I2C;
+
+ err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_COPPER_LENGTH,
+ &comp_copper_len);
+ if (err != 0)
+ goto ERR_I2C;
+
err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_TECHNOLOGY,
&cable_tech);
if (err != 0)
@@ -832,12 +853,7 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
* 11 SFP_1g_sx_CORE0 - chip-specific
* 12 SFP_1g_sx_CORE1 - chip-specific
*/
- if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) {
- if (hw->bus.lan_id == 0)
- hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
- else
- hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
- } else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) {
+ if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) {
err = hw->phy.read_i2c_eeprom(hw,
TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec);
if (err != 0)
@@ -849,6 +865,17 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
} else {
hw->phy.sfp_type = txgbe_sfp_type_unknown;
}
+ } else if (comp_codes_25g == TXGBE_SFF_25GBASESR_CAPABLE ||
+ comp_codes_25g == TXGBE_SFF_25GBASEER_CAPABLE) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type = txgbe_sfp_type_25g_sr_core0;
+ else
+ hw->phy.sfp_type = txgbe_sfp_type_25g_sr_core1;
+ } else if (comp_codes_25g == TXGBE_SFF_25GBASELR_CAPABLE) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type = txgbe_sfp_type_25g_lr_core0;
+ else
+ hw->phy.sfp_type = txgbe_sfp_type_25g_lr_core1;
} else if (comp_codes_10g &
(TXGBE_SFF_10GBASESR_CAPABLE |
TXGBE_SFF_10GBASELR_CAPABLE)) {
@@ -876,11 +903,20 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
/* Determine if the SFP+ PHY is dual speed or not. */
hw->phy.multispeed_fiber = false;
- if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
- (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
- ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
- (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
- hw->phy.multispeed_fiber = true;
+ if (hw->mac.type == txgbe_mac_aml) {
+ if ((comp_codes_25g == TXGBE_SFF_25GBASESR_CAPABLE ||
+ comp_codes_25g == TXGBE_SFF_25GBASELR_CAPABLE ||
+ comp_codes_25g == TXGBE_SFF_25GBASEER_CAPABLE) &&
+ ((comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE) ||
+ (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
+ hw->phy.multispeed_fiber = true;
+ } else {
+ if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
+ (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
+ ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
+ (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
+ hw->phy.multispeed_fiber = true;
+ }
/* Determine PHY vendor */
if (hw->phy.type != txgbe_phy_nl) {
@@ -938,7 +974,7 @@ s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
}
/* Verify supported 1G SFP modules */
- if (comp_codes_10g == 0 &&
+ if (comp_codes_10g == 0 && comp_codes_25g == 0 &&
!(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
@@ -986,6 +1022,7 @@ s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
u8 cable_length = 0;
u8 device_tech = 0;
bool active_cable = false;
+ u32 value;
if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) {
hw->phy.sfp_type = txgbe_sfp_type_not_present;
@@ -993,6 +1030,16 @@ s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
goto out;
}
+ if (hw->mac.type == txgbe_mac_aml40) {
+ /* config GPIO before read i2c */
+ wr32(hw, TXGBE_GPIODATA, TXGBE_GPIOBIT_1);
+ value = rd32(hw, TXGBE_GPIOEXT);
+ if (value & TXGBE_SFP1_MOD_PRST_LS) {
+ hw->phy.sfp_type = txgbe_sfp_type_not_present;
+ return TXGBE_ERR_SFP_NOT_PRESENT;
+ }
+ }
+
err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
&identifier);
ERR_I2C:
@@ -1024,10 +1071,27 @@ s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
hw->phy.type = txgbe_phy_qsfp_unknown_passive;
+ if (hw->mac.type == txgbe_mac_aml40) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type = txgbe_qsfp_type_40g_cu_core0;
+ else
+ hw->phy.sfp_type = txgbe_qsfp_type_40g_cu_core1;
+ } else {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
+ else
+ hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
+ }
+ } else if (comp_codes_10g & TXGBE_SFF_40GBASE_SR4) {
+ if (hw->bus.lan_id == 0)
+ hw->phy.sfp_type = txgbe_qsfp_type_40g_sr_core0;
+ else
+ hw->phy.sfp_type = txgbe_qsfp_type_40g_sr_core1;
+ } else if (comp_codes_10g & TXGBE_SFF_40GBASE_LR4) {
if (hw->bus.lan_id == 0)
- hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
+ hw->phy.sfp_type = txgbe_qsfp_type_40g_lr_core0;
else
- hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
+ hw->phy.sfp_type = txgbe_qsfp_type_40g_lr_core1;
} else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
TXGBE_SFF_10GBASELR_CAPABLE)) {
if (hw->bus.lan_id == 0)
diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h
index 4dfe18930c..79b866ea57 100644
--- a/drivers/net/txgbe/base/txgbe_phy.h
+++ b/drivers/net/txgbe/base/txgbe_phy.h
@@ -249,6 +249,8 @@
#define TXGBE_SFF_VENDOR_OUI_BYTE2 0x27
#define TXGBE_SFF_1GBE_COMP_CODES 0x06
#define TXGBE_SFF_10GBE_COMP_CODES 0x03
+#define TXGBE_SFF_25GBE_COMP_CODES 0x24
+#define TXGBE_SFF_COPPER_LENGTH 0x12
#define TXGBE_SFF_CABLE_TECHNOLOGY 0x08
#define TXGBE_SFF_CABLE_DA_PASSIVE 0x4
#define TXGBE_SFF_CABLE_DA_ACTIVE 0x8
@@ -275,6 +277,23 @@
#define TXGBE_SFF_1GBASET_CAPABLE 0x8
#define TXGBE_SFF_10GBASESR_CAPABLE 0x10
#define TXGBE_SFF_10GBASELR_CAPABLE 0x20
+#define TXGBE_SFF_25GBASESR_CAPABLE 0x2
+#define TXGBE_SFF_25GBASELR_CAPABLE 0x3
+#define TXGBE_SFF_25GBASEER_CAPABLE 0x4
+#define TXGBE_SFF_25GBASECR_91FEC 0xB
+#define TXGBE_SFF_25GBASECR_74FEC 0xC
+#define TXGBE_SFF_25GBASECR_NOFEC 0xD
+#define TXGBE_SFF_40GBASE_SR_CAPABLE 0x10
+#define TXGBE_SFF_4x10GBASESR_CAP 0x11
+#define TXGBE_SFF_40GBASEPSM4_Parallel 0x12
+#define TXGBE_SFF_40GBASE_SWMD4_CAP 0x1f
+
+#define TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
+#define TXGBE_SFF_25GAUI_C2M_AOC_BER_5 0x1
+#define TXGBE_SFF_25GAUI_C2M_ACC_BER_5 0x8
+#define TXGBE_SFF_25GAUI_C2M_AOC_BER_12 0x18
+#define TXGBE_SFF_25GAUI_C2M_ACC_BER_12 0x19
+
#define TXGBE_SFF_SOFT_RS_SELECT_MASK 0x8
#define TXGBE_SFF_SOFT_RS_SELECT_10G 0x8
#define TXGBE_SFF_SOFT_RS_SELECT_1G 0x0
@@ -290,6 +309,10 @@
#define TXGBE_I2C_EEPROM_STATUS_FAIL 0x2
#define TXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
+#define TXGBE_SFF_40GBASE_CR4 0x8
+#define TXGBE_SFF_40GBASE_SR4 0x4
+#define TXGBE_SFF_40GBASE_LR4 0x2
+
/* EEPROM for SFF-8472 (dev_addr = 0xA2) */
#define TXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index a608206f28..03c517f055 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -1601,7 +1601,10 @@ enum txgbe_5tuple_protocol {
#define TXGBE_GPIOINTSTAT 0x014840
#define TXGBE_GPIORAWINTSTAT 0x014844
#define TXGBE_GPIOEOI 0x01484C
-
+#define TXGBE_GPIOEXT 0x014850
+#define TXGBE_SFP1_MOD_ABS_LS MS(2, 0x1) /* GPIO_EXT SFP ABSENT*/
+#define TXGBE_SFP1_RX_LOS_LS MS(3, 0x1) /* GPIO_EXT RX LOSS */
+#define TXGBE_SFP1_MOD_PRST_LS MS(4, 0x1) /* GPIO_EXT SFP ABSENT*/
#define TXGBE_ARBPOOLIDX 0x01820C
#define TXGBE_ARBTXRATE 0x018404
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index ab7e45a0bf..b6dce31473 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -214,6 +214,18 @@ enum txgbe_sfp_type {
txgbe_sfp_type_1g_sx_core1,
txgbe_sfp_type_1g_lx_core0,
txgbe_sfp_type_1g_lx_core1,
+ txgbe_sfp_type_25g_sr_core0,
+ txgbe_sfp_type_25g_sr_core1,
+ txgbe_sfp_type_25g_lr_core0,
+ txgbe_sfp_type_25g_lr_core1,
+ txgbe_sfp_type_25g_aoc_core0,
+ txgbe_sfp_type_25g_aoc_core1,
+ txgbe_qsfp_type_40g_cu_core0,
+ txgbe_qsfp_type_40g_cu_core1,
+ txgbe_qsfp_type_40g_sr_core0,
+ txgbe_qsfp_type_40g_sr_core1,
+ txgbe_qsfp_type_40g_lr_core0,
+ txgbe_qsfp_type_40g_lr_core1,
txgbe_sfp_type_not_present = 0xFFFE,
txgbe_sfp_type_not_known = 0xFFFF
};
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 04/15] net/txgbe: add basic link configuration for Amber-Lite NICs
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (2 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 03/15] net/txgbe: add identification support for new SFP/QSFP modules Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 05/15] net/txgbe: add support for PHY configuration via SW-FW mailbox Zaiyu Wang
` (10 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Due to Amber-Lite's significant differences from our 10G NICs, we split
link configuration components (setup_link, check_link, etc.) into new files.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/meson.build | 2 +
drivers/net/txgbe/base/txgbe_aml.c | 324 +++++++++++++++++++++++++++
drivers/net/txgbe/base/txgbe_aml.h | 21 ++
drivers/net/txgbe/base/txgbe_aml40.c | 125 +++++++++++
drivers/net/txgbe/base/txgbe_aml40.h | 20 ++
drivers/net/txgbe/base/txgbe_hw.c | 78 ++++++-
drivers/net/txgbe/base/txgbe_hw.h | 13 +-
drivers/net/txgbe/base/txgbe_regs.h | 9 +
drivers/net/txgbe/base/txgbe_type.h | 2 +
drivers/net/txgbe/txgbe_ethdev.c | 8 +
10 files changed, 585 insertions(+), 17 deletions(-)
create mode 100644 drivers/net/txgbe/base/txgbe_aml.c
create mode 100644 drivers/net/txgbe/base/txgbe_aml.h
create mode 100644 drivers/net/txgbe/base/txgbe_aml40.c
create mode 100644 drivers/net/txgbe/base/txgbe_aml40.h
diff --git a/drivers/net/txgbe/base/meson.build b/drivers/net/txgbe/base/meson.build
index 0bb0782c92..ac4a05005e 100644
--- a/drivers/net/txgbe/base/meson.build
+++ b/drivers/net/txgbe/base/meson.build
@@ -6,6 +6,8 @@ base_sources = files(
'txgbe_dcb.c',
'txgbe_eeprom.c',
'txgbe_hw.c',
+ 'txgbe_aml.c',
+ 'txgbe_aml40.c',
'txgbe_mbx.c',
'txgbe_mng.c',
'txgbe_phy.c',
diff --git a/drivers/net/txgbe/base/txgbe_aml.c b/drivers/net/txgbe/base/txgbe_aml.c
new file mode 100644
index 0000000000..1b5a3783a9
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_aml.c
@@ -0,0 +1,324 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
+ */
+
+#include "txgbe_type.h"
+#include "txgbe_mbx.h"
+#include "txgbe_phy.h"
+#include "txgbe_dcb.h"
+#include "txgbe_vf.h"
+#include "txgbe_eeprom.h"
+#include "txgbe_mng.h"
+#include "txgbe_hw.h"
+#include "txgbe_aml.h"
+
+void txgbe_init_ops_aml(struct txgbe_hw *hw)
+{
+ struct txgbe_mac_info *mac = &hw->mac;
+ struct txgbe_phy_info *phy = &hw->phy;
+
+ txgbe_init_ops_generic(hw);
+
+ /* PHY */
+ phy->get_media_type = txgbe_get_media_type_aml;
+
+ /* LINK */
+ mac->init_mac_link_ops = txgbe_init_mac_link_ops_aml;
+ mac->get_link_capabilities = txgbe_get_link_capabilities_aml;
+ mac->check_link = txgbe_check_mac_link_aml;
+}
+
+s32 txgbe_check_mac_link_aml(struct txgbe_hw *hw, u32 *speed,
+ bool *link_up, bool link_up_wait_to_complete)
+{
+ u32 links_reg, links_orig;
+ u32 i;
+
+ /* clear the old state */
+ links_orig = rd32(hw, TXGBE_PORTSTAT);
+
+ links_reg = rd32(hw, TXGBE_PORTSTAT);
+
+ if (links_orig != links_reg) {
+ DEBUGOUT("LINKS changed from %08X to %08X",
+ links_orig, links_reg);
+ }
+
+ if (link_up_wait_to_complete) {
+ for (i = 0; i < hw->mac.max_link_up_time; i++) {
+ if (!(links_reg & TXGBE_PORTSTAT_UP)) {
+ *link_up = false;
+ } else {
+ *link_up = true;
+ break;
+ }
+ msec_delay(100);
+ links_reg = rd32(hw, TXGBE_PORTSTAT);
+ }
+ } else {
+ if (links_reg & TXGBE_PORTSTAT_UP)
+ *link_up = true;
+ else
+ *link_up = false;
+ }
+
+ if (link_up) {
+ switch (links_reg & TXGBE_CFG_PORT_ST_AML_LINK_MASK) {
+ case TXGBE_CFG_PORT_ST_AML_LINK_25G:
+ *speed = TXGBE_LINK_SPEED_25GB_FULL;
+ break;
+ case TXGBE_CFG_PORT_ST_AML_LINK_10G:
+ *speed = TXGBE_LINK_SPEED_10GB_FULL;
+ break;
+ default:
+ *speed = TXGBE_LINK_SPEED_UNKNOWN;
+ }
+ } else
+ *speed = TXGBE_LINK_SPEED_UNKNOWN;
+
+ return 0;
+}
+
+
+s32 txgbe_get_link_capabilities_aml(struct txgbe_hw *hw,
+ u32 *speed,
+ bool *autoneg)
+{
+ if (hw->phy.multispeed_fiber) {
+ *speed = TXGBE_LINK_SPEED_10GB_FULL |
+ TXGBE_LINK_SPEED_25GB_FULL;
+ *autoneg = true;
+ } else if (hw->phy.sfp_type == txgbe_sfp_type_25g_sr_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_sr_core1 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_lr_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_lr_core1) {
+ *speed = TXGBE_LINK_SPEED_25GB_FULL;
+ *autoneg = false;
+ } else if (hw->phy.sfp_type == txgbe_sfp_type_25g_aoc_core0 ||
+ hw->phy.sfp_type == txgbe_sfp_type_25g_aoc_core1) {
+ *speed = TXGBE_LINK_SPEED_25GB_FULL;
+ *autoneg = false;
+ } else {
+ /* SFP */
+ if (hw->phy.sfp_type == txgbe_sfp_type_not_present)
+ *speed = TXGBE_LINK_SPEED_25GB_FULL;
+ else
+ *speed = TXGBE_LINK_SPEED_10GB_FULL;
+ *autoneg = true;
+ }
+
+ return 0;
+}
+
+u32 txgbe_get_media_type_aml(struct txgbe_hw *hw)
+{
+ u8 device_type = hw->subsystem_device_id & 0xF0;
+ enum txgbe_media_type media_type;
+
+ switch (device_type) {
+ case TXGBE_DEV_ID_KR_KX_KX4:
+ media_type = txgbe_media_type_backplane;
+ break;
+ case TXGBE_DEV_ID_SFP:
+ media_type = txgbe_media_type_fiber;
+ break;
+ default:
+ media_type = txgbe_media_type_unknown;
+ break;
+ }
+
+ return media_type;
+}
+
+s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw,
+ u32 speed,
+ bool autoneg_wait_to_complete)
+{
+ bool autoneg = false;
+ s32 status = 0;
+ s32 ret_status = 0;
+ u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
+ bool link_up = false;
+ int i;
+ u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
+ u32 value = 0;
+
+ UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
+
+ if (hw->phy.sfp_type == txgbe_sfp_type_not_present) {
+ DEBUGOUT("SFP not detected, skip setup mac link");
+ return 0;
+ }
+
+ /* Check to see if speed passed in is supported. */
+ status = hw->mac.get_link_capabilities(hw,
+ &link_capabilities, &autoneg);
+ if (status)
+ return status;
+
+ speed &= link_capabilities;
+ if (speed == TXGBE_LINK_SPEED_UNKNOWN)
+ return TXGBE_ERR_LINK_SETUP;
+
+ value = rd32(hw, TXGBE_GPIOEXT);
+ if (value & (TXGBE_SFP1_MOD_ABS_LS | TXGBE_SFP1_RX_LOS_LS))
+ return status;
+
+ for (i = 0; i < 4; i++) {
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+ if (link_up)
+ break;
+ msleep(250);
+ }
+
+ if (link_speed == speed && link_up &&
+ !(speed == TXGBE_LINK_SPEED_25GB_FULL))
+ return status;
+
+ rte_spinlock_lock(&hw->phy_lock);
+ ret_status = 0;
+ rte_spinlock_unlock(&hw->phy_lock);
+
+ if (ret_status == TXGBE_ERR_PHY_INIT_NOT_DONE)
+ return status;
+
+ for (i = 0; i < 4; i++) {
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+ if (link_up)
+ return status;
+ msleep(250);
+ }
+
+ return status;
+}
+
+/**
+ * txgbe_setup_mac_link_multispeed_fiber_aml - Set MAC link speed
+ * @hw: pointer to hardware structure
+ * @speed: new link speed
+ * @autoneg_wait_to_complete: true when waiting for completion is needed
+ *
+ * Set the link speed in the MAC and/or PHY register and restarts link.
+ **/
+static s32 txgbe_setup_mac_link_multispeed_fiber_aml(struct txgbe_hw *hw,
+ u32 speed,
+ bool autoneg_wait_to_complete)
+{
+ u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
+ u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
+ s32 status = 0;
+ u32 speedcnt = 0;
+ bool autoneg, link_up = false;
+
+ /* Mask off requested but non-supported speeds */
+ status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
+ if (status != 0)
+ return status;
+
+ speed &= link_speed;
+
+ /* Try each speed one by one, highest priority first. We do this in
+ * software because 10Gb fiber doesn't support speed autonegotiation.
+ */
+ if (speed & TXGBE_LINK_SPEED_25GB_FULL) {
+ speedcnt++;
+ highest_link_speed = TXGBE_LINK_SPEED_25GB_FULL;
+
+ /* If we already have link at this speed, just jump out */
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+
+ if ((link_speed == TXGBE_LINK_SPEED_25GB_FULL) && link_up)
+ goto out;
+
+ /* Allow module to change analog characteristics (1G->10G) */
+ msec_delay(40);
+
+ status = hw->mac.setup_mac_link(hw,
+ TXGBE_LINK_SPEED_25GB_FULL,
+ autoneg_wait_to_complete);
+ if (status != 0)
+ return status;
+
+ /*aml wait link in setup,no need to repeatly wait*/
+ /* If we have link, just jump out */
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+
+ if (link_up)
+ goto out;
+
+ }
+
+ if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
+ speedcnt++;
+ if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
+ highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
+
+ /* If we already have link at this speed, just jump out */
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+
+ if ((link_speed == TXGBE_LINK_SPEED_10GB_FULL) && link_up)
+ goto out;
+
+ /* Allow module to change analog characteristics (25G->10G) */
+ msec_delay(40);
+
+ status = hw->mac.setup_mac_link(hw, TXGBE_LINK_SPEED_10GB_FULL,
+ autoneg_wait_to_complete);
+ if (status != 0)
+ return status;
+
+ /*aml wait link in setup,no need to repeatly wait*/
+ /* If we have link, just jump out */
+ txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
+
+ if (link_up)
+ goto out;
+ }
+
+ /* We didn't get link. Configure back to the highest speed we tried,
+ * (if there was more than one). We call ourselves back with just the
+ * single highest speed that the user requested.
+ */
+ if (speedcnt > 1)
+ status = txgbe_setup_mac_link_multispeed_fiber_aml(hw,
+ highest_link_speed,
+ autoneg_wait_to_complete);
+
+out:
+ /* Set autoneg_advertised value based on input link speed */
+ hw->phy.autoneg_advertised = 0;
+
+ if (speed & TXGBE_LINK_SPEED_25GB_FULL)
+ hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_25GB_FULL;
+
+ if (speed & TXGBE_LINK_SPEED_10GB_FULL)
+ hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
+
+ return status;
+}
+
+void txgbe_init_mac_link_ops_aml(struct txgbe_hw *hw)
+{
+ struct txgbe_mac_info *mac = &hw->mac;
+
+ if (hw->phy.media_type == txgbe_media_type_fiber ||
+ hw->phy.media_type == txgbe_media_type_fiber_qsfp) {
+ mac->disable_tx_laser =
+ txgbe_disable_tx_laser_multispeed_fiber;
+ mac->enable_tx_laser =
+ txgbe_enable_tx_laser_multispeed_fiber;
+ mac->flap_tx_laser =
+ txgbe_flap_tx_laser_multispeed_fiber;
+
+ if (hw->phy.multispeed_fiber) {
+ /* Set up dual speed SFP+ support */
+ mac->setup_link = txgbe_setup_mac_link_multispeed_fiber_aml;
+ mac->setup_mac_link = txgbe_setup_mac_link_aml;
+ mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
+ } else {
+ mac->setup_link = txgbe_setup_mac_link_aml;
+ mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
+ }
+ }
+}
diff --git a/drivers/net/txgbe/base/txgbe_aml.h b/drivers/net/txgbe/base/txgbe_aml.h
new file mode 100644
index 0000000000..18f683a746
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_aml.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
+ */
+
+#ifndef _TXGBE_AML_H_
+#define _TXGBE_AML_H_
+
+#include "txgbe_type.h"
+
+void txgbe_init_ops_aml(struct txgbe_hw *hw);
+s32 txgbe_check_mac_link_aml(struct txgbe_hw *hw,
+ u32 *speed,
+ bool *link_up, bool link_up_wait_to_complete);
+s32 txgbe_get_link_capabilities_aml(struct txgbe_hw *hw,
+ u32 *speed, bool *autoneg);
+u32 txgbe_get_media_type_aml(struct txgbe_hw *hw);
+s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw, u32 speed,
+ bool autoneg_wait_to_complete);
+void txgbe_init_mac_link_ops_aml(struct txgbe_hw *hw);
+#endif /* _TXGBE_AML_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_aml40.c b/drivers/net/txgbe/base/txgbe_aml40.c
new file mode 100644
index 0000000000..2bad990aa8
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_aml40.c
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
+ */
+
+#include "txgbe_type.h"
+#include "txgbe_mbx.h"
+#include "txgbe_phy.h"
+#include "txgbe_dcb.h"
+#include "txgbe_vf.h"
+#include "txgbe_eeprom.h"
+#include "txgbe_mng.h"
+#include "txgbe_hw.h"
+#include "txgbe_aml.h"
+#include "txgbe_aml40.h"
+
+void txgbe_init_ops_aml40(struct txgbe_hw *hw)
+{
+ struct txgbe_mac_info *mac = &hw->mac;
+ struct txgbe_phy_info *phy = &hw->phy;
+
+ txgbe_init_ops_generic(hw);
+
+ /* PHY */
+ phy->get_media_type = txgbe_get_media_type_aml40;
+
+ /* LINK */
+ mac->init_mac_link_ops = txgbe_init_mac_link_ops_aml40;
+ mac->get_link_capabilities = txgbe_get_link_capabilities_aml40;
+ mac->check_link = txgbe_check_mac_link_aml40;
+}
+
+s32 txgbe_check_mac_link_aml40(struct txgbe_hw *hw, u32 *speed,
+ bool *link_up, bool link_up_wait_to_complete)
+{
+ u32 links_reg, links_orig;
+ u32 i;
+
+ /* clear the old state */
+ links_orig = rd32(hw, TXGBE_PORTSTAT);
+
+ links_reg = rd32(hw, TXGBE_PORTSTAT);
+
+ if (links_orig != links_reg) {
+ DEBUGOUT("LINKS changed from %08X to %08X",
+ links_orig, links_reg);
+ }
+
+ if (link_up_wait_to_complete) {
+ for (i = 0; i < hw->mac.max_link_up_time; i++) {
+ if (!(links_reg & TXGBE_PORTSTAT_UP)) {
+ *link_up = false;
+ } else {
+ *link_up = true;
+ break;
+ }
+ msec_delay(100);
+ links_reg = rd32(hw, TXGBE_PORTSTAT);
+ }
+ } else {
+ if (links_reg & TXGBE_PORTSTAT_UP)
+ *link_up = true;
+ else
+ *link_up = false;
+ }
+
+ if (link_up) {
+ if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_40G) ==
+ TXGBE_CFG_PORT_ST_AML_LINK_40G)
+ *speed = TXGBE_LINK_SPEED_40GB_FULL;
+ } else
+ *speed = TXGBE_LINK_SPEED_UNKNOWN;
+
+ return 0;
+}
+
+s32 txgbe_get_link_capabilities_aml40(struct txgbe_hw *hw,
+ u32 *speed,
+ bool *autoneg)
+{
+ if (hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core0 ||
+ hw->phy.sfp_type == txgbe_qsfp_type_40g_cu_core1) {
+ *speed = TXGBE_LINK_SPEED_40GB_FULL;
+ *autoneg = false;
+ } else {
+ /*
+ * Temporary workaround: set speed to 40G even if sfp not present
+ * to avoid TXGBE_ERR_LINK_SETUP returned by setup_mac_link, but
+ * a more reasonable solution is don't execute setup_mac_link when
+ * sfp module not present.
+ */
+ *speed = TXGBE_LINK_SPEED_40GB_FULL;
+ *autoneg = true;
+ }
+
+ return 0;
+}
+
+u32 txgbe_get_media_type_aml40(struct txgbe_hw *hw)
+{
+ UNREFERENCED_PARAMETER(hw);
+ return txgbe_media_type_fiber_qsfp;
+}
+
+s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw,
+ u32 speed,
+ bool autoneg_wait_to_complete)
+{
+ return 0;
+}
+
+void txgbe_init_mac_link_ops_aml40(struct txgbe_hw *hw)
+{
+ struct txgbe_mac_info *mac = &hw->mac;
+
+ mac->disable_tx_laser =
+ txgbe_disable_tx_laser_multispeed_fiber;
+ mac->enable_tx_laser =
+ txgbe_enable_tx_laser_multispeed_fiber;
+ mac->flap_tx_laser =
+ txgbe_flap_tx_laser_multispeed_fiber;
+
+ mac->setup_link = txgbe_setup_mac_link_aml40;
+ mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
+}
diff --git a/drivers/net/txgbe/base/txgbe_aml40.h b/drivers/net/txgbe/base/txgbe_aml40.h
new file mode 100644
index 0000000000..f31360c899
--- /dev/null
+++ b/drivers/net/txgbe/base/txgbe_aml40.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015-2025 Beijing WangXun Technology Co., Ltd.
+ * Copyright(c) 2010-2017 Intel Corporation
+ */
+
+#ifndef _TXGBE_AML40_H_
+#define _TXGBE_AML40_H_
+
+#include "txgbe_type.h"
+
+void txgbe_init_ops_aml40(struct txgbe_hw *hw);
+s32 txgbe_check_mac_link_aml40(struct txgbe_hw *hw,
+ u32 *speed, bool *link_up, bool link_up_wait_to_complete);
+s32 txgbe_get_link_capabilities_aml40(struct txgbe_hw *hw,
+ u32 *speed, bool *autoneg);
+u32 txgbe_get_media_type_aml40(struct txgbe_hw *hw);
+s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw, u32 speed,
+ bool autoneg_wait_to_complete);
+void txgbe_init_mac_link_ops_aml40(struct txgbe_hw *hw);
+#endif /* _TXGBE_AML40_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 85dbbc5eff..b14ab90466 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -11,6 +11,8 @@
#include "txgbe_eeprom.h"
#include "txgbe_mng.h"
#include "txgbe_hw.h"
+#include "txgbe_aml.h"
+#include "txgbe_aml40.h"
#define TXGBE_RAPTOR_MAX_TX_QUEUES 128
#define TXGBE_RAPTOR_MAX_RX_QUEUES 128
@@ -1906,7 +1908,7 @@ static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
*
* Reads the links register to determine if link is up and the current speed
**/
-s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
+s32 txgbe_check_mac_link_sp(struct txgbe_hw *hw, u32 *speed,
bool *link_up, bool link_up_wait_to_complete)
{
u32 links_reg, links_orig;
@@ -2459,7 +2461,7 @@ s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
**/
s32 txgbe_init_shared_code(struct txgbe_hw *hw)
{
- s32 status;
+ s32 status = 0;
/*
* Set the mac type
@@ -2469,11 +2471,16 @@ s32 txgbe_init_shared_code(struct txgbe_hw *hw)
txgbe_init_ops_dummy(hw);
switch (hw->mac.type) {
case txgbe_mac_raptor:
+ txgbe_init_ops_sp(hw);
+ break;
case txgbe_mac_aml:
+ txgbe_init_ops_aml(hw);
+ break;
case txgbe_mac_aml40:
- status = txgbe_init_ops_pf(hw);
+ txgbe_init_ops_aml40(hw);
break;
case txgbe_mac_raptor_vf:
+ case txgbe_mac_aml_vf:
status = txgbe_init_ops_vf(hw);
break;
default:
@@ -2539,7 +2546,7 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw)
return err;
}
-void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
+void txgbe_init_mac_link_ops_sp(struct txgbe_hw *hw)
{
struct txgbe_mac_info *mac = &hw->mac;
@@ -2599,7 +2606,7 @@ s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
goto init_phy_ops_out;
/* Setup function pointers based on detected SFP module and speeds */
- txgbe_init_mac_link_ops(hw);
+ hw->mac.init_mac_link_ops(hw);
/* If copper media, overwrite with copper function pointers */
if (phy->media_type == txgbe_media_type_copper) {
@@ -2634,7 +2641,7 @@ s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
return 0;
- txgbe_init_mac_link_ops(hw);
+ hw->mac.init_mac_link_ops(hw);
/* PHY config will finish before releasing the semaphore */
err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
@@ -2781,7 +2788,7 @@ s32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr, u32 *data)
* Initialize the function pointers and assign the MAC type.
* Does not touch the hardware.
**/
-s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
+s32 txgbe_init_ops_generic(struct txgbe_hw *hw)
{
struct txgbe_bus_info *bus = &hw->bus;
struct txgbe_mac_info *mac = &hw->mac;
@@ -2793,7 +2800,6 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
bus->set_lan_id = txgbe_set_lan_id_multi_port;
/* PHY */
- phy->get_media_type = txgbe_get_media_type_raptor;
phy->identify = txgbe_identify_phy;
phy->init = txgbe_init_phy_raptor;
phy->read_reg = txgbe_read_phy_reg;
@@ -2861,8 +2867,6 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
mac->fc_autoneg = txgbe_fc_autoneg;
/* Link */
- mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
- mac->check_link = txgbe_check_mac_link;
mac->setup_pba = txgbe_set_pba;
/* Manageability interface */
@@ -2901,6 +2905,22 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
return 0;
}
+void txgbe_init_ops_sp(struct txgbe_hw *hw)
+{
+ struct txgbe_mac_info *mac = &hw->mac;
+ struct txgbe_phy_info *phy = &hw->phy;
+
+ txgbe_init_ops_generic(hw);
+
+ /* PHY */
+ phy->get_media_type = txgbe_get_media_type_sp;
+
+ /* LINK */
+ mac->init_mac_link_ops = txgbe_init_mac_link_ops_sp;
+ mac->get_link_capabilities = txgbe_get_link_capabilities_sp;
+ mac->check_link = txgbe_check_mac_link_sp;
+}
+
/**
* txgbe_get_link_capabilities_raptor - Determines link capabilities
* @hw: pointer to hardware structure
@@ -2909,7 +2929,7 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
*
* Determines the link capabilities by reading the AUTOC register.
**/
-s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
+s32 txgbe_get_link_capabilities_sp(struct txgbe_hw *hw,
u32 *speed,
bool *autoneg)
{
@@ -3015,7 +3035,7 @@ s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
*
* Returns the media type (fiber, copper, backplane)
**/
-u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
+u32 txgbe_get_media_type_sp(struct txgbe_hw *hw)
{
u32 media_type;
@@ -3849,3 +3869,37 @@ s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
return err;
}
+s32 txgbe_e56_check_phy_link(struct txgbe_hw *hw, u32 *speed,
+ bool *link_up)
+{
+ u32 rdata = 0;
+ u32 links_reg = 0;
+
+ /* must read it twice because the state may
+ * not be correct the first time you read it
+ */
+ rdata = rd32_epcs(hw, 0x30001);
+ rdata = rd32_epcs(hw, 0x30001);
+
+ if (rdata & TXGBE_AML_PHY_LINK_UP)
+ *link_up = true;
+ else
+ *link_up = false;
+
+ links_reg = rd32(hw, TXGBE_PORTSTAT);
+ if (*link_up) {
+ if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_40G) ==
+ TXGBE_CFG_PORT_ST_AML_LINK_40G)
+ *speed = TXGBE_LINK_SPEED_40GB_FULL;
+ else if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_25G) ==
+ TXGBE_CFG_PORT_ST_AML_LINK_25G)
+ *speed = TXGBE_LINK_SPEED_25GB_FULL;
+ else if ((links_reg & TXGBE_CFG_PORT_ST_AML_LINK_10G) ==
+ TXGBE_CFG_PORT_ST_AML_LINK_10G)
+ *speed = TXGBE_LINK_SPEED_10GB_FULL;
+ } else {
+ *speed = TXGBE_LINK_SPEED_UNKNOWN;
+ }
+
+ return 0;
+}
diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h
index 1ed2892f61..476a9688bd 100644
--- a/drivers/net/txgbe/base/txgbe_hw.h
+++ b/drivers/net/txgbe/base/txgbe_hw.h
@@ -56,7 +56,7 @@ s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,
s32 txgbe_clear_vfta(struct txgbe_hw *hw);
s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass);
-s32 txgbe_check_mac_link(struct txgbe_hw *hw,
+s32 txgbe_check_mac_link_sp(struct txgbe_hw *hw,
u32 *speed,
bool *link_up, bool link_up_wait_to_complete);
@@ -86,10 +86,11 @@ s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg,
u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
s32 txgbe_init_shared_code(struct txgbe_hw *hw);
s32 txgbe_set_mac_type(struct txgbe_hw *hw);
-s32 txgbe_init_ops_pf(struct txgbe_hw *hw);
-s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
+s32 txgbe_init_ops_generic(struct txgbe_hw *hw);
+void txgbe_init_ops_sp(struct txgbe_hw *hw);
+s32 txgbe_get_link_capabilities_sp(struct txgbe_hw *hw,
u32 *speed, bool *autoneg);
-u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw);
+u32 txgbe_get_media_type_sp(struct txgbe_hw *hw);
void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw);
void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw);
void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw);
@@ -103,7 +104,7 @@ s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
s32 txgbe_setup_mac_link(struct txgbe_hw *hw, u32 speed,
bool autoneg_wait_to_complete);
s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw);
-void txgbe_init_mac_link_ops(struct txgbe_hw *hw);
+void txgbe_init_mac_link_ops_sp(struct txgbe_hw *hw);
s32 txgbe_reset_hw(struct txgbe_hw *hw);
s32 txgbe_start_hw_raptor(struct txgbe_hw *hw);
s32 txgbe_init_phy_raptor(struct txgbe_hw *hw);
@@ -114,4 +115,6 @@ s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw);
bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw);
s32 txgbe_fmgr_cmd_op(struct txgbe_hw *hw, u32 cmd, u32 cmd_addr);
s32 txgbe_flash_read_dword(struct txgbe_hw *hw, u32 addr, u32 *data);
+s32 txgbe_e56_check_phy_link(struct txgbe_hw *hw, u32 *speed,
+ bool *link_up);
#endif /* _TXGBE_HW_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index 03c517f055..4777b0335b 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -1577,6 +1577,15 @@ enum txgbe_5tuple_protocol {
#define TXGBE_PORTSTAT_BW_100M MS(3, 0x1)
#define TXGBE_PORTSTAT_ID(r) RS(r, 8, 0x1)
+/* amlite: diff from sapphire */
+#define TXGBE_CFG_PORT_ST_AML_LINK_MASK MS(1, 0xF)
+#define TXGBE_CFG_PORT_ST_AML_LINK_10G MS(4, 0x1)
+#define TXGBE_CFG_PORT_ST_AML_LINK_25G MS(3, 0x1)
+#define TXGBE_CFG_PORT_ST_AML_LINK_40G MS(2, 0x1)
+#define TXGBE_CFG_PORT_ST_AML_LINK_50G MS(1, 0x1)
+
+#define TXGBE_AML_PHY_LINK_UP MS(2, 0x1)
+
#define TXGBE_VXLAN 0x014410
#define TXGBE_VXLAN_GPE 0x014414
#define TXGBE_GENEVE 0x014418
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index b6dce31473..8eeea54f98 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -551,6 +551,7 @@ struct txgbe_mac_info {
s32 (*prot_autoc_read)(struct txgbe_hw *hw, bool *locked, u64 *value);
s32 (*prot_autoc_write)(struct txgbe_hw *hw, bool locked, u64 value);
s32 (*negotiate_api_version)(struct txgbe_hw *hw, int api);
+ void (*init_mac_link_ops)(struct txgbe_hw *hw);
/* Link */
void (*disable_tx_laser)(struct txgbe_hw *hw);
@@ -834,6 +835,7 @@ struct txgbe_hw {
u64 rx_qp_mc_packets;
} qp_last[TXGBE_MAX_QP];
+ rte_spinlock_t phy_lock;
/*amlite: new SW-FW mbox */
u8 swfw_index;
rte_atomic32_t swfw_busy;
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 2431057485..e6b7775f3a 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -3068,6 +3068,14 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev,
case TXGBE_LINK_SPEED_10GB_FULL:
link.link_speed = RTE_ETH_SPEED_NUM_10G;
break;
+
+ case TXGBE_LINK_SPEED_25GB_FULL:
+ link.link_speed = RTE_ETH_SPEED_NUM_25G;
+ break;
+
+ case TXGBE_LINK_SPEED_40GB_FULL:
+ link.link_speed = RTE_ETH_SPEED_NUM_40G;
+ break;
}
/* Re configure MAC RX */
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 05/15] net/txgbe: add support for PHY configuration via SW-FW mailbox
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (3 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 04/15] net/txgbe: add basic link configuration for Amber-Lite NICs Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 06/15] net/txgbe: add RX&TX support for Amber-Lite NICs Zaiyu Wang
` (9 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Migrate Amber-Lite PHY configuration to firmware due to complexity.
Driver now sends mailbox commands for link state changes, handled
by firmware’s intricate PHY setup process
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_aml.c | 52 ++++++++++++++++------------
drivers/net/txgbe/base/txgbe_aml40.c | 37 +++++++++++++++++++-
drivers/net/txgbe/base/txgbe_hw.c | 1 +
drivers/net/txgbe/base/txgbe_mng.c | 36 +++++++++++++++++++
drivers/net/txgbe/base/txgbe_mng.h | 17 +++++++++
drivers/net/txgbe/base/txgbe_type.h | 7 ++++
6 files changed, 126 insertions(+), 24 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_aml.c b/drivers/net/txgbe/base/txgbe_aml.c
index 1b5a3783a9..510a539d38 100644
--- a/drivers/net/txgbe/base/txgbe_aml.c
+++ b/drivers/net/txgbe/base/txgbe_aml.c
@@ -131,21 +131,37 @@ u32 txgbe_get_media_type_aml(struct txgbe_hw *hw)
return media_type;
}
+static void txgbe_wait_for_link_up_aml(struct txgbe_hw *hw, u32 speed)
+{
+ u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
+ bool link_up = false;
+ int cnt = 0;
+ int i;
+
+ if (speed == TXGBE_LINK_SPEED_25GB_FULL)
+ cnt = 4;
+ else
+ cnt = 1;
+
+ for (i = 0; i < (4 * cnt); i++) {
+ hw->mac.check_link(hw, &link_speed, &link_up, false);
+ if (link_up)
+ break;
+ msleep(250);
+ }
+}
+
s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw,
u32 speed,
bool autoneg_wait_to_complete)
{
bool autoneg = false;
s32 status = 0;
- s32 ret_status = 0;
u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
bool link_up = false;
- int i;
u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
u32 value = 0;
- UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
-
if (hw->phy.sfp_type == txgbe_sfp_type_not_present) {
DEBUGOUT("SFP not detected, skip setup mac link");
return 0;
@@ -165,30 +181,20 @@ s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw,
if (value & (TXGBE_SFP1_MOD_ABS_LS | TXGBE_SFP1_RX_LOS_LS))
return status;
- for (i = 0; i < 4; i++) {
- txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
- if (link_up)
- break;
- msleep(250);
- }
+ status = hw->mac.check_link(hw, &link_speed, &link_up,
+ autoneg_wait_to_complete);
- if (link_speed == speed && link_up &&
- !(speed == TXGBE_LINK_SPEED_25GB_FULL))
+ if (link_speed == speed && link_up)
return status;
- rte_spinlock_lock(&hw->phy_lock);
- ret_status = 0;
- rte_spinlock_unlock(&hw->phy_lock);
+ if (speed & TXGBE_LINK_SPEED_25GB_FULL)
+ speed = 0x10;
+ else if (speed & TXGBE_LINK_SPEED_10GB_FULL)
+ speed = 0x08;
- if (ret_status == TXGBE_ERR_PHY_INIT_NOT_DONE)
- return status;
+ status = hw->phy.set_link_hostif(hw, (u8)speed, autoneg, true);
- for (i = 0; i < 4; i++) {
- txgbe_e56_check_phy_link(hw, &link_speed, &link_up);
- if (link_up)
- return status;
- msleep(250);
- }
+ txgbe_wait_for_link_up_aml(hw, speed);
return status;
}
diff --git a/drivers/net/txgbe/base/txgbe_aml40.c b/drivers/net/txgbe/base/txgbe_aml40.c
index 2bad990aa8..88408550d2 100644
--- a/drivers/net/txgbe/base/txgbe_aml40.c
+++ b/drivers/net/txgbe/base/txgbe_aml40.c
@@ -106,7 +106,42 @@ s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw,
u32 speed,
bool autoneg_wait_to_complete)
{
- return 0;
+ bool autoneg = false;
+ s32 status = 0;
+ u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
+ bool link_up = false;
+ u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
+ u32 value = 0;
+
+ if (hw->phy.sfp_type == txgbe_sfp_type_not_present) {
+ DEBUGOUT("SFP not detected, skip setup mac link");
+ return 0;
+ }
+
+ /* Check to see if speed passed in is supported. */
+ status = hw->mac.get_link_capabilities(hw,
+ &link_capabilities, &autoneg);
+ if (status)
+ return status;
+
+ speed &= link_capabilities;
+ if (speed == TXGBE_LINK_SPEED_UNKNOWN)
+ return TXGBE_ERR_LINK_SETUP;
+
+ status = hw->mac.check_link(hw, &link_speed, &link_up,
+ autoneg_wait_to_complete);
+
+ if (link_speed == speed && link_up)
+ return status;
+
+ if (speed & TXGBE_LINK_SPEED_40GB_FULL)
+ speed = 0x20;
+
+ status = hw->phy.set_link_hostif(hw, (u8)speed, autoneg, true);
+
+ txgbe_wait_for_link_up_aml(hw, speed);
+
+ return status;
}
void txgbe_init_mac_link_ops_aml40(struct txgbe_hw *hw)
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index b14ab90466..1e30d235fd 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -2819,6 +2819,7 @@ s32 txgbe_init_ops_generic(struct txgbe_hw *hw)
phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked;
phy->check_overtemp = txgbe_check_overtemp;
phy->reset = txgbe_reset_phy;
+ phy->set_link_hostif = txgbe_hic_ephy_set_link;
/* MAC */
mac->init_hw = txgbe_init_hw;
diff --git a/drivers/net/txgbe/base/txgbe_mng.c b/drivers/net/txgbe/base/txgbe_mng.c
index 8327c5fa01..7af43c7b44 100644
--- a/drivers/net/txgbe/base/txgbe_mng.c
+++ b/drivers/net/txgbe/base/txgbe_mng.c
@@ -590,3 +590,39 @@ s32 txgbe_hic_set_lldp(struct txgbe_hw *hw, bool on)
return txgbe_host_interface_command(hw, (u32 *)&buffer, sizeof(buffer),
TXGBE_HI_COMMAND_TIMEOUT, false);
}
+
+s32 txgbe_hic_ephy_set_link(struct txgbe_hw *hw, u8 speed, u8 autoneg, u8 duplex)
+{
+ struct txgbe_hic_ephy_setlink buffer;
+ s32 status;
+ int i;
+
+ buffer.hdr.cmd = FW_PHY_CONFIG_LINK_CMD;
+ buffer.hdr.buf_len = sizeof(struct txgbe_hic_ephy_setlink) - sizeof(struct txgbe_hic_hdr);
+ buffer.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
+
+ buffer.fec_mode = TXGBE_PHY_FEC_AUTO;
+ buffer.speed = speed;
+ buffer.autoneg = autoneg;
+ buffer.duplex = duplex;
+
+ for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
+ status = txgbe_host_interface_command(hw, (u32 *)&buffer,
+ sizeof(buffer),
+ TXGBE_HI_COMMAND_TIMEOUT_SHORT, true);
+ if (status != 0) {
+ msleep(1);
+ continue;
+ }
+
+ if (buffer.hdr.cmd_or_resp.ret_status ==
+ FW_CEM_RESP_STATUS_SUCCESS)
+ status = 0;
+ else
+ status = TXGBE_ERR_HOST_INTERFACE_COMMAND;
+
+ break;
+ }
+
+ return status;
+}
diff --git a/drivers/net/txgbe/base/txgbe_mng.h b/drivers/net/txgbe/base/txgbe_mng.h
index 5300970912..72f01b6229 100644
--- a/drivers/net/txgbe/base/txgbe_mng.h
+++ b/drivers/net/txgbe/base/txgbe_mng.h
@@ -13,6 +13,7 @@
#define TXGBE_PMMBX_BSIZE (TXGBE_PMMBX_QSIZE * 4)
#define TXGBE_PMMBX_DATA_SIZE (TXGBE_PMMBX_BSIZE - FW_NVM_DATA_OFFSET * 4)
#define TXGBE_HI_COMMAND_TIMEOUT 5000 /* Process HI command limit */
+#define TXGBE_HI_COMMAND_TIMEOUT_SHORT 500 /* Process HI command limit */
#define TXGBE_HI_FLASH_ERASE_TIMEOUT 5000 /* Process Erase command limit */
#define TXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */
#define TXGBE_HI_FLASH_VERIFY_TIMEOUT 60000 /* Process Apply command limit */
@@ -56,6 +57,12 @@
#define FW_LLDP_GET_CMD 0xF2
#define FW_LLDP_SET_CMD_OFF 0xF1
#define FW_LLDP_SET_CMD_ON 0xF0
+#define FW_PHY_CONFIG_READ_CMD 0xc0
+#define FW_PHY_CONFIG_LINK_CMD 0xc1
+#define FW_PHY_CONFIG_FC_CMD 0xc2
+#define FW_PHY_CONFIG_POWER_CMD 0xc3
+#define FW_PHY_CONFIG_RESET_CMD 0xc4
+#define FW_READ_SFP_INFO_CMD 0xc5
#define TXGBE_CHECKSUM_CAP_ST_PASS 0x80658383
#define TXGBE_CHECKSUM_CAP_ST_FAIL 0x70657376
@@ -101,6 +108,15 @@ union txgbe_hic_hdr2 {
struct txgbe_hic_hdr2_rsp rsp;
};
+struct txgbe_hic_ephy_setlink {
+ struct txgbe_hic_hdr hdr;
+ u8 speed;
+ u8 duplex;
+ u8 autoneg;
+ u8 fec_mode;
+ u8 resv[4];
+};
+
struct txgbe_hic_drv_info {
struct txgbe_hic_hdr hdr;
u8 port_num;
@@ -204,5 +220,6 @@ bool txgbe_mng_present(struct txgbe_hw *hw);
bool txgbe_mng_enabled(struct txgbe_hw *hw);
s32 txgbe_hic_get_lldp(struct txgbe_hw *hw);
s32 txgbe_hic_set_lldp(struct txgbe_hw *hw, bool on);
+s32 txgbe_hic_ephy_set_link(struct txgbe_hw *hw, u8 speed, u8 autoneg, u8 duplex);
#endif /* _TXGBE_MNG_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 8eeea54f98..8005283a26 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -688,6 +688,7 @@ struct txgbe_phy_info {
u8 *value);
s32 (*write_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr,
u8 value);
+ s32 (*set_link_hostif)(struct txgbe_hw *hw, u8 speed, u8 autoneg, u8 duplex);
enum txgbe_phy_type type;
u32 addr;
@@ -771,6 +772,12 @@ enum txgbe_isb_idx {
TXGBE_ISB_MAX
};
+#define TXGBE_PHY_FEC_RS MS(0, 0x1)
+#define TXGBE_PHY_FEC_BASER MS(1, 0x1)
+#define TXGBE_PHY_FEC_OFF MS(2, 0x1)
+#define TXGBE_PHY_FEC_AUTO (TXGBE_PHY_FEC_OFF | TXGBE_PHY_FEC_BASER |\
+ TXGBE_PHY_FEC_RS)
+
struct txgbe_devargs {
u16 auto_neg;
u16 poll;
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 06/15] net/txgbe: add RX&TX support for Amber-Lite NICs
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (4 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 05/15] net/txgbe: add support for PHY configuration via SW-FW mailbox Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 07/15] net/txgbe: add hardware reset change " Zaiyu Wang
` (8 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
The packet handling workflow largely reuses the existing 10G NIC’s
process, so we adjusted driver conditional checks rather than making
major changes to the overall flow.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_aml.c | 2 +-
drivers/net/txgbe/base/txgbe_aml.h | 1 +
drivers/net/txgbe/base/txgbe_aml40.c | 1 -
drivers/net/txgbe/base/txgbe_hw.c | 27 ++++++++++++
drivers/net/txgbe/base/txgbe_hw.h | 2 +
drivers/net/txgbe/base/txgbe_regs.h | 30 +++++++++++++
drivers/net/txgbe/txgbe_ethdev.c | 12 ++++--
drivers/net/txgbe/txgbe_rxtx.c | 64 +++++++++++++++-------------
8 files changed, 104 insertions(+), 35 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_aml.c b/drivers/net/txgbe/base/txgbe_aml.c
index 510a539d38..368b002c88 100644
--- a/drivers/net/txgbe/base/txgbe_aml.c
+++ b/drivers/net/txgbe/base/txgbe_aml.c
@@ -131,7 +131,7 @@ u32 txgbe_get_media_type_aml(struct txgbe_hw *hw)
return media_type;
}
-static void txgbe_wait_for_link_up_aml(struct txgbe_hw *hw, u32 speed)
+void txgbe_wait_for_link_up_aml(struct txgbe_hw *hw, u32 speed)
{
u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
bool link_up = false;
diff --git a/drivers/net/txgbe/base/txgbe_aml.h b/drivers/net/txgbe/base/txgbe_aml.h
index 18f683a746..e98c952787 100644
--- a/drivers/net/txgbe/base/txgbe_aml.h
+++ b/drivers/net/txgbe/base/txgbe_aml.h
@@ -15,6 +15,7 @@ s32 txgbe_check_mac_link_aml(struct txgbe_hw *hw,
s32 txgbe_get_link_capabilities_aml(struct txgbe_hw *hw,
u32 *speed, bool *autoneg);
u32 txgbe_get_media_type_aml(struct txgbe_hw *hw);
+void txgbe_wait_for_link_up_aml(struct txgbe_hw *hw, u32 speed);
s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw, u32 speed,
bool autoneg_wait_to_complete);
void txgbe_init_mac_link_ops_aml(struct txgbe_hw *hw);
diff --git a/drivers/net/txgbe/base/txgbe_aml40.c b/drivers/net/txgbe/base/txgbe_aml40.c
index 88408550d2..a2e034949e 100644
--- a/drivers/net/txgbe/base/txgbe_aml40.c
+++ b/drivers/net/txgbe/base/txgbe_aml40.c
@@ -111,7 +111,6 @@ s32 txgbe_setup_mac_link_aml40(struct txgbe_hw *hw,
u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
bool link_up = false;
u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
- u32 value = 0;
if (hw->phy.sfp_type == txgbe_sfp_type_not_present) {
DEBUGOUT("SFP not detected, skip setup mac link");
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 1e30d235fd..4fc4b4e284 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -20,6 +20,7 @@
#define TXGBE_RAPTOR_MC_TBL_SIZE 128
#define TXGBE_RAPTOR_VFT_TBL_SIZE 128
#define TXGBE_RAPTOR_RX_PB_SIZE 512 /*KB*/
+#define TXGBE_AML_RX_PB_SIZE 768
static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
u32 speed,
@@ -2494,6 +2495,29 @@ s32 txgbe_init_shared_code(struct txgbe_hw *hw)
return status;
}
+int txgbe_is_vf(struct txgbe_hw *hw)
+{
+ switch (hw->mac.type) {
+ case txgbe_mac_raptor_vf:
+ case txgbe_mac_aml_vf:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+int txgbe_is_pf(struct txgbe_hw *hw)
+{
+ switch (hw->mac.type) {
+ case txgbe_mac_raptor:
+ case txgbe_mac_aml:
+ case txgbe_mac_aml40:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
/**
* txgbe_set_mac_type - Sets MAC type
* @hw: pointer to the HW structure
@@ -2903,6 +2927,9 @@ s32 txgbe_init_ops_generic(struct txgbe_hw *hw)
mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
+ mac->rx_pb_size = TXGBE_AML_RX_PB_SIZE;
+
return 0;
}
diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h
index 476a9688bd..a7e9547430 100644
--- a/drivers/net/txgbe/base/txgbe_hw.h
+++ b/drivers/net/txgbe/base/txgbe_hw.h
@@ -85,6 +85,8 @@ void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr);
s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg,
u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
s32 txgbe_init_shared_code(struct txgbe_hw *hw);
+int txgbe_is_vf(struct txgbe_hw *hw);
+int txgbe_is_pf(struct txgbe_hw *hw);
s32 txgbe_set_mac_type(struct txgbe_hw *hw);
s32 txgbe_init_ops_generic(struct txgbe_hw *hw);
void txgbe_init_ops_sp(struct txgbe_hw *hw);
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index 4777b0335b..7830abac7b 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -318,12 +318,18 @@
#define TXGBE_LEDCTL_1G MS(2, 0x1)
#define TXGBE_LEDCTL_100M MS(3, 0x1)
#define TXGBE_LEDCTL_ACTIVE MS(4, 0x1)
+#define TXGBE_LINKUP_FILTER 0x014428
#define TXGBE_TAGTPID(i) (0x014430 + (i) * 4) /* 0-3 */
#define TXGBE_TAGTPID_LSB_MASK MS(0, 0xFFFF)
#define TXGBE_TAGTPID_LSB(v) LS(v, 0, 0xFFFF)
#define TXGBE_TAGTPID_MSB_MASK MS(16, 0xFFFF)
#define TXGBE_TAGTPID_MSB(v) LS(v, 16, 0xFFFF)
+/*AML LINK STATUS OVERWRITE*/
+#define TXGBE_AML_EPCS_MISC_CTL 0x13240
+#define TXGBE_AML_LINK_STATUS_OVRD_EN 0x00000020
+#define TXGBE_AML_LINK_STATUS_OVRD_VAL 0x00000010
+
/**
* GPIO Control
* P0: link speed change
@@ -1389,6 +1395,7 @@ enum txgbe_5tuple_protocol {
#define TXGBE_TXCFG_HTHRESH_MASK MS(8, 0xF)
#define TXGBE_TXCFG_HTHRESH(v) LS(v, 8, 0xF)
#define TXGBE_TXCFG_WTHRESH_MASK MS(16, 0x7F)
+#define TXGBE_TXCFG_WTHRESH_MASK_AML MS(16, 0x1FF)
#define TXGBE_TXCFG_WTHRESH(v) LS(v, 16, 0x7F)
#define TXGBE_TXCFG_FLUSH MS(26, 0x1)
@@ -1634,6 +1641,16 @@ enum txgbe_5tuple_protocol {
#define TXGBE_ARBRXCTL_WSP MS(2, 0x1)
#define TXGBE_ARBRXCTL_DIA MS(6, 0x1)
+#define TXGBE_RDM_VF_RE(_i) (0x12004 + ((_i) * 4))
+#define TXGBE_RDM_VFRE_CLR(_i) (0x120A0 + ((_i) * 4))
+#define TXGBE_RDM_RSC_CTL 0x1200C
+/* amlite: rdm_rsc_ctl_free_ctl */
+#define TXGBE_RDM_RSC_CTL_FREE_CTL MS(7, 0x1)
+#define TXGBE_RDM_RSC_CTL_FREE_CNT_DIS MS(8, 0x1)
+#define TXGBE_RDM_ARB_CFG(_i) (0x12040 + ((_i) * 4)) /* 8 of these (0-7) */
+#define TXGBE_RDM_PF_QDE(_i) (0x12080 + ((_i) * 4))
+#define TXGBE_RDM_PF_HIDE(_i) (0x12090 + ((_i) * 4))
+
#define TXGBE_RPUP2TC 0x019008
#define TXGBE_RPUP2TC_UP_SHIFT 3
#define TXGBE_RPUP2TC_UP_MASK 0x7
@@ -1708,6 +1725,19 @@ enum txgbe_5tuple_protocol {
#define TXGBE_MACTXCFG_SPEED_10G LS(0, 29, 0x3)
#define TXGBE_MACTXCFG_SPEED_1G LS(3, 29, 0x3)
+#define TXGBE_MAC_TX_CFG_AML_SPEED_MASK 0x78000000U
+#define TXGBE_MAC_TX_CFG_AML_SPEED_50G 0x20000000U
+#define TXGBE_MAC_TX_CFG_AML_SPEED_40G 0x00000000U
+#define TXGBE_MAC_TX_CFG_AML_SPEED_25G 0x10000000U
+#define TXGBE_MAC_TX_CFG_AML_SPEED_10G 0x40000000U
+#define TXGBE_MAC_TX_CFG_AML_SPEED_1G 0x70000000U
+
+#define TXGBE_MAC_MISC_CTL 0x11f00
+#define TXGBE_MAC_MISC_LINK_STS_MOD MS(0, 0x1)
+#define TXGBE_LINK_BOTH_PCS_MAC MS(0, 0x1)
+
+#define TXGBE_EPHY_STAT 0x13404
+#define TXGBE_EPHY_STAT_PPL_LOCK 0x3
#define TXGBE_ISBADDRL 0x000160
#define TXGBE_ISBADDRH 0x000164
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index e6b7775f3a..cba1e8f2a7 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -385,7 +385,7 @@ txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
uint32_t q_map;
uint8_t n, offset;
- if (hw->mac.type != txgbe_mac_raptor)
+ if (!txgbe_is_pf(hw))
return -ENOSYS;
if (stat_idx & ~QMAP_FIELD_RESERVED_BITS_MASK)
@@ -1806,7 +1806,7 @@ txgbe_dev_start(struct rte_eth_dev *dev)
}
/* Skip link setup if loopback mode is enabled. */
- if (hw->mac.type == txgbe_mac_raptor &&
+ if (txgbe_is_pf(hw) &&
dev->data->dev_conf.lpbk_mode)
goto skip_link_setup;
@@ -2816,6 +2816,7 @@ txgbe_dev_sfp_event(struct rte_eth_dev *dev)
wr32(hw, TXGBE_GPIOINTMASK, 0xFF);
reg = rd32(hw, TXGBE_GPIORAWINTSTAT);
+
if (reg & TXGBE_GPIOBIT_0)
wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_0);
if (reg & TXGBE_GPIOBIT_2) {
@@ -3078,8 +3079,13 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev,
break;
}
+ /* enable mac receiver */
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) {
+ wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
+ }
+
/* Re configure MAC RX */
- if (hw->mac.type == txgbe_mac_raptor) {
+ if (txgbe_is_pf(hw)) {
reg = rd32(hw, TXGBE_MACRXCFG);
wr32(hw, TXGBE_MACRXCFG, reg);
wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_PROMISC,
diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c
index 4e4b78fb43..558ffbf73f 100644
--- a/drivers/net/txgbe/txgbe_rxtx.c
+++ b/drivers/net/txgbe/txgbe_rxtx.c
@@ -74,19 +74,6 @@ static const u64 TXGBE_TX_OFFLOAD_MASK = (RTE_MBUF_F_TX_IP_CKSUM |
*/
#define rte_txgbe_prefetch(p) rte_prefetch0(p)
-static int
-txgbe_is_vf(struct rte_eth_dev *dev)
-{
- struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
-
- switch (hw->mac.type) {
- case txgbe_mac_raptor_vf:
- return 1;
- default:
- return 0;
- }
-}
-
/*********************************************************************
*
* TX functions
@@ -2110,7 +2097,7 @@ txgbe_get_rx_port_offloads(struct rte_eth_dev *dev)
RTE_ETH_RX_OFFLOAD_RSS_HASH |
RTE_ETH_RX_OFFLOAD_SCATTER;
- if (!txgbe_is_vf(dev))
+ if (!txgbe_is_vf(hw))
offloads |= (RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
RTE_ETH_RX_OFFLOAD_QINQ_STRIP |
RTE_ETH_RX_OFFLOAD_VLAN_EXTEND);
@@ -2119,10 +2106,10 @@ txgbe_get_rx_port_offloads(struct rte_eth_dev *dev)
* RSC is only supported by PF devices in a non-SR-IOV
* mode.
*/
- if (hw->mac.type == txgbe_mac_raptor && !sriov->active)
+ if (txgbe_is_pf(hw) && !sriov->active)
offloads |= RTE_ETH_RX_OFFLOAD_TCP_LRO;
- if (hw->mac.type == txgbe_mac_raptor)
+ if (txgbe_is_pf(hw))
offloads |= RTE_ETH_RX_OFFLOAD_MACSEC_STRIP;
offloads |= RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM;
@@ -2361,6 +2348,7 @@ uint64_t
txgbe_get_tx_port_offloads(struct rte_eth_dev *dev)
{
uint64_t tx_offload_capa;
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
tx_offload_capa =
RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
@@ -2378,7 +2366,7 @@ txgbe_get_tx_port_offloads(struct rte_eth_dev *dev)
RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
- if (!txgbe_is_vf(dev))
+ if (!txgbe_is_vf(hw))
tx_offload_capa |= RTE_ETH_TX_OFFLOAD_QINQ_INSERT;
tx_offload_capa |= RTE_ETH_TX_OFFLOAD_MACSEC_INSERT;
@@ -2496,7 +2484,7 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
/* Modification to set tail pointer for virtual function
* if vf is detected.
*/
- if (hw->mac.type == txgbe_mac_raptor_vf) {
+ if (txgbe_is_vf(hw)) {
txq->tdt_reg_addr = TXGBE_REG_ADDR(hw, TXGBE_TXWP(queue_idx));
txq->tdc_reg_addr = TXGBE_REG_ADDR(hw, TXGBE_TXCFG(queue_idx));
} else {
@@ -2789,7 +2777,7 @@ txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
/*
* Modified to setup VFRDT for Virtual Function
*/
- if (hw->mac.type == txgbe_mac_raptor_vf) {
+ if (txgbe_is_vf(hw)) {
rxq->rdt_reg_addr =
TXGBE_REG_ADDR(hw, TXGBE_RXWP(queue_idx));
rxq->rdh_reg_addr =
@@ -3035,7 +3023,7 @@ txgbe_rss_disable(struct rte_eth_dev *dev)
struct txgbe_hw *hw;
hw = TXGBE_DEV_HW(dev);
- if (hw->mac.type == txgbe_mac_raptor_vf)
+ if (txgbe_is_vf(hw))
wr32m(hw, TXGBE_VFPLCFG, TXGBE_VFPLCFG_RSSENA, 0);
else
wr32m(hw, TXGBE_RACTL, TXGBE_RACTL_RSSENA, 0);
@@ -3072,7 +3060,7 @@ txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
/* Set configured hashing protocols */
rss_hf = rss_conf->rss_hf & TXGBE_RSS_OFFLOAD_ALL;
- if (hw->mac.type == txgbe_mac_raptor_vf) {
+ if (txgbe_is_vf(hw)) {
mrqc = rd32(hw, TXGBE_VFPLCFG);
mrqc &= ~TXGBE_VFPLCFG_RSSMASK;
if (rss_hf & RTE_ETH_RSS_IPV4)
@@ -3156,7 +3144,7 @@ txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
}
rss_hf = 0;
- if (hw->mac.type == txgbe_mac_raptor_vf) {
+ if (txgbe_is_vf(hw)) {
mrqc = rd32(hw, TXGBE_VFPLCFG);
if (mrqc & TXGBE_VFPLCFG_RSSIPV4)
rss_hf |= RTE_ETH_RSS_IPV4;
@@ -3610,6 +3598,8 @@ txgbe_dcb_hw_arbite_tx_config(struct txgbe_hw *hw, uint16_t *refill,
{
switch (hw->mac.type) {
case txgbe_mac_raptor:
+ case txgbe_mac_aml:
+ case txgbe_mac_aml40:
txgbe_dcb_config_tx_desc_arbiter_raptor(hw, refill,
max, bwg_id, tsa);
txgbe_dcb_config_tx_data_arbiter_raptor(hw, refill,
@@ -4537,7 +4527,7 @@ txgbe_dev_rx_init(struct rte_eth_dev *dev)
* If loopback mode is configured, set LPBK bit.
*/
hlreg0 = rd32(hw, TXGBE_PSRCTL);
- if (hw->mac.type == txgbe_mac_raptor &&
+ if (txgbe_is_pf(hw) &&
dev->data->dev_conf.lpbk_mode)
hlreg0 |= TXGBE_PSRCTL_LBENA;
else
@@ -4622,7 +4612,7 @@ txgbe_dev_rx_init(struct rte_eth_dev *dev)
wr32(hw, TXGBE_PSRCTL, rxcsum);
- if (hw->mac.type == txgbe_mac_raptor) {
+ if (txgbe_is_pf(hw)) {
rdrxctl = rd32(hw, TXGBE_SECRXCTL);
if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
rdrxctl &= ~TXGBE_SECRXCTL_CRCSTRIP;
@@ -4712,11 +4702,18 @@ txgbe_dev_rxtx_start(struct rte_eth_dev *dev)
for (i = 0; i < dev->data->nb_tx_queues; i++) {
txq = dev->data->tx_queues[i];
/* Setup Transmit Threshold Registers */
- wr32m(hw, TXGBE_TXCFG(txq->reg_idx),
- TXGBE_TXCFG_HTHRESH_MASK |
- TXGBE_TXCFG_WTHRESH_MASK,
- TXGBE_TXCFG_HTHRESH(txq->hthresh) |
- TXGBE_TXCFG_WTHRESH(txq->wthresh));
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
+ wr32m(hw, TXGBE_TXCFG(txq->reg_idx),
+ TXGBE_TXCFG_HTHRESH_MASK |
+ TXGBE_TXCFG_WTHRESH_MASK_AML,
+ TXGBE_TXCFG_HTHRESH(txq->hthresh) |
+ TXGBE_TXCFG_WTHRESH(txq->wthresh));
+ else
+ wr32m(hw, TXGBE_TXCFG(txq->reg_idx),
+ TXGBE_TXCFG_HTHRESH_MASK |
+ TXGBE_TXCFG_WTHRESH_MASK,
+ TXGBE_TXCFG_HTHRESH(txq->hthresh) |
+ TXGBE_TXCFG_WTHRESH(txq->wthresh));
}
dmatxctl = rd32(hw, TXGBE_DMATXCTRL);
@@ -4741,13 +4738,20 @@ txgbe_dev_rxtx_start(struct rte_eth_dev *dev)
}
}
+ /* enable mac transmitter */
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) {
+ wr32(hw, TXGBE_SECTXCTL, 0);
+ wr32m(hw, TXGBE_MACTXCFG,
+ TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
+ }
+
/* Enable Receive engine */
rxctrl = rd32(hw, TXGBE_PBRXCTL);
rxctrl |= TXGBE_PBRXCTL_ENA;
hw->mac.enable_rx_dma(hw, rxctrl);
/* If loopback mode is enabled, set up the link accordingly */
- if (hw->mac.type == txgbe_mac_raptor &&
+ if (txgbe_is_pf(hw) &&
dev->data->dev_conf.lpbk_mode)
txgbe_setup_loopback_link_raptor(hw);
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 07/15] net/txgbe: add hardware reset change for Amber-Lite NICs
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (5 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 06/15] net/txgbe: add RX&TX support for Amber-Lite NICs Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 08/15] net/txgbe: add MAC reconfiguration to avoid packet loss Zaiyu Wang
` (7 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Add necessary configurations for Amber-Lite's hardware reset
process, which differs from the 10G NIC's. These configurations
may be modified in future to accommodate further changes.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_hw.c | 72 ++++++++++++++++++++++-------
drivers/net/txgbe/base/txgbe_regs.h | 2 +
2 files changed, 58 insertions(+), 16 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 4fc4b4e284..f82bbee6f0 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -267,6 +267,8 @@ s32 txgbe_start_hw(struct txgbe_hw *hw)
/* Cache bit indicating need for crosstalk fix */
switch (hw->mac.type) {
case txgbe_mac_raptor:
+ case txgbe_mac_aml:
+ case txgbe_mac_aml40:
hw->mac.get_device_caps(hw, &device_caps);
if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
hw->need_crosstalk_fix = false;
@@ -3500,13 +3502,37 @@ txgbe_reset_misc(struct txgbe_hw *hw)
{
int i;
u32 value;
+ int err = 0;
+ u32 speed;
wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
- value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
- if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
- hw->link_status = TXGBE_LINK_STATUS_NONE;
+ if (hw->mac.type == txgbe_mac_aml) {
+ if ((rd32(hw, TXGBE_EPHY_STAT) & TXGBE_EPHY_STAT_PPL_LOCK)
+ != TXGBE_EPHY_STAT_PPL_LOCK) {
+ speed = TXGBE_LINK_SPEED_25GB_FULL
+ | TXGBE_LINK_SPEED_10GB_FULL;
+ err = hw->mac.setup_link(hw, speed, false);
+ if (err) {
+ DEBUGOUT("setup phy failed");
+ return;
+ }
+ }
+ } else if (hw->mac.type == txgbe_mac_aml40) {
+ if (!(rd32(hw, TXGBE_EPHY_STAT) & TXGBE_EPHY_STAT_PPL_LOCK)) {
+ speed = TXGBE_LINK_SPEED_40GB_FULL;
+ err = hw->mac.setup_link(hw, speed, false);
+ if (err) {
+ DEBUGOUT("setup phy failed");
+ return;
+ }
+ }
+ } else {
+ value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
+ if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
+ hw->link_status = TXGBE_LINK_STATUS_NONE;
+ }
/* receive packets that size > 2048 */
wr32m(hw, TXGBE_MACRXCFG,
@@ -3596,9 +3622,10 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw)
if (!hw->phy.reset_disable)
hw->phy.reset(hw);
- /* remember AUTOC from before we reset */
- autoc = hw->mac.autoc_read(hw);
-
+ if (hw->mac.type == txgbe_mac_raptor) {
+ /* remember AUTOC from before we reset */
+ autoc = hw->mac.autoc_read(hw);
+ }
mac_reset_top:
/* Do LAN reset, the MNG domain will not be reset. */
wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
@@ -3629,16 +3656,28 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw)
goto mac_reset_top;
}
- /*
- * Store the original AUTOC/AUTOC2 values if they have not been
- * stored off yet. Otherwise restore the stored original
- * values since the reset operation sets back to defaults.
- */
- if (!hw->mac.orig_link_settings_stored) {
- hw->mac.orig_autoc = hw->mac.autoc_read(hw);
- hw->mac.orig_link_settings_stored = true;
+ /* amlite TODO*/
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) {
+ wr32(hw, TXGBE_LINKUP_FILTER, 30);
+ wr32m(hw, TXGBE_MAC_MISC_CTL, TXGBE_MAC_MISC_LINK_STS_MOD,
+ TXGBE_LINK_BOTH_PCS_MAC);
+ /* amlite: bme */
+ wr32(hw, TXGBE_PX_PF_BME, TXGBE_PX_PF_BME_EN);
+ /* amlite: rdm_rsc_ctl_free_ctl set to 1 */
+ wr32m(hw, TXGBE_RDM_RSC_CTL, TXGBE_RDM_RSC_CTL_FREE_CTL,
+ TXGBE_RDM_RSC_CTL_FREE_CTL);
} else {
- hw->mac.orig_autoc = autoc;
+ /*
+ * Store the original AUTOC/AUTOC2 values if they have not been
+ * stored off yet. Otherwise restore the stored original
+ * values since the reset operation sets back to defaults.
+ */
+ if (!hw->mac.orig_link_settings_stored) {
+ hw->mac.orig_autoc = hw->mac.autoc_read(hw);
+ hw->mac.orig_link_settings_stored = true;
+ } else {
+ hw->mac.orig_autoc = autoc;
+ }
}
if (hw->phy.ffe_set) {
@@ -3646,7 +3685,8 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw)
msec_delay(50);
/* A temporary solution to set phy */
- txgbe_set_phy_temp(hw);
+ if (hw->mac.type == txgbe_mac_raptor)
+ txgbe_set_phy_temp(hw);
}
/* Store the permanent mac address */
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index 7830abac7b..e24bd1eb03 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -1236,6 +1236,8 @@ enum txgbe_5tuple_protocol {
TXGBE_ICRMISC_LNKUP)
#define TXGBE_ICSMISC 0x000104
#define TXGBE_IENMISC 0x000108
+#define TXGBE_PX_PF_BME 0x0004B8
+#define TXGBE_PX_PF_BME_EN MS(0, 0x1)
#define TXGBE_IVARMISC 0x0004FC
#define TXGBE_IVARMISC_VEC(v) LS(v, 0, 0x7)
#define TXGBE_IVARMISC_VLD MS(7, 0x1)
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 08/15] net/txgbe: add MAC reconfiguration to avoid packet loss
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (6 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 07/15] net/txgbe: add hardware reset change " Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 09/15] net/txgbe: add TX head Write-Back mode for Amber-Lite NICs Zaiyu Wang
` (6 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
There was a bug that RX will lose the first packet when down/up port.
When PHY is configured, mac error code is reported to the MAC layer,
and MAC locked this status without unlocking. As a result, when the
first packet is reveived, MAC reports this error code and RDB dismissed
this packet.
Do MAC reset can clean MAC error code so we can fix this bug.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_hw.c | 37 +++++++++++++++++++++++++++++
drivers/net/txgbe/base/txgbe_hw.h | 1 +
drivers/net/txgbe/base/txgbe_regs.h | 2 ++
drivers/net/txgbe/txgbe_ethdev.c | 1 +
4 files changed, 41 insertions(+)
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index f82bbee6f0..4f93c28280 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -3497,6 +3497,43 @@ txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
return err;
}
+int txgbe_reconfig_mac(struct txgbe_hw *hw)
+{
+ u32 mac_wdg_timeout;
+ u32 mac_flow_ctrl;
+
+ mac_wdg_timeout = rd32(hw, TXGBE_MAC_WDG_TIMEOUT);
+ mac_flow_ctrl = rd32(hw, TXGBE_RXFCCFG);
+
+ if (hw->bus.lan_id == 0)
+ wr32(hw, TXGBE_RST, TXGBE_RST_MAC_LAN_0);
+ else if (hw->bus.lan_id == 1)
+ wr32(hw, TXGBE_RST, TXGBE_RST_MAC_LAN_1);
+
+ /* wait for mac reset complete */
+ usec_delay(1500);
+ wr32m(hw, TXGBE_MAC_MISC_CTL, TXGBE_MAC_MISC_LINK_STS_MOD,
+ TXGBE_LINK_BOTH_PCS_MAC);
+
+ /* receive packets that size > 2048 */
+ wr32m(hw, TXGBE_MACRXCFG,
+ TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
+
+ /* clear counters on read */
+ wr32m(hw, TXGBE_MACCNTCTL,
+ TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
+
+ wr32m(hw, TXGBE_RXFCCFG,
+ TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
+
+ wr32(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_PROMISC);
+
+ wr32(hw, TXGBE_MAC_WDG_TIMEOUT, mac_wdg_timeout);
+ wr32(hw, TXGBE_RXFCCFG, mac_flow_ctrl);
+
+ return 0;
+}
+
static void
txgbe_reset_misc(struct txgbe_hw *hw)
{
diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h
index a7e9547430..1356878575 100644
--- a/drivers/net/txgbe/base/txgbe_hw.h
+++ b/drivers/net/txgbe/base/txgbe_hw.h
@@ -107,6 +107,7 @@ s32 txgbe_setup_mac_link(struct txgbe_hw *hw, u32 speed,
bool autoneg_wait_to_complete);
s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw);
void txgbe_init_mac_link_ops_sp(struct txgbe_hw *hw);
+int txgbe_reconfig_mac(struct txgbe_hw *hw);
s32 txgbe_reset_hw(struct txgbe_hw *hw);
s32 txgbe_start_hw_raptor(struct txgbe_hw *hw);
s32 txgbe_init_phy_raptor(struct txgbe_hw *hw);
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index e24bd1eb03..7ee7712e53 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -158,6 +158,8 @@
#define TXGBE_RST_SW MS(0, 0x1)
#define TXGBE_RST_LAN(i) MS(((i) + 1), 0x1)
#define TXGBE_RST_FW MS(3, 0x1)
+#define TXGBE_RST_MAC_LAN_1 MS(17, 0x1)
+#define TXGBE_RST_MAC_LAN_0 MS(20, 0x1)
#define TXGBE_RST_ETH(i) MS(((i) + 29), 0x1)
#define TXGBE_RST_GLB MS(31, 0x1)
#define TXGBE_RST_DEFAULT (TXGBE_RST_SW | \
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index cba1e8f2a7..a854b40b9f 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -3081,6 +3081,7 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev,
/* enable mac receiver */
if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) {
+ txgbe_reconfig_mac(hw);
wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
}
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 09/15] net/txgbe: add TX head Write-Back mode for Amber-Lite NICs
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (7 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 08/15] net/txgbe: add MAC reconfiguration to avoid packet loss Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 10/15] net/txgbe: add RX desc merge " Zaiyu Wang
` (5 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Add TX head Write-Back mode for Amber-Lite NICs. When enabled, the
hardware no longer individually rewrites descriptors but intermittently
notifies the driver of processed descriptor indices. This feature
significantly improves performance and is enabled by default in the
driver. Users can configure it via tx_headwb and tx_headwb_size in devargs.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_regs.h | 7 ++
drivers/net/txgbe/base/txgbe_type.h | 6 ++
drivers/net/txgbe/txgbe_ethdev.c | 9 ++
drivers/net/txgbe/txgbe_rxtx.c | 126 ++++++++++++++++++----
drivers/net/txgbe/txgbe_rxtx.h | 3 +
drivers/net/txgbe/txgbe_rxtx_vec_common.h | 27 +++--
6 files changed, 151 insertions(+), 27 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index 7ee7712e53..17257442f3 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -1402,6 +1402,13 @@ enum txgbe_5tuple_protocol {
#define TXGBE_TXCFG_WTHRESH_MASK_AML MS(16, 0x1FF)
#define TXGBE_TXCFG_WTHRESH(v) LS(v, 16, 0x7F)
#define TXGBE_TXCFG_FLUSH MS(26, 0x1)
+#define TXGBE_PX_TR_CFG_HEAD_WB MS(27, 0x1) /* amlite head wb */
+#define TXGBE_PX_TR_CFG_HEAD_WB_64BYTE MS(28, 0x1) /* amlite head wb 64byte */
+#define TXGBE_PX_TR_CFG_HEAD_WB_MASK MS(27, 0x3)
+
+/* amlite: tx head wb */
+#define TXGBE_PX_TR_HEAD_ADDRL(_i) (0x03028 + ((_i) * 0x40))
+#define TXGBE_PX_TR_HEAD_ADDRH(_i) (0x0302C + ((_i) * 0x40))
#define TXGBE_TDM_DESC_CHK(i) (0x0180B0 + (i) * 4) /*0-3*/
#define TXGBE_TDM_DESC_NONFATAL(i) (0x0180C0 + (i) * 4) /*0-3*/
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 8005283a26..5692883f60 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -723,6 +723,8 @@ struct txgbe_phy_info {
#define TXGBE_DEVARG_FFE_MAIN "ffe_main"
#define TXGBE_DEVARG_FFE_PRE "ffe_pre"
#define TXGBE_DEVARG_FFE_POST "ffe_post"
+#define TXGBE_DEVARG_TX_HEAD_WB "tx_headwb"
+#define TXGBE_DEVARG_TX_HEAD_WB_SIZE "tx_headwb_size"
static const char * const txgbe_valid_arguments[] = {
TXGBE_DEVARG_BP_AUTO,
@@ -733,6 +735,8 @@ static const char * const txgbe_valid_arguments[] = {
TXGBE_DEVARG_FFE_MAIN,
TXGBE_DEVARG_FFE_PRE,
TXGBE_DEVARG_FFE_POST,
+ TXGBE_DEVARG_TX_HEAD_WB,
+ TXGBE_DEVARG_TX_HEAD_WB_SIZE,
NULL
};
@@ -783,6 +787,8 @@ struct txgbe_devargs {
u16 poll;
u16 present;
u16 sgmii;
+ u16 tx_headwb;
+ u16 tx_headwb_size;
};
struct txgbe_hw {
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index a854b40b9f..ed84594105 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -513,6 +513,9 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
u16 ffe_main = 27;
u16 ffe_pre = 8;
u16 ffe_post = 44;
+ /* New devargs for amberlite config */
+ u16 tx_headwb = 1;
+ u16 tx_headwb_size = 16;
if (devargs == NULL)
goto null;
@@ -537,6 +540,10 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
&txgbe_handle_devarg, &ffe_pre);
rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST,
&txgbe_handle_devarg, &ffe_post);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_TX_HEAD_WB,
+ &txgbe_handle_devarg, &tx_headwb);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_TX_HEAD_WB_SIZE,
+ &txgbe_handle_devarg, &tx_headwb_size);
rte_kvargs_free(kvlist);
null:
@@ -544,6 +551,8 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
hw->devarg.poll = poll;
hw->devarg.present = present;
hw->devarg.sgmii = sgmii;
+ hw->devarg.tx_headwb = tx_headwb;
+ hw->devarg.tx_headwb_size = tx_headwb_size;
hw->phy.ffe_set = ffe_set;
hw->phy.ffe_main = ffe_main;
hw->phy.ffe_pre = ffe_pre;
diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c
index 558ffbf73f..9846ce3c56 100644
--- a/drivers/net/txgbe/txgbe_rxtx.c
+++ b/drivers/net/txgbe/txgbe_rxtx.c
@@ -92,14 +92,29 @@ txgbe_tx_free_bufs(struct txgbe_tx_queue *txq)
int i, nb_free = 0;
struct rte_mbuf *m, *free[RTE_TXGBE_TX_MAX_FREE_BUF_SZ];
- /* check DD bit on threshold descriptor */
- status = txq->tx_ring[txq->tx_next_dd].dw3;
- if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) {
- if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
- txgbe_set32_masked(txq->tdc_reg_addr,
- TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH);
- return 0;
- }
+ if (txq->headwb_mem) {
+ uint16_t tx_last_dd = txq->nb_tx_desc +
+ txq->tx_next_dd - txq->tx_free_thresh;
+ if (tx_last_dd >= txq->nb_tx_desc)
+ tx_last_dd -= txq->nb_tx_desc;
+
+ volatile uint16_t head = (uint16_t)*(txq->headwb_mem);
+
+ if (txq->tx_next_dd > head && head > tx_last_dd)
+ return 0;
+ else if (tx_last_dd > txq->tx_next_dd &&
+ (head > tx_last_dd || head < txq->tx_next_dd))
+ return 0;
+ } else {
+ /* check DD bit on threshold descriptor */
+ status = txq->tx_ring[txq->tx_next_dd].dw3;
+ if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) {
+ if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
+ txgbe_set32_masked(txq->tdc_reg_addr,
+ TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH);
+ return 0;
+ }
+}
/*
* first buffer to free from S/W ring is at index
@@ -628,17 +643,28 @@ txgbe_xmit_cleanup(struct txgbe_tx_queue *txq)
/* Check to make sure the last descriptor to clean is done */
desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
status = txr[desc_to_clean_to].dw3;
- if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) {
- PMD_TX_FREE_LOG(DEBUG,
- "TX descriptor %4u is not done"
- "(port=%d queue=%d)",
- desc_to_clean_to,
- txq->port_id, txq->queue_id);
- if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
- txgbe_set32_masked(txq->tdc_reg_addr,
- TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH);
- /* Failed to clean any descriptors, better luck next time */
- return -(1);
+
+ if (txq->headwb_mem) {
+ u32 head = *(txq->headwb_mem);
+
+ PMD_TX_FREE_LOG(DEBUG, "queue[%02d]: headwb_mem = %03d, desc_to_clean_to = %03d",
+ txq->reg_idx, head, desc_to_clean_to);
+ /* we have caught up to head, no work left to do */
+ if (desc_to_clean_to == head)
+ return -(1);
+ } else {
+ if (!(status & rte_cpu_to_le_32(TXGBE_TXD_DD))) {
+ PMD_TX_FREE_LOG(DEBUG,
+ "TX descriptor %4u is not done"
+ "(port=%d queue=%d)",
+ desc_to_clean_to,
+ txq->port_id, txq->queue_id);
+ if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
+ txgbe_set32_masked(txq->tdc_reg_addr,
+ TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH);
+ /* Failed to clean any descriptors, better luck next time */
+ return -(1);
+ }
}
/* Figure out how many descriptors will be cleaned */
@@ -2244,6 +2270,8 @@ txgbe_tx_queue_release(struct txgbe_tx_queue *txq)
txq->ops->release_mbufs(txq);
txq->ops->free_swring(txq);
rte_memzone_free(txq->mz);
+ if (txq->headwb_mem)
+ rte_memzone_free(txq->headwb);
rte_free(txq);
}
}
@@ -2380,6 +2408,43 @@ txgbe_get_tx_port_offloads(struct rte_eth_dev *dev)
return tx_offload_capa;
}
+static int
+txgbe_setup_headwb_resources(struct rte_eth_dev *dev,
+ void *tx_queue,
+ unsigned int socket_id)
+{
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+ const struct rte_memzone *headwb;
+ struct txgbe_tx_queue *txq = tx_queue;
+ u8 i, headwb_size = 0;
+
+ if (hw->mac.type != txgbe_mac_aml && hw->mac.type != txgbe_mac_aml40) {
+ txq->headwb_mem = NULL;
+ return 0;
+ }
+
+ headwb_size = hw->devarg.tx_headwb_size;
+ headwb = rte_eth_dma_zone_reserve(dev, "tx_headwb_mem", txq->queue_id,
+ sizeof(u32) * headwb_size,
+ TXGBE_ALIGN, socket_id);//amlite-to-do: align?
+
+ if (headwb == NULL) {
+ DEBUGOUT("Fail to setup headwb resources: no mem");
+ txgbe_tx_queue_release(txq);
+ return -ENOMEM;
+ }
+
+ txq->headwb = headwb;
+ txq->headwb_dma = TMZ_PADDR(headwb);
+ txq->headwb_mem = (uint32_t *) TMZ_VADDR(headwb);
+
+ /* Zero out headwb_mem memory */
+ for (i = 0; i < headwb_size; i++)
+ txq->headwb_mem[i] = 0;
+
+ return 0;
+}
+
int __rte_cold
txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
uint16_t queue_idx,
@@ -2392,6 +2457,7 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
struct txgbe_hw *hw;
uint16_t tx_free_thresh;
uint64_t offloads;
+ s32 err = 0;
PMD_INIT_FUNC_TRACE();
hw = TXGBE_DEV_HW(dev);
@@ -2511,12 +2577,15 @@ txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
/* set up scalar TX function as appropriate */
txgbe_set_tx_function(dev, txq);
+ if (hw->devarg.tx_headwb)
+ err = txgbe_setup_headwb_resources(dev, txq, socket_id);
+
txq->ops->reset(txq);
txq->desc_error = 0;
dev->data->tx_queues[queue_idx] = txq;
- return 0;
+ return err;
}
/**
@@ -4658,6 +4727,23 @@ txgbe_dev_tx_init(struct rte_eth_dev *dev)
/* Setup the HW Tx Head and TX Tail descriptor pointers */
wr32(hw, TXGBE_TXRP(txq->reg_idx), 0);
wr32(hw, TXGBE_TXWP(txq->reg_idx), 0);
+
+ if ((hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) &&
+ hw->devarg.tx_headwb) {
+ uint32_t txdctl;
+
+ wr32(hw, TXGBE_PX_TR_HEAD_ADDRL(txq->reg_idx),
+ (uint32_t)(txq->headwb_dma & BIT_MASK32));
+ wr32(hw, TXGBE_PX_TR_HEAD_ADDRH(txq->reg_idx),
+ (uint32_t)(txq->headwb_dma >> 32));
+ if (hw->devarg.tx_headwb_size == 16)
+ txdctl = TXGBE_PX_TR_CFG_HEAD_WB |
+ TXGBE_PX_TR_CFG_HEAD_WB_64BYTE;
+ else
+ txdctl = TXGBE_PX_TR_CFG_HEAD_WB;
+ wr32m(hw, TXGBE_TXCFG(txq->reg_idx),
+ TXGBE_PX_TR_CFG_HEAD_WB_MASK, txdctl);
+ }
}
#ifndef RTE_LIB_SECURITY
diff --git a/drivers/net/txgbe/txgbe_rxtx.h b/drivers/net/txgbe/txgbe_rxtx.h
index 622a0d3981..b1ac03576f 100644
--- a/drivers/net/txgbe/txgbe_rxtx.h
+++ b/drivers/net/txgbe/txgbe_rxtx.h
@@ -414,6 +414,9 @@ struct txgbe_tx_queue {
const struct rte_memzone *mz;
uint64_t desc_error;
bool resetting;
+ const struct rte_memzone *headwb;
+ uint64_t headwb_dma;
+ volatile uint32_t *headwb_mem;
};
struct txgbe_txq_ops {
diff --git a/drivers/net/txgbe/txgbe_rxtx_vec_common.h b/drivers/net/txgbe/txgbe_rxtx_vec_common.h
index cf67df66d8..5d75951115 100644
--- a/drivers/net/txgbe/txgbe_rxtx_vec_common.h
+++ b/drivers/net/txgbe/txgbe_rxtx_vec_common.h
@@ -89,13 +89,26 @@ txgbe_tx_free_bufs(struct txgbe_tx_queue *txq)
int nb_free = 0;
struct rte_mbuf *m, *free[RTE_TXGBE_TX_MAX_FREE_BUF_SZ];
- /* check DD bit on threshold descriptor */
- status = txq->tx_ring[txq->tx_next_dd].dw3;
- if (!(status & TXGBE_TXD_DD)) {
- if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
- txgbe_set32_masked(txq->tdc_reg_addr,
- TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH);
- return 0;
+ if (txq->headwb_mem) {
+ uint16_t tx_last_dd = txq->nb_tx_desc +
+ txq->tx_next_dd - txq->tx_free_thresh;
+ if (tx_last_dd >= txq->nb_tx_desc)
+ tx_last_dd -= txq->nb_tx_desc;
+ volatile uint16_t head = (uint16_t)*(txq->headwb_mem);
+ if (txq->tx_next_dd > head && head > tx_last_dd)
+ return 0;
+ else if (tx_last_dd > txq->tx_next_dd &&
+ (head > tx_last_dd || head < txq->tx_next_dd))
+ return 0;
+ } else {
+ /* check DD bit on threshold descriptor */
+ status = txq->tx_ring[txq->tx_next_dd].dw3;
+ if (!(status & TXGBE_TXD_DD)) {
+ if (txq->nb_tx_free >> 1 < txq->tx_free_thresh)
+ txgbe_set32_masked(txq->tdc_reg_addr,
+ TXGBE_TXCFG_FLUSH, TXGBE_TXCFG_FLUSH);
+ return 0;
+ }
}
n = txq->tx_free_thresh;
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 10/15] net/txgbe: add RX desc merge mode for Amber-Lite NICs
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (8 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 09/15] net/txgbe: add TX head Write-Back mode for Amber-Lite NICs Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 11/15] net/txgbe: add FEC support for Amber-Lite 25G NICs Zaiyu Wang
` (4 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Add RX desc merge mode for Amber-Lite NICs. When enabled,
the hardware batch-processes RX packets, significantly
enhancing performance. This feature is enabled by default
in the driver and can be configured via the rx_desc_merge
parameter in devargs.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_regs.h | 4 ++++
drivers/net/txgbe/base/txgbe_type.h | 3 +++
drivers/net/txgbe/txgbe_ethdev.c | 4 ++++
drivers/net/txgbe/txgbe_rxtx.c | 11 +++++++++++
4 files changed, 22 insertions(+)
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index 17257442f3..86f88e31fe 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -1373,6 +1373,7 @@ enum txgbe_5tuple_protocol {
#define TXGBE_RXCFG_HDRLEN(v) LS(HDRLEN(v), 12, 0xF)
#define TXGBE_RXCFG_HDRLEN_MASK MS(12, 0xF)
#define TXGBE_RXCFG_WTHRESH(v) LS(v, 16, 0x7)
+#define TXGBE_RXCFG_DESC_MERGE MS(19, 0x1)
#define TXGBE_RXCFG_ETAG MS(22, 0x1)
#define TXGBE_RXCFG_RSCMAX_MASK MS(23, 0x3)
#define TXGBE_RXCFG_RSCMAX_1 LS(0, 23, 0x3)
@@ -1666,6 +1667,9 @@ enum txgbe_5tuple_protocol {
#define TXGBE_RPUP2TC_UP_SHIFT 3
#define TXGBE_RPUP2TC_UP_MASK 0x7
+#define TXGBE_RDM_DCACHE_CTL 0x0120A8
+#define TXGBE_RDM_DCACHE_CTL_EN MS(0, 0x1)
+
/* mac switcher */
#define TXGBE_ETHADDRL 0x016200
#define TXGBE_ETHADDRL_AD0(v) LS(v, 0, 0xFF)
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 5692883f60..ba961b4b1e 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -725,6 +725,7 @@ struct txgbe_phy_info {
#define TXGBE_DEVARG_FFE_POST "ffe_post"
#define TXGBE_DEVARG_TX_HEAD_WB "tx_headwb"
#define TXGBE_DEVARG_TX_HEAD_WB_SIZE "tx_headwb_size"
+#define TXGBE_DEVARG_RX_DESC_MERGE "rx_desc_merge"
static const char * const txgbe_valid_arguments[] = {
TXGBE_DEVARG_BP_AUTO,
@@ -737,6 +738,7 @@ static const char * const txgbe_valid_arguments[] = {
TXGBE_DEVARG_FFE_POST,
TXGBE_DEVARG_TX_HEAD_WB,
TXGBE_DEVARG_TX_HEAD_WB_SIZE,
+ TXGBE_DEVARG_RX_DESC_MERGE,
NULL
};
@@ -789,6 +791,7 @@ struct txgbe_devargs {
u16 sgmii;
u16 tx_headwb;
u16 tx_headwb_size;
+ u16 rx_desc_merge;
};
struct txgbe_hw {
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index ed84594105..fffb8fb01d 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -516,6 +516,7 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
/* New devargs for amberlite config */
u16 tx_headwb = 1;
u16 tx_headwb_size = 16;
+ u16 rx_desc_merge = 1;
if (devargs == NULL)
goto null;
@@ -544,6 +545,8 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
&txgbe_handle_devarg, &tx_headwb);
rte_kvargs_process(kvlist, TXGBE_DEVARG_TX_HEAD_WB_SIZE,
&txgbe_handle_devarg, &tx_headwb_size);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_RX_DESC_MERGE,
+ &txgbe_handle_devarg, &rx_desc_merge);
rte_kvargs_free(kvlist);
null:
@@ -553,6 +556,7 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
hw->devarg.sgmii = sgmii;
hw->devarg.tx_headwb = tx_headwb;
hw->devarg.tx_headwb_size = tx_headwb_size;
+ hw->devarg.rx_desc_merge = rx_desc_merge;
hw->phy.ffe_set = ffe_set;
hw->phy.ffe_main = ffe_main;
hw->phy.ffe_pre = ffe_pre;
diff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c
index 9846ce3c56..fe3206d797 100644
--- a/drivers/net/txgbe/txgbe_rxtx.c
+++ b/drivers/net/txgbe/txgbe_rxtx.c
@@ -4649,6 +4649,17 @@ txgbe_dev_rx_init(struct rte_eth_dev *dev)
buf_size = ROUND_DOWN(buf_size, 0x1 << 10);
srrctl |= TXGBE_RXCFG_PKTLEN(buf_size);
+ if ((hw->mac.type == txgbe_mac_aml ||
+ hw->mac.type == txgbe_mac_aml40) && hw->devarg.rx_desc_merge == 1) {
+ srrctl |= TXGBE_RXCFG_DESC_MERGE;
+
+ wr32(hw, TXGBE_RDM_DCACHE_CTL, TXGBE_RDM_DCACHE_CTL_EN);
+ wr32m(hw, TXGBE_RDM_RSC_CTL, TXGBE_RDM_RSC_CTL_FREE_CTL,
+ TXGBE_RDM_RSC_CTL_FREE_CTL);
+ wr32m(hw, TXGBE_RDM_RSC_CTL, TXGBE_RDM_RSC_CTL_FREE_CNT_DIS,
+ ~TXGBE_RDM_RSC_CTL_FREE_CNT_DIS);
+ }
+
wr32(hw, TXGBE_RXCFG(rxq->reg_idx), srrctl);
/* It adds dual VLAN length for supporting dual VLAN */
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 11/15] net/txgbe: add FEC support for Amber-Lite 25G NICs
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (9 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 10/15] net/txgbe: add RX desc merge " Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 12/15] net/txgbe: add GPIO configuration Zaiyu Wang
` (3 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Amber-Lite 25G NICs support four FEC modes (off, baser, rs, auto).
The driver implements standard interfaces (fec_get_capability,
fec_get, fec_set) to allow manual configuration. The default FEC
mode is set to 'auto'.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_aml.c | 27 ++++++-
drivers/net/txgbe/base/txgbe_hw.c | 3 +
drivers/net/txgbe/base/txgbe_mng.c | 2 +-
drivers/net/txgbe/base/txgbe_phy.h | 1 +
drivers/net/txgbe/base/txgbe_type.h | 2 +
drivers/net/txgbe/txgbe_ethdev.c | 121 ++++++++++++++++++++++++++++
6 files changed, 154 insertions(+), 2 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_aml.c b/drivers/net/txgbe/base/txgbe_aml.c
index 368b002c88..4cafdeca5c 100644
--- a/drivers/net/txgbe/base/txgbe_aml.c
+++ b/drivers/net/txgbe/base/txgbe_aml.c
@@ -131,6 +131,26 @@ u32 txgbe_get_media_type_aml(struct txgbe_hw *hw)
return media_type;
}
+static int
+txgbe_phy_fec_get(struct txgbe_hw *hw)
+{
+ int value = 0;
+
+ rte_spinlock_lock(&hw->phy_lock);
+ value = rd32_epcs(hw, SR_PMA_RS_FEC_CTRL);
+ rte_spinlock_unlock(&hw->phy_lock);
+ if (value & 0x4)
+ return TXGBE_PHY_FEC_RS;
+
+ rte_spinlock_lock(&hw->phy_lock);
+ value = rd32_epcs(hw, SR_PMA_KR_FEC_CTRL);
+ rte_spinlock_unlock(&hw->phy_lock);
+ if (value & 0x1)
+ return TXGBE_PHY_FEC_BASER;
+
+ return TXGBE_PHY_FEC_OFF;
+}
+
void txgbe_wait_for_link_up_aml(struct txgbe_hw *hw, u32 speed)
{
u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
@@ -184,7 +204,12 @@ s32 txgbe_setup_mac_link_aml(struct txgbe_hw *hw,
status = hw->mac.check_link(hw, &link_speed, &link_up,
autoneg_wait_to_complete);
- if (link_speed == speed && link_up)
+ if (link_up && speed == TXGBE_LINK_SPEED_25GB_FULL)
+ hw->cur_fec_link = txgbe_phy_fec_get(hw);
+
+ if (link_speed == speed && link_up &&
+ !(speed == TXGBE_LINK_SPEED_25GB_FULL &&
+ !(hw->fec_mode & hw->cur_fec_link)))
return status;
if (speed & TXGBE_LINK_SPEED_25GB_FULL)
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 4f93c28280..fd6594e831 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -329,6 +329,9 @@ s32 txgbe_init_hw(struct txgbe_hw *hw)
txgbe_disable_lldp(hw);
+ /* Init fec mode to 'AUTO' */
+ hw->fec_mode = TXGBE_PHY_FEC_AUTO;
+
/* Reset the hardware */
status = hw->mac.reset_hw(hw);
if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
diff --git a/drivers/net/txgbe/base/txgbe_mng.c b/drivers/net/txgbe/base/txgbe_mng.c
index 7af43c7b44..28b5ed3542 100644
--- a/drivers/net/txgbe/base/txgbe_mng.c
+++ b/drivers/net/txgbe/base/txgbe_mng.c
@@ -601,7 +601,7 @@ s32 txgbe_hic_ephy_set_link(struct txgbe_hw *hw, u8 speed, u8 autoneg, u8 duplex
buffer.hdr.buf_len = sizeof(struct txgbe_hic_ephy_setlink) - sizeof(struct txgbe_hic_hdr);
buffer.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
- buffer.fec_mode = TXGBE_PHY_FEC_AUTO;
+ buffer.fec_mode = hw->fec_mode;
buffer.speed = speed;
buffer.autoneg = autoneg;
buffer.duplex = duplex;
diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h
index 79b866ea57..94788464c2 100644
--- a/drivers/net/txgbe/base/txgbe_phy.h
+++ b/drivers/net/txgbe/base/txgbe_phy.h
@@ -40,6 +40,7 @@
#define SR_PMA_KR_LD_CESTS_RR MS16(15, 0x1)
#define SR_PMA_KR_FEC_CTRL 0x0100AB
#define SR_PMA_KR_FEC_CTRL_EN MS16(0, 0x1)
+#define SR_PMA_RS_FEC_CTRL 0x0100C8
#define SR_MII_MMD_CTL 0x1F0000
#define SR_MII_MMD_CTL_AN_EN 0x1000
#define SR_MII_MMD_CTL_RESTART_AN 0x0200
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index ba961b4b1e..3833f1420a 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -855,6 +855,8 @@ struct txgbe_hw {
/*amlite: new SW-FW mbox */
u8 swfw_index;
rte_atomic32_t swfw_busy;
+ u32 fec_mode;
+ u32 cur_fec_link;
};
struct txgbe_backplane_ability {
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index fffb8fb01d..374d6452f4 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -2805,9 +2805,31 @@ txgbe_dev_detect_sfp(void *param)
{
struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+ u32 value = 0;
s32 err;
+ if (hw->mac.type == txgbe_mac_aml40) {
+ value = rd32(hw, TXGBE_GPIOEXT);
+ if (value & TXGBE_SFP1_MOD_PRST_LS) {
+ err = TXGBE_ERR_SFP_NOT_PRESENT;
+ goto out;
+ }
+ }
+
+ if (hw->mac.type == txgbe_mac_aml) {
+ value = rd32(hw, TXGBE_GPIOEXT);
+ if (value & TXGBE_SFP1_MOD_ABS_LS) {
+ err = TXGBE_ERR_SFP_NOT_PRESENT;
+ goto out;
+ }
+ }
+
+ /* wait for sfp module ready*/
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
+ msec_delay(200);
+
err = hw->phy.identify_sfp(hw);
+out:
if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
PMD_DRV_LOG(ERR, "Unsupported SFP+ module type was detected.");
} else if (err == TXGBE_ERR_SFP_NOT_PRESENT) {
@@ -5632,6 +5654,102 @@ txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
return 0;
}
+static int txgbe_fec_get_capa_speed_to_fec(struct rte_eth_fec_capa *speed_fec_capa)
+{
+ int num = 2;
+
+ if (speed_fec_capa) {
+ speed_fec_capa[0].speed = RTE_ETH_SPEED_NUM_10G;
+ speed_fec_capa[0].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
+ speed_fec_capa[1].speed = RTE_ETH_SPEED_NUM_25G;
+ speed_fec_capa[1].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
+ RTE_ETH_FEC_MODE_CAPA_MASK(RS);
+ }
+
+ return num;
+}
+
+static int txgbe_fec_get_capability(struct rte_eth_dev *dev,
+ struct rte_eth_fec_capa *speed_fec_capa,
+ unsigned int num)
+{
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+ u8 num_entries;
+
+ if (hw->mac.type != txgbe_mac_aml)
+ return -EOPNOTSUPP;
+
+ num_entries = txgbe_fec_get_capa_speed_to_fec(NULL);
+ if (!speed_fec_capa || num < num_entries)
+ return num_entries;
+
+ return txgbe_fec_get_capa_speed_to_fec(speed_fec_capa);
+}
+
+static int txgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
+{
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+ u32 speed = 0;
+ bool negotiate = false;
+ u32 curr_fec_mode;
+
+ hw->mac.get_link_capabilities(hw, &speed, &negotiate);
+
+ if (hw->mac.type != txgbe_mac_aml ||
+ !(speed & TXGBE_LINK_SPEED_25GB_FULL))
+ return -EOPNOTSUPP;
+
+ if (hw->fec_mode == TXGBE_PHY_FEC_AUTO)
+ curr_fec_mode = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
+ else if (hw->fec_mode == TXGBE_PHY_FEC_RS)
+ curr_fec_mode = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
+ else if (hw->fec_mode == TXGBE_PHY_FEC_BASER)
+ curr_fec_mode = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
+ else
+ curr_fec_mode = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
+
+ *fec_capa = curr_fec_mode;
+ return 0;
+}
+
+static int txgbe_fec_set(struct rte_eth_dev *dev, u32 fec_capa)
+{
+ struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+ u32 orig_fec_mode = hw->fec_mode;
+ bool negotiate = false;
+ u32 speed = 0;
+
+ hw->mac.get_link_capabilities(hw, &speed, &negotiate);
+
+ if (hw->mac.type != txgbe_mac_aml ||
+ !(speed & TXGBE_LINK_SPEED_25GB_FULL))
+ return -EOPNOTSUPP;
+
+ if (!fec_capa)
+ return -EINVAL;
+
+ if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO))
+ hw->fec_mode = TXGBE_PHY_FEC_AUTO;
+
+ if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC))
+ hw->fec_mode = TXGBE_PHY_FEC_OFF;
+
+ if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER))
+ hw->fec_mode = TXGBE_PHY_FEC_BASER;
+
+ if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS))
+ hw->fec_mode = TXGBE_PHY_FEC_RS;
+
+ if (hw->fec_mode != orig_fec_mode) {
+ txgbe_dev_setup_link_alarm_handler(dev);
+ txgbe_dev_link_update(dev, 0);
+ }
+
+ return 0;
+}
+
static const struct eth_dev_ops txgbe_eth_dev_ops = {
.dev_configure = txgbe_dev_configure,
.dev_infos_get = txgbe_dev_info_get,
@@ -5708,6 +5826,9 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = {
.udp_tunnel_port_del = txgbe_dev_udp_tunnel_port_del,
.tm_ops_get = txgbe_tm_ops_get,
.tx_done_cleanup = txgbe_dev_tx_done_cleanup,
+ .fec_get_capability = txgbe_fec_get_capability,
+ .fec_get = txgbe_fec_get,
+ .fec_set = txgbe_fec_set,
};
RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 12/15] net/txgbe: add GPIO configuration
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (10 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 11/15] net/txgbe: add FEC support for Amber-Lite 25G NICs Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 13/15] net/txgbe: disable unstable features Zaiyu Wang
` (2 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Add GPIO configuration for Amber-Lite NICs to match design differences
from 10G NICs: The Amber-Lite NIC requires additional setup steps
compared to 10G NICs to ensure proper functionality of features
SFP module detection.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_regs.h | 2 +
drivers/net/txgbe/txgbe_ethdev.c | 111 ++++++++++++++++++++++++++++
2 files changed, 113 insertions(+)
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index 86f88e31fe..98d1070daa 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -1626,6 +1626,8 @@ enum txgbe_5tuple_protocol {
#define TXGBE_GPIOINTEN 0x014830
#define TXGBE_GPIOINTMASK 0x014834
#define TXGBE_GPIOINTTYPE 0x014838
+#define TXGBE_GPIO_INT_POLARITY 0x01483C
+#define TXGBE_GPIO_INT_POLARITY_3 MS(3, 0x1)
#define TXGBE_GPIOINTSTAT 0x014840
#define TXGBE_GPIORAWINTSTAT 0x014844
#define TXGBE_GPIOEOI 0x01484C
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 374d6452f4..9fd4923b6d 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -353,11 +353,33 @@ txgbe_enable_intr(struct rte_eth_dev *dev)
{
struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
+ uint32_t gpie;
wr32(hw, TXGBE_IENMISC, intr->mask_misc);
wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
txgbe_flush(hw);
+
+ /* To avoid gpio intr lost, enable pcie intr first. Then enable gpio intr. */
+ if (hw->mac.type == txgbe_mac_aml) {
+ gpie = rd32(hw, TXGBE_GPIOINTEN);
+ gpie |= TXGBE_GPIOBIT_2 | TXGBE_GPIOBIT_3 | TXGBE_GPIOBIT_6;
+ wr32(hw, TXGBE_GPIOINTEN, gpie);
+
+ gpie = rd32(hw, TXGBE_GPIOINTTYPE);
+ gpie |= TXGBE_GPIOBIT_2 | TXGBE_GPIOBIT_3 | TXGBE_GPIOBIT_6;
+ wr32(hw, TXGBE_GPIOINTTYPE, gpie);
+ }
+
+ if (hw->mac.type == txgbe_mac_aml40) {
+ gpie = rd32(hw, TXGBE_GPIOINTEN);
+ gpie |= TXGBE_GPIOBIT_4;
+ wr32(hw, TXGBE_GPIOINTEN, gpie);
+
+ gpie = rd32(hw, TXGBE_GPIOINTTYPE);
+ gpie |= TXGBE_GPIOBIT_4;
+ wr32(hw, TXGBE_GPIOINTTYPE, gpie);
+ }
}
static void
@@ -1711,6 +1733,7 @@ txgbe_dev_start(struct rte_eth_dev *dev)
uint16_t vf, idx;
uint32_t *link_speeds;
struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
+ u32 links_reg;
PMD_INIT_FUNC_TRACE();
@@ -1892,6 +1915,44 @@ txgbe_dev_start(struct rte_eth_dev *dev)
if (err)
goto error;
+ if (hw->mac.type == txgbe_mac_aml) {
+ links_reg = rd32(hw, TXGBE_PORT);
+ if (links_reg & TXGBE_PORT_LINKUP) {
+ if (links_reg & TXGBE_CFG_PORT_ST_AML_LINK_25G) {
+ wr32(hw, TXGBE_MACTXCFG,
+ (rd32(hw, TXGBE_MACTXCFG) &
+ ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) |
+ TXGBE_MAC_TX_CFG_AML_SPEED_25G);
+ } else if (links_reg & TXGBE_CFG_PORT_ST_AML_LINK_10G) {
+ wr32(hw, TXGBE_MACTXCFG,
+ (rd32(hw, TXGBE_MACTXCFG) &
+ ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) |
+ TXGBE_MAC_TX_CFG_AML_SPEED_10G);
+ }
+ }
+
+ /* amlite: restart gpio */
+ wr32(hw, TXGBE_GPIODIR, TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1 |
+ TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
+ wr32(hw, TXGBE_GPIODATA, TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
+ msleep(10);
+ wr32(hw, TXGBE_GPIODATA, TXGBE_GPIOBIT_0);
+ wr32m(hw, TXGBE_GPIO_INT_POLARITY, TXGBE_GPIO_INT_POLARITY_3, 0x0);
+ } else if (hw->mac.type == txgbe_mac_aml40) {
+ links_reg = rd32(hw, TXGBE_PORT);
+ if (links_reg & TXGBE_PORT_LINKUP) {
+ if (links_reg & TXGBE_CFG_PORT_ST_AML_LINK_40G) {
+ wr32(hw, TXGBE_MACTXCFG,
+ (rd32(hw, TXGBE_MACTXCFG) &
+ ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) |
+ TXGBE_MAC_TX_CFG_AML_SPEED_40G);
+ }
+ }
+
+ wr32(hw, TXGBE_GPIODIR, TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1
+ | TXGBE_GPIOBIT_3);
+ wr32(hw, TXGBE_GPIODATA, TXGBE_GPIOBIT_1);
+ }
skip_link_setup:
if (rte_intr_allow_others(intr_handle)) {
@@ -1989,6 +2050,10 @@ txgbe_dev_stop(struct rte_eth_dev *dev)
for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
vfinfo[vf].clear_to_send = false;
+ if (hw->mac.type == txgbe_mac_aml)
+ wr32m(hw, TXGBE_AML_EPCS_MISC_CTL,
+ TXGBE_AML_LINK_STATUS_OVRD_EN, 0x0);
+
txgbe_dev_clear_queues(dev);
/* Clear stored conf */
@@ -2867,6 +2932,27 @@ txgbe_dev_sfp_event(struct rte_eth_dev *dev)
intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
}
+ if (hw->mac.type == txgbe_mac_aml40) {
+ if (reg & TXGBE_GPIOBIT_4) {
+ wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_4);
+ rte_eal_alarm_set(1000 * 100, txgbe_dev_detect_sfp, dev);
+ }
+ } else if (hw->mac.type == txgbe_mac_raptor || hw->mac.type == txgbe_mac_aml) {
+ if (reg & TXGBE_GPIOBIT_0)
+ wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_0);
+ if (reg & TXGBE_GPIOBIT_2) {
+ wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_2);
+ rte_eal_alarm_set(1000 * 100, txgbe_dev_detect_sfp, dev);
+ }
+ if (reg & TXGBE_GPIOBIT_3) {
+ wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_3);
+ intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
+ }
+ if (reg & TXGBE_GPIOBIT_6) {
+ wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_6);
+ intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
+ }
+ }
wr32(hw, TXGBE_GPIOINTMASK, 0);
}
@@ -3044,6 +3130,9 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev,
}
if (link_up == 0) {
+ if (hw->mac.type == txgbe_mac_aml)
+ wr32m(hw, TXGBE_GPIO_INT_POLARITY,
+ TXGBE_GPIO_INT_POLARITY_3, 0x0);
if ((hw->subsystem_device_id & 0xFF) ==
TXGBE_DEV_ID_KR_KX_KX4) {
hw->mac.bp_down_event(hw);
@@ -3130,6 +3219,28 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev,
wr32(hw, TXGBE_MAC_WDG_TIMEOUT, reg);
}
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) {
+ reg = rd32(hw, TXGBE_PORT);
+ if (reg & TXGBE_PORT_LINKUP) {
+ if (reg & TXGBE_CFG_PORT_ST_AML_LINK_40G) {
+ wr32(hw, TXGBE_MACTXCFG,
+ (rd32(hw, TXGBE_MACTXCFG) &
+ ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) | TXGBE_MACTXCFG_TXE |
+ TXGBE_MAC_TX_CFG_AML_SPEED_40G);
+ } else if (reg & TXGBE_CFG_PORT_ST_AML_LINK_25G) {
+ wr32(hw, TXGBE_MACTXCFG,
+ (rd32(hw, TXGBE_MACTXCFG) &
+ ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) | TXGBE_MACTXCFG_TXE |
+ TXGBE_MAC_TX_CFG_AML_SPEED_25G);
+ } else if (reg & TXGBE_CFG_PORT_ST_AML_LINK_10G) {
+ wr32(hw, TXGBE_MACTXCFG,
+ (rd32(hw, TXGBE_MACTXCFG) &
+ ~TXGBE_MAC_TX_CFG_AML_SPEED_MASK) | TXGBE_MACTXCFG_TXE |
+ TXGBE_MAC_TX_CFG_AML_SPEED_10G);
+ }
+ }
+ }
+
return rte_eth_linkstatus_set(dev, &link);
}
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 13/15] net/txgbe: disable unstable features
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (11 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 12/15] net/txgbe: add GPIO configuration Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 14/15] net/txgbe: add other hardware-related changes Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 15/15] doc: update for txgbe Zaiyu Wang
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Temporarily disabled unstable features on Amber-Lite NICs (e.g.,
flow control). These incomplete features will be gradually completed
in future driver updates.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_hw.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index fd6594e831..6010a4a569 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -144,6 +144,10 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw)
u32 value = 0;
u64 reg_bp = 0;
+ /* amlite-to-do */
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40)
+ return 0;
+
/* Validate the requested mode */
if (hw->fc.strict_ieee && hw->fc.requested_mode == txgbe_fc_rx_pause) {
DEBUGOUT("txgbe_fc_rx_pause not valid in strict IEEE mode");
@@ -3235,6 +3239,9 @@ void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
switch (speed) {
+ case TXGBE_LINK_SPEED_25GB_FULL:
+ /* amlite-to-do */
+ break;
case TXGBE_LINK_SPEED_10GB_FULL:
esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
break;
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 14/15] net/txgbe: add other hardware-related changes
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (12 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 13/15] net/txgbe: disable unstable features Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 15/15] doc: update for txgbe Zaiyu Wang
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Add other hardware-related changes for Amber-Lite NICs, such as PF
queue rate limit, enable/disable tx laser.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_hw.c | 113 +++++++++++++++++++++------
drivers/net/txgbe/base/txgbe_osdep.h | 2 +
drivers/net/txgbe/base/txgbe_phy.c | 35 +++++++++
drivers/net/txgbe/base/txgbe_regs.h | 23 ++++++
drivers/net/txgbe/base/txgbe_type.h | 27 +++++++
drivers/net/txgbe/txgbe_ethdev.c | 72 ++++++++++++++---
6 files changed, 238 insertions(+), 34 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 6010a4a569..4ffe5a3fcf 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -2213,27 +2213,56 @@ void txgbe_clear_tx_pending(struct txgbe_hw *hw)
*
* Returns the thermal sensor data structure
**/
+#define PHYINIT_TIMEOUT 1000
s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
{
struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
s64 tsv;
u32 ts_stat;
+ u32 data_code;
+ int temp_data, temp_fraction;
+ int i = 0;
/* Only support thermal sensors attached to physical port 0 */
if (hw->bus.lan_id != 0)
return TXGBE_NOT_IMPLEMENTED;
- ts_stat = rd32(hw, TXGBE_TSSTAT);
- tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
- tsv = tsv > 1200 ? tsv : 1200;
- tsv = -(48380 << 8) / 1000
- + tsv * (31020 << 8) / 100000
- - tsv * tsv * (18201 << 8) / 100000000
- + tsv * tsv * tsv * (81542 << 8) / 1000000000000
- - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
- tsv >>= 8;
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) {
+ wr32(hw, TXGBE_AML_TS_ENA, 0x0001);
- data->sensor[0].temp = (s16)tsv;
+ while (1) {
+ data_code = rd32(hw, TXGBE_AML_TS_STS);
+ if ((data_code & TXGBE_AML_TS_STS_VLD) != 0)
+ break;
+ msleep(1);
+ if (i++ > PHYINIT_TIMEOUT) {
+ PMD_DRV_LOG(ERR, "ERROR: Wait 0x1033c Timeout!!!");
+ return -1;
+ }
+ }
+
+ data_code = data_code & 0xFFF;
+ temp_data = 419400 + 2205 * (data_code * 1000 / 4094 - 500);
+
+ /* Change double Temperature to int */
+ tsv = temp_data / 10000;
+ temp_fraction = temp_data - (tsv * 10000);
+ if (temp_fraction >= 5000)
+ tsv += 1;
+ data->sensor[0].temp = (s16)tsv;
+ } else {
+ ts_stat = rd32(hw, TXGBE_TSSTAT);
+ tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
+ tsv = tsv > 1200 ? tsv : 1200;
+ tsv = -(48380 << 8) / 1000
+ + tsv * (31020 << 8) / 100000
+ - tsv * tsv * (18201 << 8) / 100000000
+ + tsv * tsv * tsv * (81542 << 8) / 1000000000000
+ - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
+ tsv >>= 8;
+
+ data->sensor[0].temp = (s16)tsv;
+ }
return 0;
}
@@ -2254,16 +2283,32 @@ s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
if (hw->bus.lan_id != 0)
return TXGBE_NOT_IMPLEMENTED;
- wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
- wr32(hw, TXGBE_TSINTR,
- TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
- wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
-
-
data->sensor[0].alarm_thresh = 100;
- wr32(hw, TXGBE_TSATHRE, 677);
data->sensor[0].dalarm_thresh = 90;
- wr32(hw, TXGBE_TSDTHRE, 614);
+
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) {
+ wr32(hw, TXGBE_AML_TS_ENA, 0x0);
+ wr32(hw, TXGBE_AML_INTR_RAW_LO, TXGBE_AML_INTR_CL_LO);
+ wr32(hw, TXGBE_AML_INTR_RAW_HI, TXGBE_AML_INTR_CL_HI);
+
+ wr32(hw, TXGBE_AML_INTR_HIGH_EN, TXGBE_AML_INTR_EN_HI);
+ wr32(hw, TXGBE_AML_INTR_LOW_EN, TXGBE_AML_INTR_EN_LO);
+
+ wr32m(hw, TXGBE_AML_TS_CTL1, TXGBE_AML_EVAL_MODE_MASK, 0x10);
+ wr32m(hw, TXGBE_AML_TS_CTL1, TXGBE_AML_ALARM_THRE_MASK, 0x186a0000);
+ wr32m(hw, TXGBE_AML_TS_CTL1, TXGBE_AML_DALARM_THRE_MASK, 0x16f60);
+ wr32(hw, TXGBE_AML_TS_ENA, 0x1);
+ } else {
+ wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
+ wr32(hw, TXGBE_TSINTR,
+ TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
+ wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
+
+ data->sensor[0].alarm_thresh = 100;
+ wr32(hw, TXGBE_TSATHRE, 677);
+ data->sensor[0].dalarm_thresh = 90;
+ wr32(hw, TXGBE_TSDTHRE, 614);
+ }
return 0;
}
@@ -3172,12 +3217,28 @@ void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
{
u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
- if (txgbe_close_notify(hw))
- txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_LEDCTL_10G |
- TXGBE_LEDCTL_1G | TXGBE_LEDCTL_ACTIVE);
+ if (txgbe_close_notify(hw)) {
+ /* over write led when ifconfig down */
+ if (hw->mac.type == txgbe_mac_aml40) {
+ txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_AMLITE_LED_LINK_40G |
+ TXGBE_AMLITE_LED_LINK_ACTIVE);
+ } else if (hw->mac.type == txgbe_mac_aml)
+ txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_AMLITE_LED_LINK_25G |
+ TXGBE_AMLITE_LED_LINK_10G | TXGBE_AMLITE_LED_LINK_ACTIVE);
+ else
+ txgbe_led_off(hw, TXGBE_LEDCTL_UP | TXGBE_LEDCTL_10G |
+ TXGBE_LEDCTL_1G | TXGBE_LEDCTL_ACTIVE);
+ }
/* Disable Tx laser; allow 100us to go dark per spec */
- esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
+ if (hw->mac.type == txgbe_mac_aml40) {
+ wr32m(hw, TXGBE_GPIODIR, TXGBE_GPIOBIT_1, TXGBE_GPIOBIT_1);
+ esdp_reg &= ~TXGBE_GPIOBIT_1;
+ } else if (hw->mac.type == txgbe_mac_aml) {
+ esdp_reg |= TXGBE_GPIOBIT_1;
+ } else {
+ esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
+ }
wr32(hw, TXGBE_GPIODATA, esdp_reg);
txgbe_flush(hw);
usec_delay(100);
@@ -3199,7 +3260,13 @@ void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
wr32(hw, TXGBE_LEDCTL, 0);
/* Enable Tx laser; allow 100ms to light up */
- esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
+
+ if (hw->mac.type == txgbe_mac_aml40) {
+ wr32m(hw, TXGBE_GPIODIR, TXGBE_GPIOBIT_1, TXGBE_GPIOBIT_1);
+ esdp_reg |= TXGBE_GPIOBIT_1;
+ } else {
+ esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
+ }
wr32(hw, TXGBE_GPIODATA, esdp_reg);
txgbe_flush(hw);
msec_delay(100);
diff --git a/drivers/net/txgbe/base/txgbe_osdep.h b/drivers/net/txgbe/base/txgbe_osdep.h
index a1477653e2..05071aca22 100644
--- a/drivers/net/txgbe/base/txgbe_osdep.h
+++ b/drivers/net/txgbe/base/txgbe_osdep.h
@@ -162,6 +162,8 @@ static inline u64 REVERT_BIT_MASK64(u64 mask)
((mask & 0xFFFFFFFF00000000) >> 32);
}
+#define BIT(nr) (1UL << (nr))
+
#define IOMEM
#define prefetch(x) rte_prefetch0(x)
diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index 81e9aee295..bf7260a295 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -173,6 +173,41 @@ s32 txgbe_get_phy_id(struct txgbe_hw *hw)
u32 err;
u16 phy_id_high = 0;
u16 phy_id_low = 0;
+ u32 i = 0;
+ u32 status;
+
+ if (hw->mac.type == txgbe_mac_aml) {
+ hw->phy.addr = 0;
+
+ for (i = 0; i < 32; i++) {
+ hw->phy.addr = i;
+ status = txgbe_read_phy_reg_mdi(hw, TXGBE_MD_PHY_ID_HIGH, 0, &phy_id_high);
+ if (status) {
+ DEBUGOUT("txgbe_read_phy_reg_mdi failed 1");
+ return status;
+ }
+ DEBUGOUT("%d: phy_id_high 0x%x", i, phy_id_high);
+ if ((phy_id_high & 0xFFFF) == 0x0141)
+ break;
+ }
+
+ if (i == 32) {
+ DEBUGOUT("txgbe_read_phy_reg_mdi failed");
+ return TXGBE_ERR_PHY;
+ }
+
+ status = txgbe_read_phy_reg_mdi(hw, TXGBE_MD_PHY_ID_LOW, 0, &phy_id_low);
+ if (status) {
+ DEBUGOUT("txgbe_read_phy_reg_mdi failed 2");
+ return status;
+ }
+ hw->phy.id = (u32)(phy_id_high & 0xFFFF) << 6;
+ hw->phy.id |= (u32)((phy_id_low & 0xFC00) >> 10);
+
+ DEBUGOUT("phy_id 0x%x", hw->phy.id);
+
+ return status;
+ }
err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
TXGBE_MD_DEV_PMA_PMD,
diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
index 98d1070daa..f32f17428b 100644
--- a/drivers/net/txgbe/base/txgbe_regs.h
+++ b/drivers/net/txgbe/base/txgbe_regs.h
@@ -302,6 +302,17 @@
#define TXGBE_PORT_LINK1000M MS(2, 0x1)
#define TXGBE_PORT_LINK100M MS(3, 0x1)
#define TXGBE_PORT_LANID(r) RS(r, 8, 0x1)
+#define TXGBE_AMLITE_CFG_LED_CTL_LINK_BSY_SEL MS(5, 0x1)
+#define TXGBE_AMLITE_CFG_LED_CTL_LINK_10G_SEL MS(4, 0x1)
+#define TXGBE_AMLITE_CFG_LED_CTL_LINK_25G_SEL MS(3, 0x1)
+#define TXGBE_AMLITE_CFG_LED_CTL_LINK_40G_SEL MS(2, 0x1)
+#define TXGBE_AMLITE_CFG_LED_CTL_LINK_50G_SEL MS(1, 0x1)
+#define TXGBE_AMLITE_LED_LINK_ACTIVE TXGBE_AMLITE_CFG_LED_CTL_LINK_BSY_SEL
+#define TXGBE_AMLITE_LED_LINK_10G TXGBE_AMLITE_CFG_LED_CTL_LINK_10G_SEL
+#define TXGBE_AMLITE_LED_LINK_25G TXGBE_AMLITE_CFG_LED_CTL_LINK_25G_SEL
+#define TXGBE_AMLITE_LED_LINK_40G TXGBE_AMLITE_CFG_LED_CTL_LINK_40G_SEL
+#define TXGBE_AMLITE_LED_LINK_50G TXGBE_AMLITE_CFG_LED_CTL_LINK_50G_SEL
+
#define TXGBE_EXTAG 0x014408
#define TXGBE_EXTAG_ETAG_MASK MS(0, 0xFFFF)
#define TXGBE_EXTAG_ETAG(v) LS(v, 0, 0xFFFF)
@@ -1641,6 +1652,18 @@ enum txgbe_5tuple_protocol {
#define TXGBE_ARBTXRATE_MIN(v) LS(v, 0, 0x3FFF)
#define TXGBE_ARBTXRATE_MAX(v) LS(v, 16, 0x3FFF)
+#define TXGBE_TDM_RL_QUEUE_IDX 0x018210
+#define TXGBE_TDM_RL_QUEUE_CFG 0x018214
+#define TXGBE_TDM_FACTOR_INT_MASK MS(16, 0xFFFF)
+#define TXGBE_TDM_FACTOR_FRA_MASK MS(0, 0xFFFC)
+#define TXGBE_TDM_FACTOR_INT_SHIFT 16
+#define TXGBE_TDM_FACTOR_FRA_SHIFT 2
+
+#define TXGBE_TDM_RL_VM_IDX 0x018218
+#define TXGBE_TDM_RL_VM_CFG 0x01821C
+#define TXGBE_TDM_RL_CFG 0x018400
+#define TXGBE_TDM_RL_EN MS(0, 0x1)
+
/* qos */
#define TXGBE_ARBTXCTL 0x018200
#define TXGBE_ARBTXCTL_RRM MS(1, 0x1)
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 3833f1420a..aad8a15129 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -37,6 +37,33 @@
#include "txgbe_osdep.h"
#include "txgbe_devids.h"
+/* Sensors for AMLITE PVT(Process Voltage Temperature) */
+#define TXGBE_AML_INTR_RAW_HI 0x10300
+#define TXGBE_AML_INTR_RAW_ME 0x10304
+#define TXGBE_AML_INTR_RAW_LO 0x10308
+#define TXGBE_AML_TS_CTL1 0x10330
+#define TXGBE_AML_TS_CTL2 0x10334
+#define TXGBE_AML_TS_ENA 0x10338
+#define TXGBE_AML_TS_STS 0x1033C
+#define TXGBE_AML_INTR_HIGH_EN 0x10318
+#define TXGBE_AML_INTR_MED_EN 0x1031C
+#define TXGBE_AML_INTR_LOW_EN 0x10320
+#define TXGBE_AML_INTR_HIGH_STS 0x1030C
+#define TXGBE_AML_INTR_MED_STS 0x10310
+#define TXGBE_AML_INTR_LOW_STS 0x10314
+
+#define TXGBE_AML_TS_STS_VLD 0x00001000U
+#define TXGBE_AML_INTR_EN_HI 0x00000002U
+#define TXGBE_AML_INTR_EN_ME 0x00000001U
+#define TXGBE_AML_INTR_EN_LO 0x00000001U
+#define TXGBE_AML_INTR_CL_HI 0x00000002U
+#define TXGBE_AML_INTR_CL_ME 0x00000001U
+#define TXGBE_AML_INTR_CL_LO 0x00000001U
+#define TXGBE_AML_EVAL_MODE_MASK 0x00000010U
+#define TXGBE_AML_CAL_MODE_MASK 0x00000008U
+#define TXGBE_AML_ALARM_THRE_MASK 0x1FFE0000U
+#define TXGBE_AML_DALARM_THRE_MASK 0x0001FFE0U
+
struct txgbe_thermal_diode_data {
s16 temp;
s16 alarm_thresh;
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 9fd4923b6d..9032f52951 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -4243,33 +4243,80 @@ txgbe_configure_msix(struct rte_eth_dev *dev)
| TXGBE_ITR_WRDSA);
}
+static u16 txgbe_frac_to_bi(u16 frac, u16 denom, int max_bits)
+{
+ u16 value = 0;
+
+ while (frac > 0 && max_bits > 0) {
+ max_bits -= 1;
+ frac *= 2;
+ if (frac >= denom) {
+ value |= BIT(max_bits);
+ frac -= denom;
+ }
+ }
+
+ return value;
+}
+
int
txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
uint16_t queue_idx, uint32_t tx_rate)
{
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
uint32_t bcnrc_val;
+ int factor_int, factor_fra;
+ uint32_t link_speed;
if (queue_idx >= hw->mac.max_tx_queues)
return -EINVAL;
- if (tx_rate != 0) {
- bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
- bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
- } else {
- bcnrc_val = 0;
- }
-
/*
* Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
* register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
*/
wr32(hw, TXGBE_ARBTXMMW, 0x14);
- /* Set ARBTXRATE of queue X */
- wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
- wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
- txgbe_flush(hw);
+ if (hw->mac.type == txgbe_mac_aml || hw->mac.type == txgbe_mac_aml40) {
+ if (tx_rate) {
+ u16 frac;
+
+ link_speed = dev->data->dev_link.link_speed;
+ tx_rate = tx_rate * 105 / 100;
+ /* Calculate the rate factor values to set */
+ factor_int = link_speed / tx_rate;
+ frac = (link_speed % tx_rate) * 10000 / tx_rate;
+ factor_fra = txgbe_frac_to_bi(frac, 10000, 14);
+ if (tx_rate > link_speed) {
+ factor_int = 1;
+ factor_fra = 0;
+ }
+
+ wr32(hw, TXGBE_TDM_RL_QUEUE_IDX, queue_idx);
+ wr32m(hw, TXGBE_TDM_RL_QUEUE_CFG,
+ TXGBE_TDM_FACTOR_INT_MASK, factor_int << TXGBE_TDM_FACTOR_INT_SHIFT);
+ wr32m(hw, TXGBE_TDM_RL_QUEUE_CFG,
+ TXGBE_TDM_FACTOR_FRA_MASK, factor_fra << TXGBE_TDM_FACTOR_FRA_SHIFT);
+ wr32m(hw, TXGBE_TDM_RL_QUEUE_CFG,
+ TXGBE_TDM_RL_EN, TXGBE_TDM_RL_EN);
+ } else {
+ wr32(hw, TXGBE_TDM_RL_QUEUE_IDX, queue_idx);
+ wr32m(hw, TXGBE_TDM_RL_QUEUE_CFG,
+ TXGBE_TDM_RL_EN, 0);
+ }
+ } else {
+ if (tx_rate != 0) {
+ bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
+ bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
+ } else {
+ bcnrc_val = 0;
+ }
+
+ /* Set ARBTXRATE of queue X */
+ wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
+ wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
+ txgbe_flush(hw);
+ }
return 0;
}
@@ -5121,7 +5168,10 @@ txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
{
switch (mac_type) {
case txgbe_mac_raptor:
+ case txgbe_mac_aml:
+ case txgbe_mac_aml40:
case txgbe_mac_raptor_vf:
+ case txgbe_mac_aml_vf:
return 1;
default:
return 0;
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 15/15] doc: update for txgbe
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
` (13 preceding siblings ...)
2025-06-25 12:50 ` [PATCH v2 14/15] net/txgbe: add other hardware-related changes Zaiyu Wang
@ 2025-06-25 12:50 ` Zaiyu Wang
14 siblings, 0 replies; 19+ messages in thread
From: Zaiyu Wang @ 2025-06-25 12:50 UTC (permalink / raw)
To: dev; +Cc: Zaiyu Wang, Jiawen Wu, Jian Wang
Add new types of Wangxun NICs into txgbe supported NICs list.
Signed-off-by: Zaiyu Wang <zaiyuwang@trustnetic.com>
---
doc/guides/nics/txgbe.rst | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/doc/guides/nics/txgbe.rst b/doc/guides/nics/txgbe.rst
index 93fb592759..ccf645d51f 100644
--- a/doc/guides/nics/txgbe.rst
+++ b/doc/guides/nics/txgbe.rst
@@ -4,8 +4,12 @@
TXGBE Poll Mode Driver
======================
-The TXGBE PMD (librte_pmd_txgbe) provides poll mode driver support
-for Wangxun 10 Gigabit Ethernet NICs.
+Supported NICs
+--------
+
+- Wangxun 10 Gigabit Ethernet NICs
+- Wangxun 25 Gigabit Ethernet NICs
+- Wangxun 40 Gigabit Ethernet NICs
Features
--------
--
2.21.0.windows.1
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2025-06-25 12:53 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-04-18 9:41 [PATCH 0/2] *** Wangxun new NIC support *** Zaiyu Wang
2025-04-18 9:41 ` [PATCH 1/2] net/txgbe: add support for Wangxun new NIC Amber-Lite 25g/40g Zaiyu Wang
2025-04-18 9:41 ` [PATCH 2/2] net/txgbe: add basic code for Amber-Liter NIC configuration Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 00/15] Wangxun new NIC support Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 01/15] net/txgbe: add basic information for Amber-Lite 25G/40G NICs Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 02/15] net/txgbe: add new SW-FW mailbox interface Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 03/15] net/txgbe: add identification support for new SFP/QSFP modules Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 04/15] net/txgbe: add basic link configuration for Amber-Lite NICs Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 05/15] net/txgbe: add support for PHY configuration via SW-FW mailbox Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 06/15] net/txgbe: add RX&TX support for Amber-Lite NICs Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 07/15] net/txgbe: add hardware reset change " Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 08/15] net/txgbe: add MAC reconfiguration to avoid packet loss Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 09/15] net/txgbe: add TX head Write-Back mode for Amber-Lite NICs Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 10/15] net/txgbe: add RX desc merge " Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 11/15] net/txgbe: add FEC support for Amber-Lite 25G NICs Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 12/15] net/txgbe: add GPIO configuration Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 13/15] net/txgbe: disable unstable features Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 14/15] net/txgbe: add other hardware-related changes Zaiyu Wang
2025-06-25 12:50 ` [PATCH v2 15/15] doc: update for txgbe Zaiyu Wang
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