From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 77B1A46A70; Fri, 27 Jun 2025 12:58:15 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2CB5440695; Fri, 27 Jun 2025 12:58:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id EB07E40677 for ; Fri, 27 Jun 2025 12:57:57 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55RA0GiO019553; Fri, 27 Jun 2025 03:57:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=R BZumREjB4faLj9tdL2gzX47x6SBDNuN30mUT2QKibU=; b=QXIEkWQ3fR3RoG1PQ rPskWRGPMwhX3f+2+bsoHooocSsRVmEfU5NC0sG+3NQ5xOAux/0YIscB7toE3qS9 vHc8q3d4J+S9GDuC+eAbNrlLJddcVicfNBe81hGzDjjI+8tJz79p21ewvAYrhvOm 0lSdYnCqaQxTjLyRUZNmlTWlfitApqlh5mAMAhcvYaES037vQClpi8SZ7GIA8LLN z5DfcfUEupNYq1d2TT/TkahlkBqpW785Uvy/wz07r9HJmRpU6VC8Rk1KPYDRlaNv yAG+C9QtTZ/R3VL+oqPWh3C/o12m1ZeYunNZoh09fnoty3I5xj2EleZw4yJHIPng Bpm5g== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 47hs5c83np-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 27 Jun 2025 03:57:57 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 27 Jun 2025 03:57:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 27 Jun 2025 03:57:56 -0700 Received: from cavium-optiplex-3070-BM15.. (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id C174C5C68E3; Fri, 27 Jun 2025 03:57:53 -0700 (PDT) From: Tomasz Duszynski To: CC: , , , , , Subject: [PATCH v6 4/8] lib/pmu: do not try enabling perf counter access on arm64 Date: Fri, 27 Jun 2025 12:57:36 +0200 Message-ID: <20250627105740.3388237-5-tduszynski@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250627105740.3388237-1-tduszynski@marvell.com> References: <20250625044730.2435526-1-tduszynski@marvell.com> <20250627105740.3388237-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: TC3zNBuAcyfWmLxfK7O6Zqt8gMo3pYz3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI3MDA4OSBTYWx0ZWRfX3RtLtCsO0hrH 3yLaROOFf1GueGqnA5KfigzYJr6fN5a0R5gPwL+/5U0r2lKk+upJPZRbtLBgkMLjwC3PDI0eu7q 9QomTFBtTbKBdc4cODv5Q/Xws+3mQjYizTXbjvVyTBgSMqUB6aaZHz9u9EUEVMgs9w2mqgsglJF fqmGhR1sanS0JIGxtibFZlwvUzY38zk14aBoqYWN2TUO0JCbgaQiXqgO3T/JIgKY9/IDpFgSVvj npjF0R4idZCRMlyo+BctgHbNHWw2DHNLkVQddETZp4JiLSHGiAP/bA3b5BA+u939Uaa02OmDoeu 6xY0SBYVU+xpmgIXgCy2SFWWqh7GnL4yklpK0rpxpXFPpuV/Mj5sfzxkvhUde9QvVA2UMj19k0g jZeXEV80g9TNwZZSRSZ/KFJoyZsc2TFlqDTZ/EvriRNV0xwrqZpR3WI9kGc+lxz47GIxHb6W X-Proofpoint-GUID: TC3zNBuAcyfWmLxfK7O6Zqt8gMo3pYz3 X-Authority-Analysis: v=2.4 cv=BNOzrEQG c=1 sm=1 tr=0 ts=685e7935 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=6IFa9wvqVegA:10 a=M5GUcnROAAAA:8 a=Oq_oc4OIQJrBT0az780A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-27_04,2025-06-26_05,2025-03-28_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org /proc/sys/kernel/perf_user_access attribute allow user process to access perf counters. Though in order to change it binary requires elevated capabilities or must be run as root. If that's not the case counter access remains disabled. Hence to avoid confusion log message that that warns user about that. Signed-off-by: Tomasz Duszynski --- lib/pmu/pmu.c | 4 ---- lib/pmu/pmu_arm64.c | 39 +++++++-------------------------------- lib/pmu/pmu_private.h | 8 ++++++++ 3 files changed, 15 insertions(+), 36 deletions(-) diff --git a/lib/pmu/pmu.c b/lib/pmu/pmu.c index 0709f5e58c..3cae29891c 100644 --- a/lib/pmu/pmu.c +++ b/lib/pmu/pmu.c @@ -25,10 +25,6 @@ #define FIELD_PREP(m, v) (((uint64_t)(v) << (rte_ffs64(m) - 1)) & (m)) RTE_LOG_REGISTER_DEFAULT(rte_pmu_logtype, INFO) -#define RTE_LOGTYPE_PMU rte_pmu_logtype - -#define PMU_LOG(level, ...) \ - RTE_LOG_LINE(level, PMU, ## __VA_ARGS__) /* A structure describing an event */ struct rte_pmu_event { diff --git a/lib/pmu/pmu_arm64.c b/lib/pmu/pmu_arm64.c index 3f4f5fa297..2c40b5f702 100644 --- a/lib/pmu/pmu_arm64.c +++ b/lib/pmu/pmu_arm64.c @@ -14,8 +14,6 @@ #define PERF_USER_ACCESS_PATH "/proc/sys/kernel/perf_user_access" -static int restore_uaccess; - static int read_attr_int(const char *path, int *val) { @@ -39,49 +37,26 @@ read_attr_int(const char *path, int *val) return 0; } -static int -write_attr_int(const char *path, int val) -{ - char buf[BUFSIZ]; - int num, ret, fd; - - fd = open(path, O_WRONLY); - if (fd == -1) - return -errno; - - num = snprintf(buf, sizeof(buf), "%d", val); - ret = write(fd, buf, num); - if (ret == -1) { - close(fd); - - return -errno; - } - - close(fd); - - return 0; -} - static int pmu_arm64_init(void) { - int ret; + int uaccess, ret; - ret = read_attr_int(PERF_USER_ACCESS_PATH, &restore_uaccess); + ret = read_attr_int(PERF_USER_ACCESS_PATH, &uaccess); if (ret) return ret; - /* user access already enabled */ - if (restore_uaccess == 1) - return 0; + if (uaccess != 1) + PMU_LOG(WARNING, "access to perf counters disabled, " + "run 'echo 1 > %s' to enable", + PERF_USER_ACCESS_PATH); - return write_attr_int(PERF_USER_ACCESS_PATH, 1); + return ret; } static void pmu_arm64_fini(void) { - write_attr_int(PERF_USER_ACCESS_PATH, restore_uaccess); } static void diff --git a/lib/pmu/pmu_private.h b/lib/pmu/pmu_private.h index d74f7f4092..82118df8b3 100644 --- a/lib/pmu/pmu_private.h +++ b/lib/pmu/pmu_private.h @@ -5,6 +5,14 @@ #ifndef PMU_PRIVATE_H #define PMU_PRIVATE_H +#include + +extern int rte_pmu_logtype; +#define RTE_LOGTYPE_PMU rte_pmu_logtype + +#define PMU_LOG(level, ...) \ + RTE_LOG_LINE(level, PMU, ## __VA_ARGS__) + /** * Structure describing architecture specific PMU operations. */ -- 2.34.1