DPDK patches and discussions
 help / color / mirror / Atom feed
* [PATCH v1 0/4] net/ntnic: implement start, stop and deferred start for Rx/Tx queues
@ 2025-06-20 11:27 Oleksandr Kolomeiets
  2025-06-20 11:27 ` [PATCH v1 1/4] net/ntnic: implement start/stop " Oleksandr Kolomeiets
                   ` (4 more replies)
  0 siblings, 5 replies; 6+ messages in thread
From: Oleksandr Kolomeiets @ 2025-06-20 11:27 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, sil-plv, ckm, stephen

This patchset includes:
 
	* feature start/stop queues on HW layer.
	* feature deferred start for queues.
	* Improvement for memory mappings when IOMMU is unoptimized.
	* Improvement for logging

Oleksandr Kolomeiets (4):
  net/ntnic: implement start/stop for Rx/Tx queues
  net/ntnic: implement deferred start for Rx/Tx queues
  net/ntnic: unmap DMA during queue release
  net/ntnic: add warning when sending on a stopped queue

 drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c |  58 +++++---
 drivers/net/ntnic/include/ntnic_dbs.h         |   2 +
 drivers/net/ntnic/include/ntos_drv.h          |   4 +-
 drivers/net/ntnic/nthw/dbs/nthw_dbs.c         |  20 +++
 drivers/net/ntnic/ntnic_ethdev.c              | 132 ++++++++++++++++--
 drivers/net/ntnic/ntnic_mod_reg.h             |  14 +-
 drivers/net/ntnic/ntnic_vfio.c                |   3 -
 7 files changed, 193 insertions(+), 40 deletions(-)

-- 
2.47.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v1 1/4] net/ntnic: implement start/stop for Rx/Tx queues
  2025-06-20 11:27 [PATCH v1 0/4] net/ntnic: implement start, stop and deferred start for Rx/Tx queues Oleksandr Kolomeiets
@ 2025-06-20 11:27 ` Oleksandr Kolomeiets
  2025-06-20 11:27 ` [PATCH v1 2/4] net/ntnic: implement deferred start " Oleksandr Kolomeiets
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 6+ messages in thread
From: Oleksandr Kolomeiets @ 2025-06-20 11:27 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, sil-plv, ckm, stephen

The following functions exported by the driver were stubs
which merely changed the status flags:
*	rx_queue_start
*	rx_queue_stop
*	tx_queue_start
*	tx_queue_stop

Proper implementation was added to control queues's state.

Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
 drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c | 12 +++
 drivers/net/ntnic/include/ntnic_dbs.h         |  2 +
 drivers/net/ntnic/nthw/dbs/nthw_dbs.c         | 20 +++++
 drivers/net/ntnic/ntnic_ethdev.c              | 80 ++++++++++++++++++-
 drivers/net/ntnic/ntnic_mod_reg.h             |  2 +
 5 files changed, 112 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
index 94b0c97d27..0b049a8559 100644
--- a/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
+++ b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
@@ -1115,6 +1115,16 @@ nthw_setup_mngd_tx_virt_queue(nthw_dbs_t *p_nthw_dbs,
 	return NULL;
 }
 
+static int nthw_switch_rx_virt_queue(nthw_dbs_t *p_nthw_dbs, uint32_t index, uint32_t enable)
+{
+	return set_rx_am_data_enable(p_nthw_dbs, index, enable);
+}
+
+static int nthw_switch_tx_virt_queue(nthw_dbs_t *p_nthw_dbs, uint32_t index, uint32_t enable)
+{
+	return set_tx_am_data_enable(p_nthw_dbs, index, enable);
+}
+
 static uint16_t nthw_get_rx_packets(struct nthw_virt_queue *rxvq,
 	uint16_t n,
 	struct nthw_received_packets *rp,
@@ -1419,6 +1429,8 @@ static struct sg_ops_s sg_ops = {
 	.nthw_release_mngd_rx_virt_queue = nthw_release_mngd_rx_virt_queue,
 	.nthw_setup_mngd_tx_virt_queue = nthw_setup_mngd_tx_virt_queue,
 	.nthw_release_mngd_tx_virt_queue = nthw_release_mngd_tx_virt_queue,
+	.nthw_switch_rx_virt_queue = nthw_switch_rx_virt_queue,
+	.nthw_switch_tx_virt_queue = nthw_switch_tx_virt_queue,
 	.nthw_get_rx_packets = nthw_get_rx_packets,
 	.nthw_release_rx_packets = nthw_release_rx_packets,
 	.nthw_get_tx_packets = nthw_get_tx_packets,
diff --git a/drivers/net/ntnic/include/ntnic_dbs.h b/drivers/net/ntnic/include/ntnic_dbs.h
index 247ae76d98..c35a7cb99b 100644
--- a/drivers/net/ntnic/include/ntnic_dbs.h
+++ b/drivers/net/ntnic/include/ntnic_dbs.h
@@ -267,6 +267,7 @@ int set_rx_am_data(nthw_dbs_t *p,
 	uint32_t host_id,
 	uint32_t packed,
 	uint32_t int_enable);
+int set_rx_am_data_enable(nthw_dbs_t *p, uint32_t index, uint32_t enable);
 int set_tx_am_data(nthw_dbs_t *p,
 	uint32_t index,
 	uint64_t guest_physical_address,
@@ -274,6 +275,7 @@ int set_tx_am_data(nthw_dbs_t *p,
 	uint32_t host_id,
 	uint32_t packed,
 	uint32_t int_enable);
+int set_tx_am_data_enable(nthw_dbs_t *p, uint32_t index, uint32_t enable);
 int set_rx_uw_data(nthw_dbs_t *p,
 	uint32_t index,
 	uint64_t guest_physical_address,
diff --git a/drivers/net/ntnic/nthw/dbs/nthw_dbs.c b/drivers/net/ntnic/nthw/dbs/nthw_dbs.c
index aed52f67f5..da64dbab48 100644
--- a/drivers/net/ntnic/nthw/dbs/nthw_dbs.c
+++ b/drivers/net/ntnic/nthw/dbs/nthw_dbs.c
@@ -618,6 +618,16 @@ int set_rx_am_data(nthw_dbs_t *p,
 	return 0;
 }
 
+int set_rx_am_data_enable(nthw_dbs_t *p, uint32_t index, uint32_t enable)
+{
+	if (!p->mp_reg_rx_avail_monitor_data)
+		return -ENOTSUP;
+
+	nthw_dbs_set_shadow_rx_am_data_enable(p, index, enable);
+	flush_rx_am_data(p, index);
+	return 0;
+}
+
 static void set_tx_am_data_index(nthw_dbs_t *p, uint32_t index)
 {
 	nthw_field_set_val32(p->mp_fld_tx_avail_monitor_control_adr, index);
@@ -680,6 +690,16 @@ int set_tx_am_data(nthw_dbs_t *p,
 	return 0;
 }
 
+int set_tx_am_data_enable(nthw_dbs_t *p, uint32_t index, uint32_t enable)
+{
+	if (!p->mp_reg_tx_avail_monitor_data)
+		return -ENOTSUP;
+
+	p->m_tx_am_shadow[index].enable = enable;
+	flush_tx_am_data(p, index);
+	return 0;
+}
+
 static void set_rx_uw_data_index(nthw_dbs_t *p, uint32_t index)
 {
 	nthw_field_set_val32(p->mp_fld_rx_used_writer_control_adr, index);
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index c2a507675c..d961edb903 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -1180,25 +1180,97 @@ static int dev_set_mtu_inline(struct rte_eth_dev *eth_dev, uint16_t mtu)
 
 static int eth_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 {
+	if (sg_ops == NULL) {
+		NT_LOG_DBGX(DBG, NTNIC, "SG module is not initialized");
+		return -1;
+	}
+
+	struct pmd_internals *internals = eth_dev->data->dev_private;
+	struct drv_s *p_drv = internals->p_drv;
+	struct ntdrv_4ga_s *p_nt_drv = &p_drv->ntdrv;
+	nthw_dbs_t *p_nthw_dbs = p_nt_drv->adapter_info.fpga_info.mp_nthw_dbs;
+	struct ntnic_rx_queue *rx_q = &internals->rxq_scg[rx_queue_id];
+	int index = rx_q->queue.hw_id;
+
+	if (sg_ops->nthw_switch_rx_virt_queue(p_nthw_dbs, index, 1) != 0) {
+		NT_LOG_DBGX(DBG, NTNIC, "Failed to start Rx queue #%d", index);
+		return -1;
+	}
+
+	rx_q->enabled = 1;
 	eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 	return 0;
 }
 
 static int eth_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 {
+	if (sg_ops == NULL) {
+		NT_LOG_DBGX(DBG, NTNIC, "SG module is not initialized");
+		return -1;
+	}
+
+	struct pmd_internals *internals = eth_dev->data->dev_private;
+	struct drv_s *p_drv = internals->p_drv;
+	struct ntdrv_4ga_s *p_nt_drv = &p_drv->ntdrv;
+	nthw_dbs_t *p_nthw_dbs = p_nt_drv->adapter_info.fpga_info.mp_nthw_dbs;
+	struct ntnic_rx_queue *rx_q = &internals->rxq_scg[rx_queue_id];
+	int index = rx_q->queue.hw_id;
+
+	if (sg_ops->nthw_switch_rx_virt_queue(p_nthw_dbs, index, 0) != 0) {
+		NT_LOG_DBGX(DBG, NTNIC, "Failed to stop Rx queue #%d", index);
+		return -1;
+	}
+
+	rx_q->enabled = 0;
 	eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 	return 0;
 }
 
-static int eth_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
+static int eth_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 {
-	eth_dev->data->tx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
+	if (sg_ops == NULL) {
+		NT_LOG_DBGX(DBG, NTNIC, "SG module is not initialized");
+		return -1;
+	}
+
+	struct pmd_internals *internals = eth_dev->data->dev_private;
+	struct drv_s *p_drv = internals->p_drv;
+	struct ntdrv_4ga_s *p_nt_drv = &p_drv->ntdrv;
+	nthw_dbs_t *p_nthw_dbs = p_nt_drv->adapter_info.fpga_info.mp_nthw_dbs;
+	struct ntnic_tx_queue *tx_q = &internals->txq_scg[tx_queue_id];
+	int index = tx_q->queue.hw_id;
+
+	if (sg_ops->nthw_switch_tx_virt_queue(p_nthw_dbs, index, 1) != 0) {
+		NT_LOG_DBGX(DBG, NTNIC, "Failed to start Tx queue #%d", index);
+		return -1;
+	}
+
+	tx_q->enabled = 1;
+	eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 	return 0;
 }
 
-static int eth_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
+static int eth_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 {
-	eth_dev->data->tx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
+	if (sg_ops == NULL) {
+		NT_LOG_DBGX(DBG, NTNIC, "SG module is not initialized");
+		return -1;
+	}
+
+	struct pmd_internals *internals = eth_dev->data->dev_private;
+	struct drv_s *p_drv = internals->p_drv;
+	struct ntdrv_4ga_s *p_nt_drv = &p_drv->ntdrv;
+	nthw_dbs_t *p_nthw_dbs = p_nt_drv->adapter_info.fpga_info.mp_nthw_dbs;
+	struct ntnic_tx_queue *tx_q = &internals->txq_scg[tx_queue_id];
+	int index = tx_q->queue.hw_id;
+
+	if (sg_ops->nthw_switch_tx_virt_queue(p_nthw_dbs, index, 0) != 0) {
+		NT_LOG_DBGX(DBG, NTNIC, "Failed to stop Tx queue #%d", index);
+		return -1;
+	}
+
+	tx_q->enabled = 0;
+	eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 	return 0;
 }
 
diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h
index 9d14bebd7a..7f5bd5e0ec 100644
--- a/drivers/net/ntnic/ntnic_mod_reg.h
+++ b/drivers/net/ntnic/ntnic_mod_reg.h
@@ -94,6 +94,8 @@ struct sg_ops_s {
 		int irq_vector,
 		uint32_t in_order);
 	int (*nthw_release_mngd_tx_virt_queue)(struct nthw_virt_queue *txvq);
+	int (*nthw_switch_rx_virt_queue)(nthw_dbs_t *p_nthw_dbs, uint32_t index, uint32_t enable);
+	int (*nthw_switch_tx_virt_queue)(nthw_dbs_t *p_nthw_dbs, uint32_t index, uint32_t enable);
 	/*
 	 * These functions handles both Split and Packed including merged buffers (jumbo)
 	 */
-- 
2.47.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v1 2/4] net/ntnic: implement deferred start for Rx/Tx queues
  2025-06-20 11:27 [PATCH v1 0/4] net/ntnic: implement start, stop and deferred start for Rx/Tx queues Oleksandr Kolomeiets
  2025-06-20 11:27 ` [PATCH v1 1/4] net/ntnic: implement start/stop " Oleksandr Kolomeiets
@ 2025-06-20 11:27 ` Oleksandr Kolomeiets
  2025-06-20 11:27 ` [PATCH v1 3/4] net/ntnic: unmap DMA during queue release Oleksandr Kolomeiets
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 6+ messages in thread
From: Oleksandr Kolomeiets @ 2025-06-20 11:27 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, sil-plv, ckm, stephen

Handle rx_deferred_start and tx_deferred_start flags
during configuration done in rx_queue_setup and tx_queue_setup,
so that marked queues do not start with dev_start.

Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
 drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c | 46 +++++++++++--------
 drivers/net/ntnic/include/ntos_drv.h          |  3 +-
 drivers/net/ntnic/ntnic_ethdev.c              | 22 +++++----
 drivers/net/ntnic/ntnic_mod_reg.h             | 12 +++--
 4 files changed, 52 insertions(+), 31 deletions(-)

diff --git a/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
index 0b049a8559..107fe91394 100644
--- a/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
+++ b/drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c
@@ -369,7 +369,8 @@ static struct nthw_virt_queue *nthw_setup_rx_virt_queue(nthw_dbs_t *p_nthw_dbs,
 	uint32_t host_id,
 	uint32_t header,
 	uint32_t vq_type,
-	int irq_vector)
+	int irq_vector,
+	uint8_t rx_deferred_start)
 {
 	uint32_t qs = dbs_qsize_log2(queue_size);
 	uint32_t int_enable;
@@ -430,7 +431,8 @@ static struct nthw_virt_queue *nthw_setup_rx_virt_queue(nthw_dbs_t *p_nthw_dbs,
 	 * 2. Configure the DBS.RX_AM_DATA memory and enable the queues you plan to use;
 	 *  good idea to initialize all DBS_RX_QUEUES entries.
 	 */
-	if (set_rx_am_data(p_nthw_dbs, index, (uint64_t)avail_struct_phys_addr, RX_AM_ENABLE,
+	uint32_t enable = rx_deferred_start ? RX_AM_DISABLE : RX_AM_ENABLE;
+	if (set_rx_am_data(p_nthw_dbs, index, (uint64_t)avail_struct_phys_addr, enable,
 			host_id, 0, irq_vector >= 0 ? 1 : 0) != 0) {
 		return NULL;
 	}
@@ -698,7 +700,8 @@ static struct nthw_virt_queue *nthw_setup_tx_virt_queue(nthw_dbs_t *p_nthw_dbs,
 	uint32_t header,
 	uint32_t vq_type,
 	int irq_vector,
-	uint32_t in_order)
+	uint32_t in_order,
+	uint8_t tx_deferred_start)
 {
 	uint32_t int_enable;
 	uint32_t vec;
@@ -760,8 +763,9 @@ static struct nthw_virt_queue *nthw_setup_tx_virt_queue(nthw_dbs_t *p_nthw_dbs,
 	 *            kernel).
 	 */
 	if (irq_vector < 0) {
+		uint32_t enable = tx_deferred_start ? TX_AM_DISABLE : TX_AM_ENABLE;
 		if (set_tx_am_data(p_nthw_dbs, index, (uint64_t)avail_struct_phys_addr,
-				TX_AM_ENABLE, host_id, 0, 0) != 0) {
+				enable, host_id, 0, 0) != 0) {
 			return NULL;
 		}
 	}
@@ -794,7 +798,8 @@ nthw_setup_mngd_rx_virt_queue_split(nthw_dbs_t *p_nthw_dbs,
 	uint32_t header,
 	struct nthw_memory_descriptor *p_virt_struct_area,
 	struct nthw_memory_descriptor *p_packet_buffers,
-	int irq_vector)
+	int irq_vector,
+	uint8_t rx_deferred_start)
 {
 	struct virtq_struct_layout_s virtq_struct_layout = dbs_calc_struct_layout(queue_size);
 
@@ -831,7 +836,7 @@ nthw_setup_mngd_rx_virt_queue_split(nthw_dbs_t *p_nthw_dbs,
 		virtq_struct_layout.used_offset,
 		(char *)p_virt_struct_area->phys_addr +
 		virtq_struct_layout.desc_offset,
-		(uint16_t)queue_size, host_id, header, SPLIT_RING, irq_vector);
+		(uint16_t)queue_size, host_id, header, SPLIT_RING, irq_vector, rx_deferred_start);
 
 	rxvq[index].usage = NTHW_VIRTQ_MANAGED;
 
@@ -849,7 +854,8 @@ nthw_setup_mngd_tx_virt_queue_split(nthw_dbs_t *p_nthw_dbs,
 	int irq_vector,
 	uint32_t in_order,
 	struct nthw_memory_descriptor *p_virt_struct_area,
-	struct nthw_memory_descriptor *p_packet_buffers)
+	struct nthw_memory_descriptor *p_packet_buffers,
+	uint8_t tx_deferred_start)
 {
 	struct virtq_struct_layout_s virtq_struct_layout = dbs_calc_struct_layout(queue_size);
 
@@ -889,7 +895,7 @@ nthw_setup_mngd_tx_virt_queue_split(nthw_dbs_t *p_nthw_dbs,
 		(char *)p_virt_struct_area->phys_addr +
 		virtq_struct_layout.desc_offset,
 		(uint16_t)queue_size, host_id, port, virtual_port, header,
-		SPLIT_RING, irq_vector, in_order);
+		SPLIT_RING, irq_vector, in_order, tx_deferred_start);
 
 	txvq[index].usage = NTHW_VIRTQ_MANAGED;
 
@@ -977,7 +983,8 @@ nthw_setup_managed_rx_virt_queue_packed(nthw_dbs_t *p_nthw_dbs,
 	uint32_t header,
 	struct nthw_memory_descriptor *p_virt_struct_area,
 	struct nthw_memory_descriptor *p_packet_buffers,
-	int irq_vector)
+	int irq_vector,
+	uint8_t rx_deferred_start)
 {
 	struct pvirtq_struct_layout_s pvirtq_layout;
 	struct nthw_virt_queue *vq = &rxvq[index];
@@ -996,7 +1003,7 @@ nthw_setup_managed_rx_virt_queue_packed(nthw_dbs_t *p_nthw_dbs,
 		(void *)((uintptr_t)p_virt_struct_area->phys_addr +
 			pvirtq_layout.device_event_offset),
 		p_virt_struct_area->phys_addr, (uint16_t)queue_size, host_id,
-		header, PACKED_RING, irq_vector);
+		header, PACKED_RING, irq_vector, rx_deferred_start);
 
 	vq->usage = NTHW_VIRTQ_MANAGED;
 	return vq;
@@ -1013,7 +1020,8 @@ nthw_setup_managed_tx_virt_queue_packed(nthw_dbs_t *p_nthw_dbs,
 	int irq_vector,
 	uint32_t in_order,
 	struct nthw_memory_descriptor *p_virt_struct_area,
-	struct nthw_memory_descriptor *p_packet_buffers)
+	struct nthw_memory_descriptor *p_packet_buffers,
+	uint8_t tx_deferred_start)
 {
 	struct pvirtq_struct_layout_s pvirtq_layout;
 	struct nthw_virt_queue *vq = &txvq[index];
@@ -1030,7 +1038,7 @@ nthw_setup_managed_tx_virt_queue_packed(nthw_dbs_t *p_nthw_dbs,
 		(void *)((uintptr_t)p_virt_struct_area->phys_addr +
 			pvirtq_layout.device_event_offset),
 		p_virt_struct_area->phys_addr, (uint16_t)queue_size, host_id,
-		port, virtual_port, header, PACKED_RING, irq_vector, in_order);
+		port, virtual_port, header, PACKED_RING, irq_vector, in_order, tx_deferred_start);
 
 	vq->usage = NTHW_VIRTQ_MANAGED;
 	return vq;
@@ -1052,18 +1060,19 @@ nthw_setup_mngd_rx_virt_queue(nthw_dbs_t *p_nthw_dbs,
 	struct nthw_memory_descriptor *p_virt_struct_area,
 	struct nthw_memory_descriptor *p_packet_buffers,
 	uint32_t vq_type,
-	int irq_vector)
+	int irq_vector,
+	uint8_t rx_deferred_start)
 {
 	switch (vq_type) {
 	case SPLIT_RING:
 		return nthw_setup_mngd_rx_virt_queue_split(p_nthw_dbs, index, queue_size,
 				host_id, header, p_virt_struct_area,
-				p_packet_buffers, irq_vector);
+				p_packet_buffers, irq_vector, rx_deferred_start);
 
 	case PACKED_RING:
 		return nthw_setup_managed_rx_virt_queue_packed(p_nthw_dbs, index, queue_size,
 				host_id, header, p_virt_struct_area,
-				p_packet_buffers, irq_vector);
+				p_packet_buffers, irq_vector, rx_deferred_start);
 
 	default:
 		break;
@@ -1091,7 +1100,8 @@ nthw_setup_mngd_tx_virt_queue(nthw_dbs_t *p_nthw_dbs,
 	struct nthw_memory_descriptor *p_packet_buffers,
 	uint32_t vq_type,
 	int irq_vector,
-	uint32_t in_order)
+	uint32_t in_order,
+	uint8_t tx_deferred_start)
 {
 	switch (vq_type) {
 	case SPLIT_RING:
@@ -1099,14 +1109,14 @@ nthw_setup_mngd_tx_virt_queue(nthw_dbs_t *p_nthw_dbs,
 				host_id, port, virtual_port, header,
 				irq_vector, in_order,
 				p_virt_struct_area,
-				p_packet_buffers);
+				p_packet_buffers, tx_deferred_start);
 
 	case PACKED_RING:
 		return nthw_setup_managed_tx_virt_queue_packed(p_nthw_dbs, index, queue_size,
 				host_id, port, virtual_port, header,
 				irq_vector, in_order,
 				p_virt_struct_area,
-				p_packet_buffers);
+				p_packet_buffers, tx_deferred_start);
 
 	default:
 		break;
diff --git a/drivers/net/ntnic/include/ntos_drv.h b/drivers/net/ntnic/include/ntos_drv.h
index f6ce442d17..cef3c5c277 100644
--- a/drivers/net/ntnic/include/ntos_drv.h
+++ b/drivers/net/ntnic/include/ntos_drv.h
@@ -69,7 +69,7 @@ struct __rte_cache_aligned ntnic_rx_queue {
 	nt_meta_port_type_t type;
 	uint32_t port;     /* Rx port for this queue */
 	enum fpga_info_profile profile;  /* Inline / Capture */
-
+	uint8_t rx_deferred_start;
 };
 
 struct __rte_cache_aligned ntnic_tx_queue {
@@ -89,6 +89,7 @@ struct __rte_cache_aligned ntnic_tx_queue {
 	unsigned long err_pkts;	/* Tx error packet stat */
 	int  enabled;  /* Enabling/disabling of this queue */
 	enum fpga_info_profile profile;  /* Inline / Capture */
+	uint8_t tx_deferred_start;
 };
 
 struct nt_mtr_profile {
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index d961edb903..d875e7c236 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -995,7 +995,7 @@ static int eth_rx_scg_queue_setup(struct rte_eth_dev *eth_dev,
 	uint16_t rx_queue_id,
 	uint16_t nb_rx_desc __rte_unused,
 	unsigned int socket_id __rte_unused,
-	const struct rte_eth_rxconf *rx_conf __rte_unused,
+	const struct rte_eth_rxconf *rx_conf,
 	struct rte_mempool *mb_pool)
 {
 	NT_LOG_DBGX(DBG, NTNIC, "Rx queue setup");
@@ -1029,7 +1029,8 @@ static int eth_rx_scg_queue_setup(struct rte_eth_dev *eth_dev,
 
 	mbp_priv = rte_mempool_get_priv(rx_q->mb_pool);
 	rx_q->buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
-	rx_q->enabled = 1;
+	rx_q->enabled = !rx_conf->rx_deferred_start;
+	rx_q->rx_deferred_start = rx_conf->rx_deferred_start;
 
 	if (allocate_hw_virtio_queues(eth_dev, EXCEPTION_PATH_HID, &rx_q->hwq,
 			SG_NB_HW_RX_DESCRIPTORS, SG_HW_RX_PKT_BUFFER_SIZE) < 0)
@@ -1048,7 +1049,8 @@ static int eth_rx_scg_queue_setup(struct rte_eth_dev *eth_dev,
 			&rx_q->hwq.virt_queues_ctrl,
 			rx_q->hwq.pkt_buffers,
 			SPLIT_RING,
-			-1);
+			-1,
+			rx_conf->rx_deferred_start);
 
 	NT_LOG(DBG, NTNIC, "(%" PRIu32 ") NTNIC RX OVS-SW queues successfully setup",
 		internals->port);
@@ -1060,7 +1062,7 @@ static int eth_tx_scg_queue_setup(struct rte_eth_dev *eth_dev,
 	uint16_t tx_queue_id,
 	uint16_t nb_tx_desc __rte_unused,
 	unsigned int socket_id __rte_unused,
-	const struct rte_eth_txconf *tx_conf __rte_unused)
+	const struct rte_eth_txconf *tx_conf)
 {
 	const struct port_ops *port_ops = get_port_ops();
 
@@ -1141,9 +1143,11 @@ static int eth_tx_scg_queue_setup(struct rte_eth_dev *eth_dev,
 			tx_q->hwq.pkt_buffers,
 			SPLIT_RING,
 			-1,
-			IN_ORDER);
+			IN_ORDER,
+			tx_conf->tx_deferred_start);
 
-	tx_q->enabled = 1;
+	tx_q->enabled = !tx_conf->tx_deferred_start;
+	tx_q->tx_deferred_start = tx_conf->tx_deferred_start;
 
 	NT_LOG(DBG, NTNIC, "(%" PRIu32 ") NTNIC TX OVS-SW queues successfully setup",
 		internals->port);
@@ -1365,10 +1369,12 @@ eth_dev_start(struct rte_eth_dev *eth_dev)
 	uint q;
 
 	for (q = 0; q < internals->nb_rx_queues; q++)
-		eth_rx_queue_start(eth_dev, q);
+		if (!internals->rxq_scg[q].rx_deferred_start)
+			eth_rx_queue_start(eth_dev, q);
 
 	for (q = 0; q < internals->nb_tx_queues; q++)
-		eth_tx_queue_start(eth_dev, q);
+		if (!internals->txq_scg[q].tx_deferred_start)
+			eth_tx_queue_start(eth_dev, q);
 
 	if (internals->type == PORT_TYPE_VIRTUAL || internals->type == PORT_TYPE_OVERRIDE) {
 		eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP;
diff --git a/drivers/net/ntnic/ntnic_mod_reg.h b/drivers/net/ntnic/ntnic_mod_reg.h
index 7f5bd5e0ec..26efec1c65 100644
--- a/drivers/net/ntnic/ntnic_mod_reg.h
+++ b/drivers/net/ntnic/ntnic_mod_reg.h
@@ -37,7 +37,8 @@ struct sg_ops_s {
 		uint32_t host_id,
 		uint32_t header,
 		uint32_t vq_type,
-		int irq_vector);
+		int irq_vector,
+		uint8_t rx_deferred_start);
 	struct nthw_virt_queue *(*nthw_setup_tx_virt_queue)(nthw_dbs_t *p_nthw_dbs,
 		uint32_t index,
 		uint16_t start_idx,
@@ -52,7 +53,8 @@ struct sg_ops_s {
 		uint32_t header,
 		uint32_t vq_type,
 		int irq_vector,
-		uint32_t in_order);
+		uint32_t in_order,
+		uint8_t tx_deferred_start);
 	struct nthw_virt_queue *(*nthw_setup_mngd_rx_virt_queue)(nthw_dbs_t *p_nthw_dbs,
 		uint32_t index,
 		uint32_t queue_size,
@@ -70,7 +72,8 @@ struct sg_ops_s {
 		 */
 		struct nthw_memory_descriptor *p_packet_buffers,
 		uint32_t vq_type,
-		int irq_vector);
+		int irq_vector,
+		uint8_t rx_deferred_start);
 	int (*nthw_release_mngd_rx_virt_queue)(struct nthw_virt_queue *rxvq);
 	struct nthw_virt_queue *(*nthw_setup_mngd_tx_virt_queue)(nthw_dbs_t *p_nthw_dbs,
 		uint32_t index,
@@ -92,7 +95,8 @@ struct sg_ops_s {
 		struct nthw_memory_descriptor *p_packet_buffers,
 		uint32_t vq_type,
 		int irq_vector,
-		uint32_t in_order);
+		uint32_t in_order,
+		uint8_t tx_deferred_start);
 	int (*nthw_release_mngd_tx_virt_queue)(struct nthw_virt_queue *txvq);
 	int (*nthw_switch_rx_virt_queue)(nthw_dbs_t *p_nthw_dbs, uint32_t index, uint32_t enable);
 	int (*nthw_switch_tx_virt_queue)(nthw_dbs_t *p_nthw_dbs, uint32_t index, uint32_t enable);
-- 
2.47.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v1 3/4] net/ntnic: unmap DMA during queue release
  2025-06-20 11:27 [PATCH v1 0/4] net/ntnic: implement start, stop and deferred start for Rx/Tx queues Oleksandr Kolomeiets
  2025-06-20 11:27 ` [PATCH v1 1/4] net/ntnic: implement start/stop " Oleksandr Kolomeiets
  2025-06-20 11:27 ` [PATCH v1 2/4] net/ntnic: implement deferred start " Oleksandr Kolomeiets
@ 2025-06-20 11:27 ` Oleksandr Kolomeiets
  2025-06-20 11:27 ` [PATCH v1 4/4] net/ntnic: add warning when sending on a stopped queue Oleksandr Kolomeiets
  2025-06-28 22:20 ` [PATCH v1 0/4] net/ntnic: implement start, stop and deferred start for Rx/Tx queues Stephen Hemminger
  4 siblings, 0 replies; 6+ messages in thread
From: Oleksandr Kolomeiets @ 2025-06-20 11:27 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, sil-plv, ckm, stephen

Perform unmapping in a default container, which is used by queues.
Handle multiple mappings when IOMMU is unoptimized.

Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
 drivers/net/ntnic/include/ntos_drv.h |  1 +
 drivers/net/ntnic/ntnic_ethdev.c     | 26 ++++++++++++++++++++++++--
 drivers/net/ntnic/ntnic_vfio.c       |  3 ---
 3 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ntnic/include/ntos_drv.h b/drivers/net/ntnic/include/ntos_drv.h
index cef3c5c277..047c077057 100644
--- a/drivers/net/ntnic/include/ntos_drv.h
+++ b/drivers/net/ntnic/include/ntos_drv.h
@@ -51,6 +51,7 @@ struct nthw_memory_descriptor {
 struct hwq_s {
 	int vf_num;
 	struct nthw_memory_descriptor virt_queues_ctrl;
+	struct nthw_memory_descriptor pkt_buffers_ctrl;
 	struct nthw_memory_descriptor *pkt_buffers;
 };
 
diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index d875e7c236..79ef9e7e7c 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -879,6 +879,10 @@ static int allocate_hw_virtio_queues(struct rte_eth_dev *eth_dev, int vf_num, st
 		if (res != 0)
 			return -1;
 
+		hwq->pkt_buffers_ctrl.virt_addr = virt_addr;
+		hwq->pkt_buffers_ctrl.phys_addr = (void *)iova_addr;
+		hwq->pkt_buffers_ctrl.len = size;
+
 		for (i = 0; i < num_descr; i++) {
 			hwq->pkt_buffers[i].virt_addr =
 				(void *)((char *)virt_addr + ((uint64_t)(i) * buf_size));
@@ -900,9 +904,13 @@ static int allocate_hw_virtio_queues(struct rte_eth_dev *eth_dev, int vf_num, st
 	hwq->vf_num = vf_num;
 	hwq->virt_queues_ctrl.virt_addr = virt;
 	hwq->virt_queues_ctrl.phys_addr = (void *)(iova_addr);
-	hwq->virt_queues_ctrl.len = 0x100000;
+	hwq->virt_queues_ctrl.len = ONE_G_SIZE;
 	iova_addr += 0x100000;
 
+	hwq->pkt_buffers_ctrl.virt_addr = NULL;
+	hwq->pkt_buffers_ctrl.phys_addr = NULL;
+	hwq->pkt_buffers_ctrl.len = 0;
+
 	NT_LOG(DBG, NTNIC,
 		"VFIO MMAP: virt_addr=%p phys_addr=%p size=%" PRIX32 " hpa=%" PRIX64 "",
 		hwq->virt_queues_ctrl.virt_addr, hwq->virt_queues_ctrl.phys_addr,
@@ -948,13 +956,27 @@ static int deallocate_hw_virtio_queues(struct hwq_s *hwq)
 	void *virt = hwq->virt_queues_ctrl.virt_addr;
 
 	int res = nt_vfio_dma_unmap(vf_num, hwq->virt_queues_ctrl.virt_addr,
-			(uint64_t)hwq->virt_queues_ctrl.phys_addr, ONE_G_SIZE);
+			(uint64_t)hwq->virt_queues_ctrl.phys_addr, hwq->virt_queues_ctrl.len);
 
 	if (res != 0) {
 		NT_LOG(ERR, NTNIC, "VFIO UNMMAP FAILED! res %i, vf_num %i", res, vf_num);
 		return -1;
 	}
 
+	if (hwq->pkt_buffers_ctrl.virt_addr != NULL &&
+			hwq->pkt_buffers_ctrl.phys_addr != NULL &&
+			hwq->pkt_buffers_ctrl.len > 0) {
+		int res = nt_vfio_dma_unmap(vf_num,
+				hwq->pkt_buffers_ctrl.virt_addr,
+				(uint64_t)hwq->pkt_buffers_ctrl.phys_addr,
+				hwq->pkt_buffers_ctrl.len);
+
+		if (res != 0) {
+			NT_LOG(ERR, NTNIC, "VFIO UNMMAP FAILED! res %i, vf_num %i", res, vf_num);
+			return -1;
+		}
+	}
+
 	release_hw_virtio_queues(hwq);
 	rte_free(hwq->pkt_buffers);
 	rte_free(virt);
diff --git a/drivers/net/ntnic/ntnic_vfio.c b/drivers/net/ntnic/ntnic_vfio.c
index 8d955e8342..1031b3cf67 100644
--- a/drivers/net/ntnic/ntnic_vfio.c
+++ b/drivers/net/ntnic/ntnic_vfio.c
@@ -211,9 +211,6 @@ nt_vfio_dma_unmap(int vf_num, void *virt_addr, uint64_t iova_addr, uint64_t size
 		return -1;
 	}
 
-	if (vfio->container_fd == -1)
-		return 0;
-
 	int res = rte_vfio_container_dma_unmap(vfio->container_fd, gp_virt_base, iova_addr, size);
 
 	if (res != 0) {
-- 
2.47.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH v1 4/4] net/ntnic: add warning when sending on a stopped queue
  2025-06-20 11:27 [PATCH v1 0/4] net/ntnic: implement start, stop and deferred start for Rx/Tx queues Oleksandr Kolomeiets
                   ` (2 preceding siblings ...)
  2025-06-20 11:27 ` [PATCH v1 3/4] net/ntnic: unmap DMA during queue release Oleksandr Kolomeiets
@ 2025-06-20 11:27 ` Oleksandr Kolomeiets
  2025-06-28 22:20 ` [PATCH v1 0/4] net/ntnic: implement start, stop and deferred start for Rx/Tx queues Stephen Hemminger
  4 siblings, 0 replies; 6+ messages in thread
From: Oleksandr Kolomeiets @ 2025-06-20 11:27 UTC (permalink / raw)
  To: dev; +Cc: mko-plv, sil-plv, ckm, stephen

When sending a burst of output packets on a stopped transmit queue,
the packets are written to a memory mapped address.
On queue start the packets are processed and transmitted by the NIC.

Signed-off-by: Oleksandr Kolomeiets <okl-plv@napatech.com>
---
 drivers/net/ntnic/ntnic_ethdev.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/ntnic/ntnic_ethdev.c b/drivers/net/ntnic/ntnic_ethdev.c
index 79ef9e7e7c..4145128d11 100644
--- a/drivers/net/ntnic/ntnic_ethdev.c
+++ b/drivers/net/ntnic/ntnic_ethdev.c
@@ -694,6 +694,10 @@ static uint16_t eth_dev_tx_scg(void *queue, struct rte_mbuf **bufs, uint16_t nb_
 	int pkts_sent = 0;
 	uint16_t nb_segs_arr[MAX_TX_PACKETS];
 
+	if (!tx_q->enabled)
+		NT_LOG(WRN, NTNIC, "Trying to send a burst of output packets "
+					"on a stopped transmit queue of an Ethernet device");
+
 	if (nb_pkts > MAX_TX_PACKETS)
 		nb_pkts = MAX_TX_PACKETS;
 
-- 
2.47.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH v1 0/4] net/ntnic: implement start, stop and deferred start for Rx/Tx queues
  2025-06-20 11:27 [PATCH v1 0/4] net/ntnic: implement start, stop and deferred start for Rx/Tx queues Oleksandr Kolomeiets
                   ` (3 preceding siblings ...)
  2025-06-20 11:27 ` [PATCH v1 4/4] net/ntnic: add warning when sending on a stopped queue Oleksandr Kolomeiets
@ 2025-06-28 22:20 ` Stephen Hemminger
  4 siblings, 0 replies; 6+ messages in thread
From: Stephen Hemminger @ 2025-06-28 22:20 UTC (permalink / raw)
  To: Oleksandr Kolomeiets; +Cc: dev, mko-plv, sil-plv, ckm

On Fri, 20 Jun 2025 13:27:03 +0200
Oleksandr Kolomeiets <okl-plv@napatech.com> wrote:

> This patchset includes:
>  
> 	* feature start/stop queues on HW layer.
> 	* feature deferred start for queues.
> 	* Improvement for memory mappings when IOMMU is unoptimized.
> 	* Improvement for logging
> 
> Oleksandr Kolomeiets (4):
>   net/ntnic: implement start/stop for Rx/Tx queues
>   net/ntnic: implement deferred start for Rx/Tx queues
>   net/ntnic: unmap DMA during queue release
>   net/ntnic: add warning when sending on a stopped queue
> 
>  drivers/net/ntnic/dbsconfig/ntnic_dbsconfig.c |  58 +++++---
>  drivers/net/ntnic/include/ntnic_dbs.h         |   2 +
>  drivers/net/ntnic/include/ntos_drv.h          |   4 +-
>  drivers/net/ntnic/nthw/dbs/nthw_dbs.c         |  20 +++
>  drivers/net/ntnic/ntnic_ethdev.c              | 132 ++++++++++++++++--
>  drivers/net/ntnic/ntnic_mod_reg.h             |  14 +-
>  drivers/net/ntnic/ntnic_vfio.c                |   3 -
>  7 files changed, 193 insertions(+), 40 deletions(-)
> 

Unrelated to this patch, this driver does not follow the convention about
naming external symbols. Since DPDK can be linked statically, and C does not
have namespaces; the same symbol in two places can be a problem.

The common practice is to use a common prefix for all globals in a driver.
In this driver that would be ntnic_

Doing a debug build (so symbols are visible) and running nm to display
global symbols gives:

$ nm librte_net_ntnic.a | grep ' [TD] '


0000000000000cf8 T nthw_adapter_init
00000000000038ca T nt4ga_stat_ops_init
0000000000002a11 T nthw_sg_init
0000000000002094 T nthw_link_100g_init
0000000000000000 T link_agx_100g_init
0000000000000432 T nthw_port_init
0000000000001bb4 T nim_agx_read_id
00000000000019f6 T nim_agx_setup
0000000000001781 T nthw_construct_and_preinit_nim
000000000000099b T nthw_nim_id_to_text
00000000000009f4 T nthw_nim_qsfp_plus_nim_set_tx_laser_disable
0000000000000976 T nthw_nim_state_build
00000000000018c1 T nthw_qsfp28_set_fec_enable
000000000000186c T nthw_qsfp28_set_high_power
0000000000000d59 T nthw_create_action_elements_inline
0000000000000a75 T nthw_create_attr
0000000000000b16 T nthw_create_match_elements
0000000000003455 T nthw_dev_flow_init
000000000000346b T nthw_dev_fp_flow_init
00000000000000a9 T nthw_interpret_raw_data
000000000000343f T ntnic_filter_init
0000000000000d7e T ntnic_xstats_ops_init
0000000000000039 T dbs_init
00000000000011a3 T dbs_reset
0000000000000000 T nthw_dbs_new
0000000000003470 T nthw_dbs_set_tx_qp_data
00000000000017e5 T nthw_get_rx_idle
00000000000015d9 T nthw_get_rx_init
00000000000018cf T nthw_get_tx_idle
0000000000001703 T nthw_get_tx_init
00000000000013a8 T nthw_set_rx_control
000000000000176d T nthw_set_rx_idle
0000000000001519 T nthw_set_rx_init
000000000000145f T nthw_set_tx_control
0000000000001857 T nthw_set_tx_idle
0000000000001c88 T set_rx_am_data
0000000000001cfb T set_rx_am_data_enable
0000000000002eb1 T set_rx_dr_data
00000000000024e1 T set_rx_uw_data
0000000000001fd8 T set_tx_am_data
000000000000204b T set_tx_am_data_enable
00000000000032f0 T set_tx_dr_data
0000000000001643 T set_tx_init
0000000000002a9a T set_tx_uw_data
00000000000048e0 D nthw_fpga_9563_055_049_0000
0000000000004820 D nthw_fpga_9574_055_049_0000
0000000000000000 D nthw_fpga_instances
0000000000000000 D sa_nthw_fpga_mod_str_map
000000000000001a T clk9563_ops_init
000000000000028a T nt200a0x_ops_init
00000000000008f8 T nt400dxx_ops_init
0000000000000acf T rst9563_ops_init
0000000000000dc8 T rst9574_ops_init
0000000000001b75 T rst_nt200a0x_ops_init
0000000000000f30 T rst_nt400dxx_ops_init
0000000000001433 T get_nt200a0x_ops
0000000000001467 T get_nt400dxx_ops
0000000000000431 T nthw_fpga_avr_probe
0000000000000000 T nthw_fpga_get_param_info
00000000000001fc T nthw_fpga_iic_scan
00000000000009ce T nthw_fpga_init
00000000000013e5 T nthw_fpga_shutdown
0000000000000942 T nthw_fpga_si5340_clock_synth_init_fmt2
00000000000002a4 T nthw_fpga_silabs_detect
000000000000141d T register_nt200a0x_ops
0000000000001451 T register_nt400dxx_ops
0000000000000000 T nthw_gmf_init
0000000000000551 T nthw_gmf_set_enable
000000000000058d T nthw_gmf_set_enable_tsi
0000000000000000 T nthw_gfg_init
0000000000000eff T nthw_gfg_stop
0000000000000373 T nthw_tsm_get_time
0000000000000309 T nthw_tsm_get_ts
0000000000000039 T nthw_tsm_init
0000000000000000 T nthw_tsm_new
00000000000004f3 T nthw_tsm_set_config_ts_format
00000000000003dd T nthw_tsm_set_timer_t0_enable
000000000000042d T nthw_tsm_set_timer_t0_max_count
0000000000000468 T nthw_tsm_set_timer_t1_enable
00000000000004b8 T nthw_tsm_set_timer_t1_max_count
0000000000000000 T nthw_gpio_phy_init
0000000000000408 T nthw_gpio_phy_is_module_present
000000000000045a T nthw_gpio_phy_set_low_power
0000000000000507 T nthw_gpio_phy_set_reset
0000000000000039 T nthw_hif_delete
0000000000000d57 T nthw_hif_end_point_counters_sample
00000000000009f4 T nthw_hif_force_soft_reset
0000000000000a5f T nthw_hif_get_stat
0000000000000b84 T nthw_hif_get_stat_rate
0000000000000054 T nthw_hif_init
0000000000000000 T nthw_hif_new
0000000000000db3 T nthw_hif_read_test_reg
0000000000000d0b T nthw_hif_stat_req_disable
0000000000000cbf T nthw_hif_stat_req_enable
0000000000000a34 T nthw_hif_trigger_sample_time
0000000000000ead T nthw_hif_write_test_reg
000000000000004e T nthw_i2cm_init
0000000000000015 T nthw_i2cm_new
0000000000000bb4 T nthw_i2cm_read
0000000000000c1f T nthw_i2cm_write
0000000000000c85 T nthw_i2cm_write16
0000000000000039 T nthw_igam_init
0000000000000000 T nthw_igam_new
0000000000000223 T nthw_igam_read
0000000000000325 T nthw_igam_set_ctrl_forward_rst
000000000000029f T nthw_igam_write
000000000000129b T nthw_iic_bus_ready
0000000000001323 T nthw_iic_data_ready
0000000000000a86 T nthw_iic_delete
00000000000003e7 T nthw_iic_init
00000000000003ae T nthw_iic_new
0000000000000d60 T nthw_iic_readbyte
0000000000000b34 T nthw_iic_read_data
0000000000001475 T nthw_iic_scan
00000000000013ab T nthw_iic_scan_dev_addr
0000000000000aa1 T nthw_iic_set_retry_params
0000000000001083 T nthw_iic_writebyte
0000000000000f36 T nthw_iic_write_data
000000000000180c T nthw_mac_pcs_get_fec_bypass
0000000000001858 T nthw_mac_pcs_get_fec_stat_all_am_locked
0000000000001832 T nthw_mac_pcs_get_fec_valid
0000000000002184 T nthw_mac_pcs_get_fld_block_lock_lock
00000000000021a2 T nthw_mac_pcs_get_fld_block_lock_lock_mask
00000000000021b3 T nthw_mac_pcs_get_fld_lane_lock_lock
00000000000021d1 T nthw_mac_pcs_get_fld_lane_lock_lock_mask
00000000000014ee T nthw_mac_pcs_get_hi_ber
0000000000001514 T nthw_mac_pcs_get_link_summary
0000000000000000 T nthw_mac_pcs_init
0000000000001279 T nthw_mac_pcs_is_rx_path_rst
00000000000014ad T nthw_mac_pcs_reset_bip_counters
00000000000018e1 T nthw_mac_pcs_reset_fec_counters
000000000000168a T nthw_mac_pcs_reset_required
0000000000001224 T nthw_mac_pcs_rx_path_rst
00000000000016ff T nthw_mac_pcs_set_fec
0000000000001a12 T nthw_mac_pcs_set_gty_tx_tuning
000000000000129f T nthw_mac_pcs_set_host_loopback
00000000000020d9 T nthw_mac_pcs_set_led_mode
00000000000013a6 T nthw_mac_pcs_set_line_loopback
000000000000216a T nthw_mac_pcs_set_port_no
0000000000001cda T nthw_mac_pcs_set_receiver_equalization_mode
0000000000001016 T nthw_mac_pcs_set_rx_enable
0000000000002119 T nthw_mac_pcs_set_timestamp_comp_rx
000000000000116a T nthw_mac_pcs_set_ts_eop
000000000000106b T nthw_mac_pcs_set_tx_enable
00000000000010c0 T nthw_mac_pcs_set_tx_sel_host
0000000000001115 T nthw_mac_pcs_set_tx_sel_tfg
0000000000001fc1 T nthw_mac_pcs_swap_gty_rx_polarity
0000000000001ea9 T nthw_mac_pcs_swap_gty_tx_polarity
00000000000011cf T nthw_mac_pcs_tx_path_rst
0000000000000039 T nthw_pcie3_delete
0000000000000a77 T nthw_pcie3_end_point_counters_sample_post
000000000000085b T nthw_pcie3_get_stat
000000000000091d T nthw_pcie3_get_stat_rate
0000000000000054 T nthw_pcie3_init
0000000000000000 T nthw_pcie3_new
0000000000000818 T nthw_pcie3_stat_req_disable
00000000000007d5 T nthw_pcie3_stat_req_enable
00000000000007aa T nthw_pcie3_trigger_sample_time
0000000000000082 T nthw_pca9532_init
0000000000000049 T nthw_pca9532_new
00000000000000d3 T nthw_pca9532_set_led_on
0000000000000092 T nthw_pcal6416a_init
0000000000000049 T nthw_pcal6416a_new
000000000000027e T nthw_pcal6416a_read
00000000000000e3 T nthw_pcal6416a_write
0000000000000262 T nthw_pcm_nt400dxx_get_ts_pll_locked_latch
000000000000023f T nthw_pcm_nt400dxx_get_ts_pll_locked_stat
0000000000000039 T nthw_pcm_nt400dxx_init
0000000000000000 T nthw_pcm_nt400dxx_new
0000000000000285 T nthw_pcm_nt400dxx_set_ts_pll_locked_latch
00000000000001fb T nthw_pcm_nt400dxx_set_ts_pll_recal
0000000000002868 T nthw_phy_tile_configure_fec
000000000000241a T nthw_phy_tile_get_link_summary
0000000000001a43 T nthw_phy_tile_get_no_intfs
0000000000003130 T nthw_phy_tile_get_port_status_reset_ack
0000000000003187 T nthw_phy_tile_get_port_status_tx_lanes_stable
0000000000002616 T nthw_phy_tile_get_rx_am_lock
00000000000025e2 T nthw_phy_tile_get_rx_hi_ber
0000000000003221 T nthw_phy_tile_get_sys_pll_get_rdy
00000000000032de T nthw_phy_tile_get_sys_pll_ref_clk_fgt_enabled
0000000000003259 T nthw_phy_tile_get_sys_pll_system_pll_lock
000000000000269d T nthw_phy_tile_get_timestamp_comp_rx
0000000000000039 T nthw_phy_tile_init
0000000000000000 T nthw_phy_tile_new
00000000000026e8 T nthw_phy_tile_read_eth
00000000000024fc T nthw_phy_tile_read_fec_enabled_by_scratch
0000000000001d0c T nthw_phy_tile_read_xcvr
00000000000022d7 T nthw_phy_tile_set_host_loopback
00000000000033b0 T nthw_phy_tile_set_port_config_rst
000000000000229c T nthw_phy_tile_set_rx_pol_inv
0000000000001adc T nthw_phy_tile_set_rx_reset
0000000000003291 T nthw_phy_tile_set_sys_pll_en_ref_clk_fgt
0000000000003363 T nthw_phy_tile_set_sys_pll_force_rst
0000000000003316 T nthw_phy_tile_set_sys_pll_forward_rst
00000000000031d4 T nthw_phy_tile_set_sys_pll_set_rdy
0000000000002649 T nthw_phy_tile_set_timestamp_comp_rx
000000000000234e T nthw_phy_tile_set_tx_equalization
0000000000002261 T nthw_phy_tile_set_tx_pol_inv
0000000000001bf3 T nthw_phy_tile_set_tx_reset
0000000000001a1b T nthw_phy_tile_use_phy_tile_pll_check
00000000000027a3 T nthw_phy_tile_write_eth
0000000000001e0f T nthw_phy_tile_write_xcvr
0000000000000039 T nthw_prm_nt400dxx_init
0000000000000000 T nthw_prm_nt400dxx_new
0000000000000173 T nthw_prm_nt400dxx_periph_rst
00000000000001aa T nthw_prm_nt400dxx_platform_rst
0000000000000082 T nthw_pca9849_init
0000000000000049 T nthw_pca9849_new
00000000000000b8 T nthw_pca9849_set_channel
00000000000003c8 T nthw_si5156_init
000000000000038f T nthw_si5156_new
0000000000000419 T nthw_si5156_write16
00000000000001b8 T nthw_si5332_clock_active
0000000000000167 T nthw_si5332_init
000000000000012e T nthw_si5332_new
000000000000030c T nthw_si5332_write
0000000000000262 T nthw_rpf_administrative_block
000000000000029e T nthw_rpf_block
000000000000004e T nthw_rpf_delete
000000000000037c T nthw_rpf_get_maturing_delay
00000000000003e4 T nthw_rpf_get_ts_at_eof
0000000000000069 T nthw_rpf_init
0000000000000015 T nthw_rpf_new
0000000000000345 T nthw_rpf_set_maturing_delay
00000000000003aa T nthw_rpf_set_ts_at_eof
00000000000002d2 T nthw_rpf_unblock
00000000000003f6 T nthw_rmc_block
0000000000000392 T nthw_rmc_get_dbg_merge
00000000000003c4 T nthw_rmc_get_mac_if_err
0000000000000360 T nthw_rmc_get_status_descr_fifo_of
000000000000032e T nthw_rmc_get_status_sf_ram_of
0000000000000039 T nthw_rmc_init
0000000000000000 T nthw_rmc_new
0000000000000444 T nthw_rmc_unblock
0000000000000039 T nthw_sdc_delete
000000000000034e T nthw_sdc_get_states
0000000000000054 T nthw_sdc_init
0000000000000000 T nthw_sdc_new
0000000000000569 T nthw_sdc_wait_states
00000000000003f7 T nthw_si5340_config
00000000000005a8 T nthw_si5340_config_fmt2
00000000000000b3 T nthw_si5340_delete
0000000000000039 T nthw_si5340_init
0000000000000000 T nthw_si5340_new
0000000000000447 T nthw_spim_enable
00000000000004d5 T nthw_spim_get_tx_fifo_empty
0000000000000039 T nthw_spim_init
0000000000000000 T nthw_spim_new
00000000000003fa T nthw_spim_reset
00000000000004a7 T nthw_spim_write_tx_fifo
00000000000004ea T nthw_spis_enable
000000000000054a T nthw_spis_get_rx_fifo_empty
0000000000000039 T nthw_spis_init
0000000000000000 T nthw_spis_new
000000000000057c T nthw_spis_read_rx_fifo
000000000000049d T nthw_spis_reset
000000000000023b T nthw_spi_v3_init
0000000000000000 T nthw_spi_v3_new
000000000000044e T nthw_spi_v3_transfer
0000000000000039 T nthw_stat_delete
0000000000000ec2 T nthw_stat_get_load_bps_rx
0000000000000f72 T nthw_stat_get_load_bps_tx
0000000000001022 T nthw_stat_get_load_pps_rx
00000000000010d2 T nthw_stat_get_load_pps_tx
0000000000000054 T nthw_stat_init
0000000000000000 T nthw_stat_new
0000000000000ce5 T nthw_stat_set_dma_address
0000000000000e3e T nthw_stat_trigger
0000000000000000 D dbg_res_descr
0000000000001aa1 T nthw_flow_api_create
0000000000001f1c T nthw_flow_api_done
0000000000001fc7 T nthw_flow_api_get_be_dev
0000000000000f38 T nthw_flow_delete_eth_dev
0000000000002950 T nthw_flow_get_flm_stats
00000000000029af T nthw_flow_get_ifr_stats
00000000000000a1 T nthw_flow_nic_alloc_resource
000000000000024f T nthw_flow_nic_alloc_resource_config
000000000000069a T nthw_flow_nic_deref_resource
00000000000004a6 T nthw_flow_nic_free_resource
0000000000000596 T nthw_flow_nic_ref_resource
000000000000005e T nthw_flow_nic_set_error
0000000000002a0e T nthw_init_flow_filter
0000000000002032 T sprint_nt_rss_mask
0000000000000000 T nthw_flow_group_handle_create
00000000000000ef T nthw_flow_group_handle_destroy
0000000000000153 T nthw_flow_group_translate_get
0000000000000322 T nthw_flow_group_translate_get_orig_group
000000000000014b T ntnic_id_table_create
000000000000018c T ntnic_id_table_destroy
0000000000000361 T ntnic_id_table_find
0000000000000285 T ntnic_id_table_free_id
00000000000001d7 T ntnic_id_table_get_id
0000000000000000 T nthw_callocate_mod
000000000000061b T nthw_flow_api_backend_done
000000000000037a T nthw_flow_api_backend_init
0000000000000346 T nthw_zero_module_cache
0000000000000100 T flm_age_event_clear
00000000000000b3 T flm_age_event_get
00000000000000d8 T flm_age_event_set
0000000000002680 T flm_age_queue_count
000000000000021e T flm_age_queue_create
0000000000000128 T flm_age_queue_free
00000000000001d6 T flm_age_queue_free_all
00000000000015a0 T flm_age_queue_get
00000000000026e4 T flm_age_queue_get_size
00000000000004c9 T flm_age_queue_put
0000000000000036 T flm_lrn_queue_create
000000000000006c T flm_lrn_queue_free
00000000000008da T flm_lrn_queue_get_read_buffer
0000000000000087 T flm_lrn_queue_get_write_buffer
0000000000000fc2 T flm_lrn_queue_release_read_buffer
0000000000000767 T flm_lrn_queue_release_write_buffer
0000000000003c7c T nthw_flm_inf_queue_get
00000000000018e4 T nthw_flm_inf_queue_put
000000000000028f T nthw_flm_inf_sta_queue_free_all
000000000000079a T nthw_flm_sta_queue_put
000000000000e97b T done_flow_management_of_ndev_profile_inline
0000000000010e5f T flow_actions_template_create_profile_inline
000000000001106e T flow_actions_template_destroy_profile_inline
000000000000f6e3 T flow_actions_update_profile_inline
0000000000011448 T flow_async_create_profile_inline
0000000000011c73 T flow_async_destroy_profile_inline
00000000000109f4 T flow_configure_profile_inline
000000000000ede6 T flow_create_profile_inline
000000000000f286 T flow_destroy_locked_profile_inline
000000000000f4f5 T flow_destroy_profile_inline
00000000000100cf T flow_dev_dump_profile_inline
000000000000f5be T flow_flush_profile_inline
000000000000ffad T flow_get_aged_flows_profile_inline
0000000000010424 T flow_get_flm_stats_profile_inline
0000000000010640 T flow_get_ifr_stats_profile_inline
0000000000010953 T flow_info_get_profile_inline
0000000000010cd3 T flow_pattern_template_create_profile_inline
0000000000010e18 T flow_pattern_template_destroy_profile_inline
00000000000106fb T flow_set_mtu_inline
00000000000110b5 T flow_template_table_create_profile_inline
000000000001135b T flow_template_table_destroy_profile_inline
000000000000d015 T initialize_flow_management_of_ndev_profile_inline
0000000000011d4f T profile_inline_init
0000000000005514 T hw_db_inline_action_set_add
0000000000005704 T hw_db_inline_action_set_deref
000000000000569a T hw_db_inline_action_set_ref
0000000000008294 T hw_db_inline_cat_add
0000000000008460 T hw_db_inline_cat_deref
0000000000008401 T hw_db_inline_cat_ref
000000000000583e T hw_db_inline_cot_add
00000000000059f8 T hw_db_inline_cot_deref
000000000000599b T hw_db_inline_cot_ref
0000000000000000 T hw_db_inline_create
000000000000080b T hw_db_inline_deref_idxs
000000000000064b T hw_db_inline_destroy
0000000000000c1c T hw_db_inline_dump
00000000000022c3 T hw_db_inline_dump_cfn
0000000000002385 T hw_db_inline_find_data
0000000000000bb5 T hw_db_inline_find_idx
0000000000008d4c T hw_db_inline_flm_add
00000000000092a3 T hw_db_inline_flm_deref
00000000000095bb T hw_db_inline_flm_ft_add
000000000000940a T hw_db_inline_flm_ft_default
00000000000098cd T hw_db_inline_flm_ft_deref
0000000000009817 T hw_db_inline_flm_ft_ref
0000000000009235 T hw_db_inline_flm_ref
0000000000009a91 T hw_db_inline_hsh_add
0000000000009e62 T hw_db_inline_hsh_deref
0000000000009e03 T hw_db_inline_hsh_ref
0000000000008556 T hw_db_inline_km_add
00000000000086ee T hw_db_inline_km_deref
0000000000008834 T hw_db_inline_km_ft_add
0000000000008a83 T hw_db_inline_km_ft_deref
00000000000089e4 T hw_db_inline_km_ft_ref
0000000000008695 T hw_db_inline_km_ref
0000000000004f7d T hw_db_inline_match_set_add
0000000000005290 T hw_db_inline_match_set_deref
0000000000005222 T hw_db_inline_match_set_ref
0000000000005c5e T hw_db_inline_qsl_add
0000000000006244 T hw_db_inline_qsl_deref
00000000000061fc T hw_db_inline_qsl_ref
000000000000a02a T hw_db_inline_scrub_add
000000000000a3ea T hw_db_inline_scrub_deref
000000000000a38b T hw_db_inline_scrub_ref
000000000000290f T hw_db_inline_setup_mbr_filter
00000000000064ad T hw_db_inline_slc_lr_add
000000000000672c T hw_db_inline_slc_lr_deref
00000000000066cd T hw_db_inline_slc_lr_ref
0000000000006ca7 T hw_db_inline_tpe_add
000000000000783b T hw_db_inline_tpe_deref
0000000000007b4b T hw_db_inline_tpe_ext_add
0000000000007ebc T hw_db_inline_tpe_ext_deref
0000000000007e51 T hw_db_inline_tpe_ext_ref
00000000000077dc T hw_db_inline_tpe_ref
0000000000000000 D flow_be_iface
0000000000008436 T nthw_bin_flow_backend_init
0000000000008c88 T nthw_flow_backend_init
0000000000000113 T nthw_flow_filter_done
0000000000000000 T nthw_flow_filter_init
00000000000005c1 T nthw_gethash
000000000000065f T nthw_init_hasher
0000000000000506 T hsh_set
0000000000000000 T kcc_free_ndev_resource_management
0000000000000270 T km_add_match_elem
0000000000000000 T km_attach_ndev_resource_management
00000000000032e0 T km_clear_data_match_entry
0000000000000203 T km_free_ndev_resource_management
0000000000000cc5 T km_key_compare
0000000000000555 T km_key_create
00000000000010c2 T km_rcp_set
0000000000003242 T km_write_data_match_entry
0000000000000029 T hw_mod_cat_alloc
0000000000006d3a T hw_mod_cat_cct_flush
00000000000015ce T hw_mod_cat_cfn_flush
0000000000004fd8 T hw_mod_cat_cfn_set
0000000000006667 T hw_mod_cat_cot_flush
0000000000006d07 T hw_mod_cat_cot_set
0000000000006054 T hw_mod_cat_cte_flush
00000000000062d8 T hw_mod_cat_cte_get
00000000000062a5 T hw_mod_cat_cte_set
000000000000630c T hw_mod_cat_cts_flush
0000000000006633 T hw_mod_cat_cts_get
0000000000006600 T hw_mod_cat_cts_set
0000000000006ea2 T hw_mod_cat_exo_flush
0000000000000a3d T hw_mod_cat_free
0000000000005c53 T hw_mod_cat_fte_flm_flush
000000000000600b T hw_mod_cat_fte_flm_get
0000000000005fc2 T hw_mod_cat_fte_flm_set
0000000000005c1d T hw_mod_cat_fte_km_flush
0000000000005f79 T hw_mod_cat_fte_km_get
0000000000005f30 T hw_mod_cat_fte_km_set
0000000000006df1 T hw_mod_cat_kcc_flush
000000000000523e T hw_mod_cat_kce_flm_flush
00000000000055ca T hw_mod_cat_kce_flm_get
0000000000005581 T hw_mod_cat_kce_flm_set
0000000000005208 T hw_mod_cat_kce_km_flush
0000000000005538 T hw_mod_cat_kce_km_get
00000000000054ef T hw_mod_cat_kce_km_set
0000000000005729 T hw_mod_cat_kcs_flm_flush
0000000000005ab2 T hw_mod_cat_kcs_flm_get
0000000000005a69 T hw_mod_cat_kcs_flm_set
00000000000056f3 T hw_mod_cat_kcs_km_flush
0000000000005a20 T hw_mod_cat_kcs_km_get
00000000000059d7 T hw_mod_cat_kcs_km_set
000000000000700a T hw_mod_cat_len_flush
0000000000000000 T hw_mod_cat_present
0000000000006f53 T hw_mod_cat_rck_flush
0000000000000e9b T hw_mod_cat_reset
0000000000000029 T hw_mod_flm_alloc
000000000000363d T hw_mod_flm_buf_ctrl_get
0000000000003416 T hw_mod_flm_buf_ctrl_update
0000000000000cda T hw_mod_flm_control_flush
0000000000001594 T hw_mod_flm_control_set
0000000000000be2 T hw_mod_flm_free
0000000000003d51 T hw_mod_flm_inf_sta_data_update_get
0000000000001c5d T hw_mod_flm_load_bin_flush
0000000000001dcf T hw_mod_flm_load_bin_set
0000000000003bf9 T hw_mod_flm_lrn_data_set_flush
0000000000000000 T hw_mod_flm_present
0000000000001dfb T hw_mod_flm_prio_flush
000000000000227c T hw_mod_flm_prio_set
00000000000022a8 T hw_mod_flm_pst_flush
0000000000002644 T hw_mod_flm_pst_set
0000000000002677 T hw_mod_flm_rcp_flush
00000000000033d3 T hw_mod_flm_rcp_set
000000000000338f T hw_mod_flm_rcp_set_mask
0000000000000c23 T hw_mod_flm_reset
0000000000001abc T hw_mod_flm_scan_flush
0000000000001c31 T hw_mod_flm_scan_set
0000000000002731 T hw_mod_flm_scrub_flush
000000000000418d T hw_mod_flm_scrub_set
0000000000003e9d T hw_mod_flm_scrub_timeout_decode
0000000000003f18 T hw_mod_flm_scrub_timeout_encode
000000000000369e T hw_mod_flm_stat_get
0000000000003667 T hw_mod_flm_stat_update
0000000000001a8f T hw_mod_flm_status_get
00000000000015c0 T hw_mod_flm_status_update
0000000000000029 T hw_mod_hsh_alloc
000000000000030c T hw_mod_hsh_free
0000000000000000 T hw_mod_hsh_present
00000000000003c2 T hw_mod_hsh_rcp_flush
0000000000001721 T hw_mod_hsh_rcp_set
000000000000034d T hw_mod_hsh_reset
0000000000000029 T hw_mod_km_alloc
000000000000250c T hw_mod_km_cam_flush
0000000000002edd T hw_mod_km_cam_set
00000000000006a5 T hw_mod_km_free
0000000000000000 T hw_mod_km_present
0000000000000916 T hw_mod_km_rcp_flush
00000000000024cf T hw_mod_km_rcp_get
0000000000002492 T hw_mod_km_rcp_set
00000000000006e6 T hw_mod_km_reset
0000000000002f1a T hw_mod_km_tcam_flush
000000000000347b T hw_mod_km_tcam_get
0000000000003430 T hw_mod_km_tcam_set
00000000000034c6 T hw_mod_km_tci_flush
00000000000037e3 T hw_mod_km_tci_set
0000000000003820 T hw_mod_km_tcq_flush
0000000000000029 T hw_mod_pdb_alloc
00000000000013c6 T hw_mod_pdb_config_flush
0000000000000269 T hw_mod_pdb_free
0000000000000000 T hw_mod_pdb_present
000000000000036c T hw_mod_pdb_rcp_flush
0000000000001393 T hw_mod_pdb_rcp_set
00000000000002aa T hw_mod_pdb_reset
0000000000000029 T hw_mod_qsl_alloc
0000000000000350 T hw_mod_qsl_free
0000000000000000 T hw_mod_qsl_present
00000000000014f1 T hw_mod_qsl_qen_flush
000000000000176a T hw_mod_qsl_qen_get
0000000000001737 T hw_mod_qsl_qen_set
0000000000000fa5 T hw_mod_qsl_qst_flush
00000000000014be T hw_mod_qsl_qst_set
0000000000000509 T hw_mod_qsl_rcp_flush
0000000000000f72 T hw_mod_qsl_rcp_set
0000000000000391 T hw_mod_qsl_reset
000000000000179e T hw_mod_qsl_unmq_flush
0000000000001a41 T hw_mod_qsl_unmq_set
0000000000000029 T hw_mod_slc_lr_alloc
000000000000019a T hw_mod_slc_lr_free
0000000000000000 T hw_mod_slc_lr_present
0000000000000250 T hw_mod_slc_lr_rcp_flush
0000000000000b39 T hw_mod_slc_lr_rcp_set
00000000000001db T hw_mod_slc_lr_reset
0000000000000029 T hw_mod_tpe_alloc
000000000000318a T hw_mod_tpe_cpy_rcp_flush
0000000000003878 T hw_mod_tpe_cpy_rcp_set
00000000000049f0 T hw_mod_tpe_csu_rcp_flush
00000000000050f4 T hw_mod_tpe_csu_rcp_set
00000000000006ac T hw_mod_tpe_free
00000000000038ab T hw_mod_tpe_hfu_rcp_flush
00000000000049bd T hw_mod_tpe_hfu_rcp_set
00000000000015ce T hw_mod_tpe_ifr_counters_get
000000000000159b T hw_mod_tpe_ifr_counters_set
000000000000148b T hw_mod_tpe_ifr_counters_update
0000000000001156 T hw_mod_tpe_ifr_rcp_flush
0000000000001458 T hw_mod_tpe_ifr_rcp_set
0000000000001602 T hw_mod_tpe_ins_rcp_flush
0000000000001c84 T hw_mod_tpe_ins_rcp_set
0000000000000000 T hw_mod_tpe_present
00000000000006ed T hw_mod_tpe_reset
0000000000002594 T hw_mod_tpe_rpl_ext_flush
0000000000002b81 T hw_mod_tpe_rpl_ext_set
0000000000001cb7 T hw_mod_tpe_rpl_rcp_flush
0000000000002561 T hw_mod_tpe_rpl_rcp_set
0000000000002bb4 T hw_mod_tpe_rpl_rpl_flush
0000000000003156 T hw_mod_tpe_rpl_rpl_set
0000000000000862 T hw_mod_tpe_rpp_ifr_rcp_flush
0000000000000b64 T hw_mod_tpe_rpp_ifr_rcp_set
0000000000000b97 T hw_mod_tpe_rpp_rcp_flush
0000000000001123 T hw_mod_tpe_rpp_rcp_set
00000000000024b1 T cat_nthw_cct_cnt
00000000000024db T cat_nthw_cct_color
000000000000252f T cat_nthw_cct_flush
0000000000002505 T cat_nthw_cct_km
0000000000002487 T cat_nthw_cct_select
00000000000015fc T cat_nthw_cfn_cnt
0000000000001623 T cat_nthw_cfn_enable
0000000000001acd T cat_nthw_cfn_err_cv
0000000000001af7 T cat_nthw_cfn_err_fcs
0000000000001aa3 T cat_nthw_cfn_err_inv
00000000000019a7 T cat_nthw_cfn_err_l3_cs
00000000000019d1 T cat_nthw_cfn_err_l4_cs
00000000000019fb T cat_nthw_cfn_err_tnl_l3_cs
0000000000001a25 T cat_nthw_cfn_err_tnl_l4_cs
0000000000001a79 T cat_nthw_cfn_err_tnl_ttl_exp
0000000000001b21 T cat_nthw_cfn_err_trunc
0000000000001a4f T cat_nthw_cfn_err_ttl_exp
0000000000001d54 T cat_nthw_cfn_flush
000000000000164a T cat_nthw_cfn_inv
0000000000001d00 T cat_nthw_cfn_km0_or
0000000000001d2a T cat_nthw_cfn_km1_or
0000000000001cac T cat_nthw_cfn_lc
0000000000001cd6 T cat_nthw_cfn_lc_inv
0000000000001b4b T cat_nthw_cfn_mac_port
0000000000001c2e T cat_nthw_cfn_pm_and_inv
0000000000001c04 T cat_nthw_cfn_pm_cmb
0000000000001b75 T cat_nthw_cfn_pm_cmp
0000000000001bb0 T cat_nthw_cfn_pm_dct
0000000000001bda T cat_nthw_cfn_pm_ext_inv
0000000000001c82 T cat_nthw_cfn_pm_inv
0000000000001c58 T cat_nthw_cfn_pm_or_inv
0000000000001980 T cat_nthw_cfn_ptc_cfp
00000000000017b2 T cat_nthw_cfn_ptc_frag
0000000000001671 T cat_nthw_cfn_ptc_inv
00000000000017dc T cat_nthw_cfn_ptc_ip_prot
0000000000001698 T cat_nthw_cfn_ptc_isl
00000000000016e6 T cat_nthw_cfn_ptc_l2
0000000000001788 T cat_nthw_cfn_ptc_l3
0000000000001806 T cat_nthw_cfn_ptc_l4
00000000000016bf T cat_nthw_cfn_ptc_mac
000000000000175e T cat_nthw_cfn_ptc_mpls
0000000000001902 T cat_nthw_cfn_ptc_tnl_frag
000000000000192c T cat_nthw_cfn_ptc_tnl_ip_prot
000000000000185a T cat_nthw_cfn_ptc_tnl_l2
00000000000018d8 T cat_nthw_cfn_ptc_tnl_l3
0000000000001956 T cat_nthw_cfn_ptc_tnl_l4
00000000000018ae T cat_nthw_cfn_ptc_tnl_mpls
0000000000001884 T cat_nthw_cfn_ptc_tnl_vlan
0000000000001830 T cat_nthw_cfn_ptc_tunnel
0000000000001734 T cat_nthw_cfn_ptc_vlan
000000000000170d T cat_nthw_cfn_ptc_vn_tag
00000000000015d5 T cat_nthw_cfn_select
00000000000023ca T cat_nthw_cot_cnt
00000000000023f4 T cat_nthw_cot_color
0000000000002448 T cat_nthw_cot_flush
000000000000241e T cat_nthw_cot_km
00000000000023a0 T cat_nthw_cot_select
0000000000002082 T cat_nthw_cte_cnt
00000000000020ac T cat_nthw_cte_enable_col
00000000000020d6 T cat_nthw_cte_enable_cor
0000000000002226 T cat_nthw_cte_enable_epp
0000000000002100 T cat_nthw_cte_enable_hsh
00000000000021fc T cat_nthw_cte_enable_hst
0000000000002154 T cat_nthw_cte_enable_ipf
00000000000021d2 T cat_nthw_cte_enable_msk
00000000000021a8 T cat_nthw_cte_enable_pdb
000000000000212a T cat_nthw_cte_enable_qsl
000000000000217e T cat_nthw_cte_enable_slc
0000000000002250 T cat_nthw_cte_enable_tpe
000000000000227a T cat_nthw_cte_flush
0000000000002058 T cat_nthw_cte_select
000000000000230d T cat_nthw_cts_cat_a
0000000000002337 T cat_nthw_cts_cat_b
00000000000022e3 T cat_nthw_cts_cnt
0000000000002361 T cat_nthw_cts_flush
00000000000022b9 T cat_nthw_cts_select
0000000000000039 T cat_nthw_delete
0000000000002598 T cat_nthw_exo_cnt
00000000000025c2 T cat_nthw_exo_dyn
0000000000002616 T cat_nthw_exo_flush
00000000000025ec T cat_nthw_exo_ofs
000000000000256e T cat_nthw_exo_select
0000000000001f9f T cat_nthw_fte_cnt
0000000000001fd3 T cat_nthw_fte_enable
0000000000002007 T cat_nthw_fte_flush
0000000000001f6a T cat_nthw_fte_select
0000000000000098 T cat_nthw_init
0000000000002917 T cat_nthw_kcc_category
00000000000028bb T cat_nthw_kcc_cnt
000000000000296b T cat_nthw_kcc_flush
0000000000002941 T cat_nthw_kcc_id
00000000000028e5 T cat_nthw_kcc_key
0000000000002891 T cat_nthw_kcc_select
0000000000001dc2 T cat_nthw_kce_cnt
0000000000001df6 T cat_nthw_kce_enable
0000000000001e2a T cat_nthw_kce_flush
0000000000001d8d T cat_nthw_kce_select
0000000000001ee4 T cat_nthw_kcs_category
0000000000001eaf T cat_nthw_kcs_cnt
0000000000001f19 T cat_nthw_kcs_flush
0000000000001e7b T cat_nthw_kcs_select
0000000000002756 T cat_nthw_len_cnt
00000000000027d4 T cat_nthw_len_dyn1
00000000000027fe T cat_nthw_len_dyn2
0000000000002852 T cat_nthw_len_flush
0000000000002828 T cat_nthw_len_inv
0000000000002780 T cat_nthw_len_lower
000000000000272c T cat_nthw_len_select
00000000000027aa T cat_nthw_len_upper
0000000000000000 T cat_nthw_new
000000000000267f T cat_nthw_rck_cnt
00000000000026a9 T cat_nthw_rck_data
00000000000026ed T cat_nthw_rck_flush
0000000000002655 T cat_nthw_rck_select
0000000000000071 T cat_nthw_set_debug_mode
0000000000000060 T csu_nthw_delete
0000000000000098 T csu_nthw_init
0000000000000027 T csu_nthw_new
0000000000000290 T csu_nthw_rcp_cnt
0000000000000353 T csu_nthw_rcp_flush
0000000000000305 T csu_nthw_rcp_inner_l3_cmd
000000000000032c T csu_nthw_rcp_inner_l4_cmd
00000000000002b7 T csu_nthw_rcp_outer_l3_cmd
00000000000002de T csu_nthw_rcp_outer_l4_cmd
0000000000000269 T csu_nthw_rcp_select
0000000000000000 T csu_nthw_set_debug_mode
000000000000211a T flm_nthw_buf_ctrl_update
00000000000015dd T flm_nthw_control_crcrd
00000000000015b3 T flm_nthw_control_crcwr
0000000000001631 T flm_nthw_control_eab
0000000000001406 T flm_nthw_control_enable
0000000000001685 T flm_nthw_control_flush
000000000000142d T flm_nthw_control_init
0000000000001454 T flm_nthw_control_lds
000000000000147b T flm_nthw_control_lfs
00000000000014a2 T flm_nthw_control_lis
0000000000001565 T flm_nthw_control_pds
000000000000158c T flm_nthw_control_pis
0000000000001607 T flm_nthw_control_rbl
0000000000001517 T flm_nthw_control_rds
000000000000153e T flm_nthw_control_ris
000000000000165b T flm_nthw_control_split_sdram_usage
00000000000014c9 T flm_nthw_control_uds
00000000000014f0 T flm_nthw_control_uis
0000000000000082 T flm_nthw_delete
000000000000268e T flm_nthw_inf_sta_data_update
00000000000000e1 T flm_nthw_init
0000000000001aa4 T flm_nthw_load_aps_cnt
0000000000001a82 T flm_nthw_load_aps_update
00000000000019da T flm_nthw_load_bin
0000000000001a04 T flm_nthw_load_bin_flush
0000000000001a4d T flm_nthw_load_lps_cnt
0000000000001a2b T flm_nthw_load_lps_update
00000000000022e9 T flm_nthw_lrn_data_flush
0000000000000049 T flm_nthw_new
0000000000001c29 T flm_nthw_prio_flush
0000000000001b03 T flm_nthw_prio_ft0
0000000000001b57 T flm_nthw_prio_ft1
0000000000001bab T flm_nthw_prio_ft2
0000000000001bff T flm_nthw_prio_ft3
0000000000001ad9 T flm_nthw_prio_limit0
0000000000001b2d T flm_nthw_prio_limit1
0000000000001b81 T flm_nthw_prio_limit2
0000000000001bd5 T flm_nthw_prio_limit3
0000000000001ca4 T flm_nthw_pst_bp
0000000000001c7a T flm_nthw_pst_cnt
0000000000001d22 T flm_nthw_pst_flush
0000000000001cce T flm_nthw_pst_pp
0000000000001c50 T flm_nthw_pst_select
0000000000001cf8 T flm_nthw_pst_tp
00000000000020b1 T flm_nthw_rcp_auto_ipv4_mask
0000000000002033 T flm_nthw_rcp_byt_dyn
000000000000205d T flm_nthw_rcp_byt_ofs
0000000000001d8b T flm_nthw_rcp_cnt
00000000000020db T flm_nthw_rcp_flush
0000000000002009 T flm_nthw_rcp_ipn
0000000000001fb5 T flm_nthw_rcp_kid
0000000000001db5 T flm_nthw_rcp_lookup
0000000000001f83 T flm_nthw_rcp_mask
0000000000001fdf T flm_nthw_rcp_opn
0000000000001ddf T flm_nthw_rcp_qw0_dyn
0000000000001e09 T flm_nthw_rcp_qw0_ofs
0000000000001e33 T flm_nthw_rcp_qw0_sel
0000000000001e5d T flm_nthw_rcp_qw4_dyn
0000000000001e87 T flm_nthw_rcp_qw4_ofs
0000000000001d61 T flm_nthw_rcp_select
0000000000001eb1 T flm_nthw_rcp_sw8_dyn
0000000000001edb T flm_nthw_rcp_sw8_ofs
0000000000001f05 T flm_nthw_rcp_sw8_sel
0000000000001f2f T flm_nthw_rcp_sw9_dyn
0000000000001f59 T flm_nthw_rcp_sw9_ofs
0000000000002087 T flm_nthw_rcp_txplm
00000000000019b3 T flm_nthw_scan_flush
0000000000001989 T flm_nthw_scan_i
00000000000032f4 T flm_nthw_scrub_cnt
0000000000003372 T flm_nthw_scrub_del
00000000000033c6 T flm_nthw_scrub_flush
000000000000339c T flm_nthw_scrub_inf
0000000000003348 T flm_nthw_scrub_r
00000000000032ca T flm_nthw_scrub_select
000000000000331e T flm_nthw_scrub_t
00000000000000ba T flm_nthw_set_debug_mode
0000000000002d03 T flm_nthw_stat_aul_done_cnt
0000000000002d38 T flm_nthw_stat_aul_done_update
0000000000002db1 T flm_nthw_stat_aul_fail_cnt
0000000000002de6 T flm_nthw_stat_aul_fail_update
0000000000002d5a T flm_nthw_stat_aul_ignore_cnt
0000000000002d8f T flm_nthw_stat_aul_ignore_update
0000000000003117 T flm_nthw_stat_csh_hit_cnt
000000000000314c T flm_nthw_stat_csh_hit_update
000000000000316e T flm_nthw_stat_csh_miss_cnt
00000000000031a3 T flm_nthw_stat_csh_miss_update
00000000000031c5 T flm_nthw_stat_csh_unh_cnt
00000000000031fa T flm_nthw_stat_csh_unh_update
0000000000003273 T flm_nthw_stat_cuc_move_cnt
00000000000032a8 T flm_nthw_stat_cuc_move_update
000000000000321c T flm_nthw_stat_cuc_start_cnt
0000000000003251 T flm_nthw_stat_cuc_start_update
0000000000002e5f T flm_nthw_stat_flows_cnt
0000000000002e94 T flm_nthw_stat_flows_update
0000000000002f0d T flm_nthw_stat_inf_done_cnt
0000000000002f42 T flm_nthw_stat_inf_done_update
0000000000002f64 T flm_nthw_stat_inf_skip_cnt
0000000000002f99 T flm_nthw_stat_inf_skip_update
00000000000029f4 T flm_nthw_stat_lrn_done_cnt
0000000000002a29 T flm_nthw_stat_lrn_done_update
0000000000002aa2 T flm_nthw_stat_lrn_fail_cnt
0000000000002ad7 T flm_nthw_stat_lrn_fail_update
0000000000002a4b T flm_nthw_stat_lrn_ignore_cnt
0000000000002a80 T flm_nthw_stat_lrn_ignore_update
00000000000030c0 T flm_nthw_stat_pck_dis_cnt
00000000000030f5 T flm_nthw_stat_pck_dis_update
0000000000002fbb T flm_nthw_stat_pck_hit_cnt
0000000000002ff0 T flm_nthw_stat_pck_hit_update
0000000000003012 T flm_nthw_stat_pck_miss_cnt
0000000000003047 T flm_nthw_stat_pck_miss_update
0000000000003069 T flm_nthw_stat_pck_unh_cnt
000000000000309e T flm_nthw_stat_pck_unh_update
0000000000002ba7 T flm_nthw_stat_prb_done_cnt
0000000000002bdc T flm_nthw_stat_prb_done_update
0000000000002bfe T flm_nthw_stat_prb_ignore_cnt
0000000000002c33 T flm_nthw_stat_prb_ignore_update
0000000000002c55 T flm_nthw_stat_rel_done_cnt
0000000000002c8a T flm_nthw_stat_rel_done_update
0000000000002cac T flm_nthw_stat_rel_ignore_cnt
0000000000002ce1 T flm_nthw_stat_rel_ignore_update
0000000000002eb6 T flm_nthw_stat_sta_done_cnt
0000000000002eeb T flm_nthw_stat_sta_done_update
0000000000002e08 T flm_nthw_stat_tul_done_cnt
0000000000002e3d T flm_nthw_stat_tul_done_update
0000000000002af9 T flm_nthw_stat_unl_done_cnt
0000000000002b2e T flm_nthw_stat_unl_done_update
0000000000002b50 T flm_nthw_stat_unl_ignore_cnt
0000000000002b85 T flm_nthw_stat_unl_ignore_update
00000000000018ee T flm_nthw_status_cache_buf_crit
0000000000001724 T flm_nthw_status_calib_fail
00000000000016a9 T flm_nthw_status_calib_success
0000000000001867 T flm_nthw_status_crcerr
00000000000017c3 T flm_nthw_status_critical
00000000000018b9 T flm_nthw_status_eft_bp
0000000000001940 T flm_nthw_status_flush
000000000000178e T flm_nthw_status_idle
0000000000001759 T flm_nthw_status_initdone
0000000000001815 T flm_nthw_status_panic
0000000000001967 T flm_nthw_status_update
0000000000000060 T hfu_nthw_delete
0000000000000098 T hfu_nthw_init
0000000000000027 T hfu_nthw_new
00000000000004d1 T hfu_nthw_rcp_cnt
0000000000000879 T hfu_nthw_rcp_flush
0000000000000594 T hfu_nthw_rcp_len_a_add_dyn
00000000000005bb T hfu_nthw_rcp_len_a_add_ofs
000000000000051f T hfu_nthw_rcp_len_a_ol4len
0000000000000546 T hfu_nthw_rcp_len_a_pos_dyn
000000000000056d T hfu_nthw_rcp_len_a_pos_ofs
00000000000005e2 T hfu_nthw_rcp_len_a_sub_dyn
00000000000004f8 T hfu_nthw_rcp_len_a_wr
0000000000000681 T hfu_nthw_rcp_len_b_add_dyn
00000000000006ab T hfu_nthw_rcp_len_b_add_ofs
0000000000000630 T hfu_nthw_rcp_len_b_pos_dyn
0000000000000657 T hfu_nthw_rcp_len_b_pos_ofs
00000000000006d5 T hfu_nthw_rcp_len_b_sub_dyn
0000000000000609 T hfu_nthw_rcp_len_b_wr
000000000000077d T hfu_nthw_rcp_len_c_add_dyn
00000000000007a7 T hfu_nthw_rcp_len_c_add_ofs
0000000000000729 T hfu_nthw_rcp_len_c_pos_dyn
0000000000000753 T hfu_nthw_rcp_len_c_pos_ofs
00000000000007d1 T hfu_nthw_rcp_len_c_sub_dyn
00000000000006ff T hfu_nthw_rcp_len_c_wr
00000000000004aa T hfu_nthw_rcp_select
0000000000000825 T hfu_nthw_rcp_ttl_pos_dyn
000000000000084f T hfu_nthw_rcp_ttl_pos_ofs
00000000000007fb T hfu_nthw_rcp_ttl_wr
0000000000000000 T hfu_nthw_set_debug_mode
0000000000000060 T hsh_nthw_delete
0000000000000098 T hsh_nthw_init
0000000000000027 T hsh_nthw_new
0000000000000b79 T hsh_nthw_rcp_auto_ipv4_mask
0000000000000793 T hsh_nthw_rcp_cnt
0000000000000bb3 T hsh_nthw_rcp_flush
0000000000000ad3 T hsh_nthw_rcp_hsh_type
0000000000000aa9 T hsh_nthw_rcp_hsh_valid
0000000000000b37 T hsh_nthw_rcp_k
00000000000007ba T hsh_nthw_rcp_load_dist_type
00000000000007e1 T hsh_nthw_rcp_mac_port_mask
00000000000009f9 T hsh_nthw_rcp_p_mask
0000000000000864 T hsh_nthw_rcp_qw0_ofs
000000000000083d T hsh_nthw_rcp_qw0_pe
00000000000008b2 T hsh_nthw_rcp_qw4_ofs
000000000000088b T hsh_nthw_rcp_qw4_pe
0000000000000a55 T hsh_nthw_rcp_seed
000000000000076c T hsh_nthw_rcp_select
0000000000000816 T hsh_nthw_rcp_sort
0000000000000a7f T hsh_nthw_rcp_tnl_p
0000000000000afd T hsh_nthw_rcp_toeplitz
0000000000000900 T hsh_nthw_rcp_w8_ofs
00000000000008d9 T hsh_nthw_rcp_w8_pe
0000000000000927 T hsh_nthw_rcp_w8_sort
000000000000097b T hsh_nthw_rcp_w9_ofs
00000000000009cf T hsh_nthw_rcp_w9_p
0000000000000951 T hsh_nthw_rcp_w9_pe
00000000000009a5 T hsh_nthw_rcp_w9_sort
0000000000000a23 T hsh_nthw_rcp_word_mask
0000000000000000 T hsh_nthw_set_debug_mode
0000000000000543 T ifr_nthw_counters_cnt
000000000000056d T ifr_nthw_counters_drop
0000000000000519 T ifr_nthw_counters_select
00000000000005a2 T ifr_nthw_counters_update
0000000000000060 T ifr_nthw_init
0000000000000027 T ifr_nthw_new
00000000000003c2 T ifr_nthw_rcp_cnt
00000000000004e0 T ifr_nthw_rcp_flush
000000000000041d T ifr_nthw_rcp_ipv4_df_drop
00000000000003e9 T ifr_nthw_rcp_ipv4_en
0000000000000485 T ifr_nthw_rcp_ipv6_drop
0000000000000451 T ifr_nthw_rcp_ipv6_en
00000000000004b9 T ifr_nthw_rcp_mtu
000000000000039b T ifr_nthw_rcp_select
0000000000000000 T ifr_nthw_set_debug_mode
0000000000000067 T info_nthw_delete
0000000000000879 T info_nthw_get_kcc_banks
0000000000000868 T info_nthw_get_kcc_size
0000000000000846 T info_nthw_get_ltx_avail
0000000000000857 T info_nthw_get_nb_categories
000000000000089b T info_nthw_get_nb_cat_funcs
0000000000000a17 T info_nthw_get_nb_cat_km_if_cnt
0000000000000a2b T info_nthw_get_nb_cat_km_if_m0
0000000000000a3f T info_nthw_get_nb_cat_km_if_m1
0000000000000945 T info_nthw_get_nb_flm_categories
0000000000000967 T info_nthw_get_nb_flm_entry_size
00000000000009bc T info_nthw_get_nb_flm_load_aps_max
0000000000000989 T info_nthw_get_nb_flm_prios
000000000000099a T info_nthw_get_nb_flm_pst_profiles
00000000000009ab T info_nthw_get_nb_flm_scrub_profiles
0000000000000956 T info_nthw_get_nb_flm_size_mb
0000000000000978 T info_nthw_get_nb_flm_variant
0000000000000adf T info_nthw_get_nb_hsh_categories
0000000000000af3 T info_nthw_get_nb_hsh_toeplitz
00000000000008f0 T info_nthw_get_nb_km_cam_banks
0000000000000912 T info_nthw_get_nb_km_cam_records
0000000000000901 T info_nthw_get_nb_km_cam_record_words
00000000000008df T info_nthw_get_nb_km_categories
00000000000008ac T info_nthw_get_nb_km_flow_types
0000000000000923 T info_nthw_get_nb_km_tcam_banks
0000000000000934 T info_nthw_get_nb_km_tcam_bank_width
00000000000008ce T info_nthw_get_nb_len
00000000000009ef T info_nthw_get_nb_pdb_categories
0000000000000824 T info_nthw_get_nb_phy_ports
00000000000008bd T info_nthw_get_nb_pm_ext
00000000000009cd T info_nthw_get_nb_qsl_categories
00000000000009de T info_nthw_get_nb_qsl_qst_entries
000000000000088a T info_nthw_get_nb_queues
0000000000000a03 T info_nthw_get_nb_roa_categories
0000000000000acb T info_nthw_get_nb_rpp_per_ps
0000000000000835 T info_nthw_get_nb_rx_ports
0000000000000a53 T info_nthw_get_nb_tpe_categories
0000000000000ab7 T info_nthw_get_nb_tpe_ifr_categories
0000000000000a7b T info_nthw_get_nb_tx_cpy_mask_mem
0000000000000a67 T info_nthw_get_nb_tx_cpy_writers
0000000000000a8f T info_nthw_get_nb_tx_rpl_depth
0000000000000aa3 T info_nthw_get_nb_tx_rpl_ext_categories
000000000000009f T info_nthw_init
000000000000002e T info_nthw_new
00000000000016db T km_nthw_cam_cnt
00000000000018fd T km_nthw_cam_flush
0000000000001801 T km_nthw_cam_ft0
000000000000182b T km_nthw_cam_ft1
0000000000001855 T km_nthw_cam_ft2
000000000000187f T km_nthw_cam_ft3
00000000000018a9 T km_nthw_cam_ft4
00000000000018d3 T km_nthw_cam_ft5
00000000000016b1 T km_nthw_cam_select
0000000000001705 T km_nthw_cam_w0
000000000000172f T km_nthw_cam_w1
0000000000001759 T km_nthw_cam_w2
0000000000001783 T km_nthw_cam_w3
00000000000017ad T km_nthw_cam_w4
00000000000017d7 T km_nthw_cam_w5
0000000000000060 T km_nthw_delete
0000000000000098 T km_nthw_init
0000000000000027 T km_nthw_new
00000000000013e4 T km_nthw_rcp_bank_a
000000000000140e T km_nthw_rcp_bank_b
0000000000000e6a T km_nthw_rcp_cnt
0000000000001294 T km_nthw_rcp_dual
0000000000001528 T km_nthw_rcp_dw0_b_dyn
0000000000001552 T km_nthw_rcp_dw0_b_ofs
00000000000010e6 T km_nthw_rcp_dw10_dyn
000000000000111f T km_nthw_rcp_dw10_ofs
0000000000001158 T km_nthw_rcp_dw10_sel_a
0000000000001191 T km_nthw_rcp_dw10_sel_b
000000000000157c T km_nthw_rcp_dw2_b_dyn
00000000000015a6 T km_nthw_rcp_dw2_b_ofs
0000000000000fc9 T km_nthw_rcp_dw8_dyn
000000000000103b T km_nthw_rcp_dw8_ofs
0000000000001074 T km_nthw_rcp_dw8_sel_a
00000000000010ad T km_nthw_rcp_dw8_sel_b
00000000000012e8 T km_nthw_rcp_el_a
0000000000001312 T km_nthw_rcp_el_b
0000000000001678 T km_nthw_rcp_flush
0000000000001390 T km_nthw_rcp_ftm_a
00000000000013ba T km_nthw_rcp_ftm_b
000000000000133c T km_nthw_rcp_info_a
0000000000001366 T km_nthw_rcp_info_b
000000000000148c T km_nthw_rcp_keyway_a
00000000000014c5 T km_nthw_rcp_keyway_b
0000000000001438 T km_nthw_rcp_kl_a
0000000000001462 T km_nthw_rcp_kl_b
000000000000121e T km_nthw_rcp_mask_b
0000000000001259 T km_nthw_rcp_mask_da
00000000000012be T km_nthw_rcp_paired
0000000000000e91 T km_nthw_rcp_qw0_dyn
0000000000000eb8 T km_nthw_rcp_qw0_ofs
0000000000000edf T km_nthw_rcp_qw0_sel_a
0000000000000f06 T km_nthw_rcp_qw0_sel_b
0000000000000f2d T km_nthw_rcp_qw4_dyn
0000000000000f54 T km_nthw_rcp_qw4_ofs
0000000000000f7b T km_nthw_rcp_qw4_sel_a
0000000000000fa2 T km_nthw_rcp_qw4_sel_b
0000000000000e43 T km_nthw_rcp_select
00000000000015d0 T km_nthw_rcp_sw4_b_dyn
00000000000015fa T km_nthw_rcp_sw4_b_ofs
0000000000001624 T km_nthw_rcp_sw5_b_dyn
000000000000164e T km_nthw_rcp_sw5_b_ofs
0000000000001002 T km_nthw_rcp_swx_cch
00000000000011ca T km_nthw_rcp_swx_sel_a
00000000000011f4 T km_nthw_rcp_swx_sel_b
00000000000014fe T km_nthw_rcp_synergy_mode
0000000000000000 T km_nthw_set_debug_mode
0000000000001966 T km_nthw_tcam_cnt
00000000000019c2 T km_nthw_tcam_flush
000000000000193c T km_nthw_tcam_select
0000000000001990 T km_nthw_tcam_t
0000000000001a2b T km_nthw_tci_cnt
0000000000001a55 T km_nthw_tci_color
0000000000001aa9 T km_nthw_tci_flush
0000000000001a7f T km_nthw_tci_ft
0000000000001a01 T km_nthw_tci_select
0000000000001b3c T km_nthw_tcq_bank_mask
0000000000001b12 T km_nthw_tcq_cnt
0000000000001b9f T km_nthw_tcq_flush
0000000000001b75 T km_nthw_tcq_qual
0000000000001ae8 T km_nthw_tcq_select
000000000000080a T pdb_nthw_config_flush
00000000000007e0 T pdb_nthw_config_port_ofs
00000000000007b6 T pdb_nthw_config_ts_format
0000000000000060 T pdb_nthw_delete
0000000000000098 T pdb_nthw_init
0000000000000027 T pdb_nthw_new
00000000000005b8 T pdb_nthw_rcp_align
00000000000004a7 T pdb_nthw_rcp_cnt
0000000000000591 T pdb_nthw_rcp_crc_overwrite
00000000000004f5 T pdb_nthw_rcp_desc_len
00000000000004ce T pdb_nthw_rcp_descriptor
0000000000000753 T pdb_nthw_rcp_duplicate_bit
0000000000000729 T pdb_nthw_rcp_duplicate_en
000000000000077d T pdb_nthw_rcp_flush
00000000000006d5 T pdb_nthw_rcp_ip_prot_tnl
00000000000005df T pdb_nthw_rcp_ofs0_dyn
0000000000000606 T pdb_nthw_rcp_ofs0_rel
000000000000062d T pdb_nthw_rcp_ofs1_dyn
0000000000000657 T pdb_nthw_rcp_ofs1_rel
0000000000000681 T pdb_nthw_rcp_ofs2_dyn
00000000000006ab T pdb_nthw_rcp_ofs2_rel
00000000000006ff T pdb_nthw_rcp_ppc_hsh
0000000000000480 T pdb_nthw_rcp_select
0000000000000543 T pdb_nthw_rcp_tx_ignore
000000000000056a T pdb_nthw_rcp_tx_now
000000000000051c T pdb_nthw_rcp_tx_port
0000000000000000 T pdb_nthw_set_debug_mode
0000000000000060 T qsl_nthw_delete
0000000000000098 T qsl_nthw_init
0000000000000027 T qsl_nthw_new
0000000000000b84 T qsl_nthw_qen_cnt
0000000000000bae T qsl_nthw_qen_en
0000000000000bd8 T qsl_nthw_qen_flush
0000000000000b5a T qsl_nthw_qen_select
00000000000009b5 T qsl_nthw_qst_cnt
0000000000000a09 T qsl_nthw_qst_en
0000000000000b1b T qsl_nthw_qst_flush
0000000000000a6d T qsl_nthw_qst_lre
00000000000009df T qsl_nthw_qst_queue
000000000000098b T qsl_nthw_qst_select
0000000000000aa7 T qsl_nthw_qst_tci
0000000000000a33 T qsl_nthw_qst_tx_port
0000000000000ae1 T qsl_nthw_qst_ven
000000000000079f T qsl_nthw_rcp_cnt
00000000000007c6 T qsl_nthw_rcp_discard
00000000000007ed T qsl_nthw_rcp_drop
0000000000000952 T qsl_nthw_rcp_flush
00000000000008b0 T qsl_nthw_rcp_lr
0000000000000778 T qsl_nthw_rcp_select
000000000000083b T qsl_nthw_rcp_tbl_hi
0000000000000862 T qsl_nthw_rcp_tbl_idx
0000000000000814 T qsl_nthw_rcp_tbl_lo
0000000000000889 T qsl_nthw_rcp_tbl_msk
00000000000008e4 T qsl_nthw_rcp_tsa
0000000000000918 T qsl_nthw_rcp_vli
0000000000000000 T qsl_nthw_set_debug_mode
0000000000000c41 T qsl_nthw_unmq_cnt
0000000000000c6b T qsl_nthw_unmq_dest_queue
0000000000000c95 T qsl_nthw_unmq_en
0000000000000cbf T qsl_nthw_unmq_flush
0000000000000c17 T qsl_nthw_unmq_select
0000000000000060 T rpp_lr_nthw_delete
0000000000000433 T rpp_lr_nthw_ifr_rcp_cnt
0000000000000557 T rpp_lr_nthw_ifr_rcp_flush
000000000000048e T rpp_lr_nthw_ifr_rcp_ipv4_df_drop
000000000000045a T rpp_lr_nthw_ifr_rcp_ipv4_en
00000000000004f6 T rpp_lr_nthw_ifr_rcp_ipv6_drop
00000000000004c2 T rpp_lr_nthw_ifr_rcp_ipv6_en
0000000000000530 T rpp_lr_nthw_ifr_rcp_mtu
000000000000040c T rpp_lr_nthw_ifr_rcp_select
0000000000000098 T rpp_lr_nthw_init
0000000000000027 T rpp_lr_nthw_new
0000000000000385 T rpp_lr_nthw_rcp_cnt
00000000000003ac T rpp_lr_nthw_rcp_exp
00000000000003d3 T rpp_lr_nthw_rcp_flush
000000000000035e T rpp_lr_nthw_rcp_select
0000000000000000 T rpp_lr_nthw_set_debug_mode
0000000000000060 T slc_lr_nthw_delete
0000000000000098 T slc_lr_nthw_init
0000000000000027 T slc_lr_nthw_new
00000000000002f7 T slc_lr_nthw_rcp_cnt
000000000000042f T slc_lr_nthw_rcp_flush
0000000000000345 T slc_lr_nthw_rcp_head_dyn
000000000000036c T slc_lr_nthw_rcp_head_ofs
000000000000031e T slc_lr_nthw_rcp_head_slc_en
0000000000000408 T slc_lr_nthw_rcp_pcap
00000000000002d0 T slc_lr_nthw_rcp_select
00000000000003ba T slc_lr_nthw_rcp_tail_dyn
00000000000003e1 T slc_lr_nthw_rcp_tail_ofs
0000000000000393 T slc_lr_nthw_rcp_tail_slc_en
0000000000000000 T slc_lr_nthw_set_debug_mode
0000000000000060 T tx_cpy_nthw_delete
00000000000000a8 T tx_cpy_nthw_init
0000000000000027 T tx_cpy_nthw_new
0000000000000000 T tx_cpy_nthw_set_debug_mode
000000000000118a T tx_cpy_nthw_writer_cnt
00000000000011fa T tx_cpy_nthw_writer_dyn
00000000000012a2 T tx_cpy_nthw_writer_flush
000000000000126a T tx_cpy_nthw_writer_len
0000000000001232 T tx_cpy_nthw_writer_ofs
00000000000011c2 T tx_cpy_nthw_writer_reader_select
0000000000001152 T tx_cpy_nthw_writer_select
0000000000000060 T tx_ins_nthw_delete
0000000000000098 T tx_ins_nthw_init
0000000000000027 T tx_ins_nthw_new
0000000000000283 T tx_ins_nthw_rcp_cnt
00000000000002aa T tx_ins_nthw_rcp_dyn
000000000000031f T tx_ins_nthw_rcp_flush
00000000000002f8 T tx_ins_nthw_rcp_len
00000000000002d1 T tx_ins_nthw_rcp_ofs
000000000000025c T tx_ins_nthw_rcp_select
0000000000000000 T tx_ins_nthw_set_debug_mode
0000000000000060 T tx_rpl_nthw_delete
000000000000058e T tx_rpl_nthw_ext_cnt
00000000000005df T tx_rpl_nthw_ext_flush
00000000000005b5 T tx_rpl_nthw_ext_rpl_ptr
0000000000000567 T tx_rpl_nthw_ext_select
0000000000000098 T tx_rpl_nthw_init
0000000000000027 T tx_rpl_nthw_new
000000000000041d T tx_rpl_nthw_rcp_cnt
0000000000000444 T tx_rpl_nthw_rcp_dyn
0000000000000507 T tx_rpl_nthw_rcp_eth_type_wr
00000000000004e0 T tx_rpl_nthw_rcp_ext_prio
000000000000052e T tx_rpl_nthw_rcp_flush
0000000000000492 T tx_rpl_nthw_rcp_len
000000000000046b T tx_rpl_nthw_rcp_ofs
00000000000004b9 T tx_rpl_nthw_rcp_rpl_ptr
00000000000003f6 T tx_rpl_nthw_rcp_select
0000000000000645 T tx_rpl_nthw_rpl_cnt
00000000000006a1 T tx_rpl_nthw_rpl_flush
000000000000061b T tx_rpl_nthw_rpl_select
000000000000066f T tx_rpl_nthw_rpl_value
0000000000000000 T tx_rpl_nthw_set_debug_mode
000000000000115f T nthw_meter_init
0000000000002351 T nthw_field_clr_all
0000000000002371 T nthw_field_clr_flush
00000000000022c6 T nthw_field_flush_register
0000000000001dfa T nthw_field_get_bit_pos_high
0000000000001de9 T nthw_field_get_bit_pos_low
0000000000001dd8 T nthw_field_get_bit_width
0000000000001daf T nthw_field_get_debug_mode
0000000000001e16 T nthw_field_get_mask
0000000000002210 T nthw_field_get_signed
0000000000002270 T nthw_field_get_updated
0000000000001e4b T nthw_field_get_val
00000000000021e7 T nthw_field_get_val32
0000000000001b38 T nthw_field_init
0000000000001b1c T nthw_field_new
0000000000001e27 T nthw_field_reset
00000000000023a0 T nthw_field_set_all
0000000000001dc0 T nthw_field_set_debug_mode
00000000000023c0 T nthw_field_set_flush
0000000000001fbe T nthw_field_set_val
00000000000022e9 T nthw_field_set_val32
00000000000021af T nthw_field_set_val_flush
0000000000002313 T nthw_field_set_val_flush32
00000000000022a8 T nthw_field_update_register
00000000000025fd T nthw_field_wait_clr_all32
00000000000025d2 T nthw_field_wait_set_all32
0000000000002628 T nthw_field_wait_set_any32
00000000000003a6 T nthw_fpga_extract_prod_id
00000000000003d3 T nthw_fpga_extract_rev_id
000000000000038e T nthw_fpga_extract_type_id
00000000000003bb T nthw_fpga_extract_ver_id
0000000000000aed T nthw_fpga_get_product_id
0000000000000a92 T nthw_fpga_get_product_param
0000000000000403 T nthw_fpga_mgr_delete
000000000000041e T nthw_fpga_mgr_init
0000000000000611 T nthw_fpga_mgr_log_dump
00000000000003e7 T nthw_fpga_mgr_new
0000000000000551 T nthw_fpga_mgr_query_fpga
0000000000000753 T nthw_fpga_model_init
000000000000071a T nthw_fpga_model_new
0000000000000a6a T nthw_fpga_query_module
0000000000000363 T nthw_fpga_read_buildtime
0000000000000308 T nthw_fpga_read_ident
000000000000099c T nthw_fpga_set_debug_mode
0000000000000f8a T nthw_module_get_bus
0000000000000f11 T nthw_module_get_debug_mode
0000000000000d1b T nthw_module_get_major_version
0000000000000d2c T nthw_module_get_minor_version
0000000000000e2a T nthw_module_get_register
0000000000000d3d T nthw_module_get_version_packed64
0000000000000b7b T nthw_module_init
0000000000000d63 T nthw_module_is_version_newer
0000000000000b5f T nthw_module_new
0000000000000e08 T nthw_module_query_register
0000000000000f22 T nthw_module_set_debug_mode
0000000000000b1a T nthw_param_init
0000000000000afe T nthw_param_new
0000000000001ace T nthw_register_clr
00000000000018de T nthw_register_flush
00000000000011d9 T nthw_register_get_address
00000000000013d2 T nthw_register_get_bit_width
00000000000013e3 T nthw_register_get_debug_mode
00000000000012e5 T nthw_register_get_field
00000000000015ef T nthw_register_get_val
000000000000165a T nthw_register_get_val32
000000000000180b T nthw_register_get_val_updated32
0000000000000fb7 T nthw_register_init
0000000000001847 T nthw_register_make_dirty
0000000000000f9b T nthw_register_new
00000000000012c3 T nthw_register_query_field
00000000000011ea T nthw_register_reset
00000000000013f4 T nthw_register_set_debug_mode
000000000000187c T nthw_register_set_val
000000000000168a T nthw_register_update
0000000000000000 T nthw_platform_get_nthw_adapter_id
0000000000000f95 T nthw_rac_bar0_read32
0000000000000ff9 T nthw_rac_bar0_write32
0000000000000097 T nthw_rac_init
000000000000005e T nthw_rac_new
000000000000105d T nthw_rac_rab_dma_begin
000000000000125e T nthw_rac_rab_dma_commit
000000000000246d T nthw_rac_rab_flush
0000000000001295 T nthw_rac_rab_get_free
0000000000000c61 T nthw_rac_rab_init
0000000000001d79 T nthw_rac_rab_read32
0000000000001477 T nthw_rac_rab_read32_dma
0000000000000cb5 T nthw_rac_rab_reset
0000000000000d8d T nthw_rac_rab_setup
000000000000160f T nthw_rac_rab_write32
00000000000012c2 T nthw_rac_rab_write32_dma
000000000000005f T ntlog_helper_str_add
0000000000000000 T ntlog_helper_str_alloc
0000000000000152 T ntlog_helper_str_free
0000000000000199 T nt_dma_alloc
000000000000039d T nt_dma_free
0000000000000613 T nthw_convert_link_speed
0000000000000715 T nthw_string_to_u32
00000000000006e3 T nt_link_duplex_to_eth_duplex
000000000000057f T nt_link_speed_capa_to_eth_speed_capa
00000000000004b8 T nt_link_speed_to_eth_speed_num
000000000000013e T nt_os_get_time_monotonic_counter
0000000000000107 T nt_os_wait_usec
000000000000011f T nt_os_wait_usec_poll
0000000000000149 T nt_util_align_size
0000000000000175 T nt_util_vfio_init
00000000000000b2 T get_100g_link_ops
0000000000000182 T get_adapter_ops
00000000000000e6 T get_agx_100g_link_ops
00000000000001b6 T get_clk9563_ops
000000000000038a T get_dev_flow_ops
0000000000000356 T get_dev_fp_flow_ops
00000000000002ba T get_flow_backend_ops
0000000000000322 T get_flow_filter_ops
000000000000004a T get_meter_ops
000000000000014e T get_nt4ga_stat_ops
000000000000007e T get_ntnic_filter_ops
00000000000003be T get_ntnic_xstats_ops
000000000000011a T get_port_ops
00000000000002ee T get_profile_inline_ops
000000000000021e T get_rst9563_ops
0000000000000268 T get_rst9574_ops
00000000000001ea T get_rst_nt200a0x_ops
000000000000029c T get_rst_nt400dxx_ops
0000000000000016 T get_sg_ops
000000000000009c T register_100g_link_ops
000000000000016c T register_adapter_ops
00000000000000d0 T register_agx_100g_link_ops
00000000000001a0 T register_clk9563_ops
0000000000000374 T register_dev_flow_ops
0000000000000340 T register_dev_fp_flow_ops
000000000000023c T register_flow_backend_ops
000000000000030c T register_flow_filter_ops
0000000000000034 T register_meter_ops
0000000000000138 T register_nt4ga_stat_ops
0000000000000068 T register_ntnic_filter_ops
00000000000003a8 T register_ntnic_xstats_ops
0000000000000104 T register_port_ops
00000000000002d8 T register_profile_inline_ops
0000000000000208 T register_rst9563_ops
0000000000000252 T register_rst9574_ops
00000000000001d4 T register_rst_nt200a0x_ops
0000000000000286 T register_rst_nt400dxx_ops
0000000000000000 T register_sg_ops
0000000000000449 T nt_vfio_dma_map
0000000000000652 T nt_vfio_dma_unmap
000000000000078d T nt_vfio_init
0000000000000396 T nt_vfio_remove
0000000000000067 T nt_vfio_setup
0000000000000000 T nt_vfio_vf_num

Symbols used in only one file should be declared static.

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2025-06-28 22:21 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-06-20 11:27 [PATCH v1 0/4] net/ntnic: implement start, stop and deferred start for Rx/Tx queues Oleksandr Kolomeiets
2025-06-20 11:27 ` [PATCH v1 1/4] net/ntnic: implement start/stop " Oleksandr Kolomeiets
2025-06-20 11:27 ` [PATCH v1 2/4] net/ntnic: implement deferred start " Oleksandr Kolomeiets
2025-06-20 11:27 ` [PATCH v1 3/4] net/ntnic: unmap DMA during queue release Oleksandr Kolomeiets
2025-06-20 11:27 ` [PATCH v1 4/4] net/ntnic: add warning when sending on a stopped queue Oleksandr Kolomeiets
2025-06-28 22:20 ` [PATCH v1 0/4] net/ntnic: implement start, stop and deferred start for Rx/Tx queues Stephen Hemminger

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).