[PATCH V2] net/mlx5: fix IPv6 DSCP offset in HWS sync API

[Gavin Li <gavinl@nvidia.com>]

The RTE action process in synchronous flow API with hardware steering
differs from the process in SWS. The bit shift handling for IPv6 DSCP was
not handled in HWS, resulting in incorrect data in the field.

To resolve this, bit shift handling should be added to HWS.

Fixes: ec1e7a5ceb69 ("net/mlx5: update IPv6 traffic class modification")
Cc: stable@dpdk.org
Signed-off-by: Gavin Li <gavinl@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow.h    | 5 +++++
 drivers/net/mlx5/mlx5_flow_dv.c | 6 ------
 drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++
 3 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index e8b298dd1d..fafcdccbed 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -3715,6 +3715,11 @@ void
 mlx5_indirect_list_handles_release(struct rte_eth_dev *dev);
 
 bool mlx5_flow_is_steering_disabled(void);
+static inline bool
+mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv)
+{
+	return priv->sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_OK;
+}
 
 #ifdef HAVE_MLX5_HWS_SUPPORT
 
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 95ca57e8c4..83046418c4 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1638,12 +1638,6 @@ mlx5_modify_flex_item(const struct rte_eth_dev *dev,
 	}
 }
 
-static inline bool
-mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv)
-{
-	return priv->sh->phdev->config.ipv6_tc_fallback == MLX5_IPV6_TC_OK;
-}
-
 void
 mlx5_flow_field_id_to_modify_info
 		(const struct rte_flow_field_data *data,
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 208f50fbfd..d3d2272338 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -1629,6 +1629,11 @@ flow_hw_modify_field_compile(struct rte_eth_dev *dev,
 			value = *(const uint8_t *)item.spec << 24;
 			value = rte_cpu_to_be_32(value);
 			item.spec = &value;
+		} else if (conf->dst.field == RTE_FLOW_FIELD_IPV6_DSCP &&
+			   !(mask[0] & MLX5_IPV6_HDR_ECN_MASK) &&
+			   mlx5_dv_modify_ipv6_traffic_class_supported(dev->data->dev_private)) {
+			value = *(const unaligned_uint32_t *)item.spec << MLX5_IPV6_HDR_DSCP_SHIFT;
+			item.spec = &value;
 		}
 	} else {
 		type = conf->operation == RTE_FLOW_MODIFY_SET ?
-- 
2.34.1