From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9A32BA0C4C; Tue, 12 Oct 2021 20:57:43 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 30C28410E7; Tue, 12 Oct 2021 20:57:43 +0200 (CEST) Received: from new4-smtp.messagingengine.com (new4-smtp.messagingengine.com [66.111.4.230]) by mails.dpdk.org (Postfix) with ESMTP id 3D15D410DC for ; Tue, 12 Oct 2021 20:57:42 +0200 (CEST) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.nyi.internal (Postfix) with ESMTP id A2413580CB6; Tue, 12 Oct 2021 14:57:41 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Tue, 12 Oct 2021 14:57:41 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm2; bh= mQz5g1oEfq04LT6KnHXSz/a1KMb0UqMGMxYY6gBL+ws=; b=DoLI/28EeMhsesd1 1UM+/Iw/JLepq/+rpkfRSDaKeglFQctH7HGIAlGmV36ApSRxLlNUPl4LvusmTY6m 2dPeQgHYhe7ZueDFSoakE7Mu0QxvCxwWR1rHcxGox04DwV4H/jhb0Om2Tcf7d7uV r54ide5gTFWAxhxnPZHXUvsuCpuehlnnzb3T7hetpD98R4zbJysGG7oKRdTNx8kf N0z5Ztm7DtE9Azr51Qt3bRhjpuj6oDzmKgyxdjDfQPmF6PRLfi8noaFVRB3oIM2C oCXQ0A6Oy44Nld9YrkIelFijupP8tjskcm7fGL4KYEWxwV7g9kEx4G6Q9/pz7OPn QBKbIA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; bh=mQz5g1oEfq04LT6KnHXSz/a1KMb0UqMGMxYY6gBL+ ws=; b=oCWQE7C/FYI7bQb9v56XwYLEU7ufmjn4TjLPkPYEWb3etPQ760shsahMq LZcyyG8hggwb162lpB/US6GrMNnd3Ta9o59k74vrK4REb50O74v3IWRYIE755AUT vzQWwUQnWSJOLJg1c7cKYcLYO34llN5AVrLKIDU6ajc7sHd60BITZ3d7PsObgbCq 8NyNnWZn7G4+APjtXsAqVMSDIjRUtC1iKGVMeRPCdKZnL0y2r3ts9xnp2RNGcfVN S5VvJX1GlYGSOIFEzeRG5kKmsbYIFSWyYPt2WgfwcU3b4XHD8PvUpoGgiFKktACA a5C3ApwvdkQ9Q1F9k6GBkfDpZMx8A== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrvddtkedguddvjecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfgh necuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd enucfjughrpefhvffufffkjghfggfgtgesthfuredttddtvdenucfhrhhomhepvfhhohhm rghsucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenuc ggtffrrghtthgvrhhnpedugefgvdefudfftdefgeelgffhueekgfffhfeujedtteeutdej ueeiiedvffegheenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfh hrohhmpehthhhomhgrshesmhhonhhjrghlohhnrdhnvght X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 12 Oct 2021 14:57:36 -0400 (EDT) From: Thomas Monjalon To: Chengwen Feng Cc: ferruh.yigit@intel.com, bruce.richardson@intel.com, jerinj@marvell.com, jerinjacobk@gmail.com, andrew.rybchenko@oktetlabs.ru, dev@dpdk.org, mb@smartsharesystems.com, nipun.gupta@nxp.com, hemant.agrawal@nxp.com, maxime.coquelin@redhat.com, honnappa.nagarahalli@arm.com, david.marchand@redhat.com, sburla@marvell.com, pkapoor@marvell.com, konstantin.ananyev@intel.com, conor.walsh@intel.com, kevin.laatz@intel.com Date: Tue, 12 Oct 2021 20:57:34 +0200 Message-ID: <2047369.cba7otALbc@thomas> In-Reply-To: <20211011073348.8235-3-fengchengwen@huawei.com> References: <1625231891-2963-1-git-send-email-fengchengwen@huawei.com> <20211011073348.8235-1-fengchengwen@huawei.com> <20211011073348.8235-3-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH v25 2/6] dmadev: add control plane API support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 11/10/2021 09:33, Chengwen Feng: > +Device Configuration > +~~~~~~~~~~~~~~~~~~~~ > + > +The rte_dma_configure API is used to configure a DMA device. > + > +.. code-block:: c > + > + int rte_dma_configure(int16_t dev_id, > + const struct rte_dma_conf *dev_conf); > + > +The ``rte_dma_conf`` structure is used to pass the configuration parameters > +for the DMA device. > + > + > +Configuration of Virtual DMA Channels > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > + > +The rte_dma_vchan_setup API is used to configure a virtual DMA channel. > + > +.. code-block:: c > + > + int rte_dma_vchan_setup(int16_t dev_id, uint16_t vchan, > + const struct rte_dma_vchan_conf *conf); > + > +The ``rte_dma_vchan_conf`` structure is used to pass the configuration > +parameters for the virtual DMA channel. I think those 2 above sections don't bring anything in the guide. Functions are described in Doxygen comments, it is enough. > --- a/doc/guides/rel_notes/release_21_11.rst > +++ b/doc/guides/rel_notes/release_21_11.rst > @@ -144,6 +144,7 @@ New Features > * **Introduced dmadev library with:** > > * Device allocation functions. > + * Control plane API. This is not a feature, you can drop from the release notes. [...] > +/**@{@name DMA capability > + * @see struct rte_dma_info::dev_capa > + */ Thank you for using Doxygen grouping. > +#define RTE_DMA_CAPA_MEM_TO_MEM RTE_BIT64(0) > +/**< Support memory-to-memory transfer */ Would it be possible to put the comment before the flag? > +#define RTE_DMA_CAPA_MEM_TO_DEV RTE_BIT64(1) > +/**< Support memory-to-device transfer. */ > +#define RTE_DMA_CAPA_DEV_TO_MEM RTE_BIT64(2) > +/**< Support device-to-memory transfer. */ > +#define RTE_DMA_CAPA_DEV_TO_DEV RTE_BIT64(3) > +/**< Support device-to-device transfer. */ > +#define RTE_DMA_CAPA_SVA RTE_BIT64(4) > +/**< Support SVA which could use VA as DMA address. > + * If device support SVA then application could pass any VA address like memory > + * from rte_malloc(), rte_memzone(), malloc, stack memory. > + * If device don't support SVA, then application should pass IOVA address which > + * from rte_malloc(), rte_memzone(). > + */ > +#define RTE_DMA_CAPA_SILENT RTE_BIT64(5) > +/**< Support work in silent mode. > + * In this mode, application don't required to invoke rte_dma_completed*() > + * API. > + * @see struct rte_dma_conf::silent_mode > + */ > +#define RTE_DMA_CAPA_OPS_COPY RTE_BIT64(32) > +/**< Support copy operation. > + * This capability start with index of 32, so that it could leave gap between > + * normal capability and ops capability. > + */ > +#define RTE_DMA_CAPA_OPS_COPY_SG RTE_BIT64(33) > +/**< Support scatter-gather list copy operation. */ > +#define RTE_DMA_CAPA_OPS_FILL RTE_BIT64(34) > +/**< Support fill operation. */ > +/**@}*/