From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9F9DAA0550; Wed, 10 Feb 2021 22:17:58 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 531A81CC4D5; Wed, 10 Feb 2021 22:17:58 +0100 (CET) Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by mails.dpdk.org (Postfix) with ESMTP id 182CC4069D for ; Wed, 10 Feb 2021 22:17:57 +0100 (CET) Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailout.west.internal (Postfix) with ESMTP id EDECE2DC; Wed, 10 Feb 2021 16:17:55 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Wed, 10 Feb 2021 16:17:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=fm3; bh= u4EuAjlYxlLaulOhsUuHK2HUYn6tP5Zwls/xq5yij2M=; b=wt2ERmLLff94HUY6 A+qIUC+DDL8PiIUnupUAO7l6ka2uxZM2OXpJP0xBY6UPhFWPuigPiP/A0RfCO7R5 aRD4yUJ3pP5Wkijioltd5v9f3Ba/Mr9MRc/qqB6xmRXhfUvtdYC/NGt25Qy+ddSp EVCZWRcsPKeltfIN/uXOmTmuKkND1/e/JyMK/Qft72Zr3/cabu6Gzg6A/Uu54C7h UUkfUC27S+kIiZntXAD72fcpw/zZhzmPn4BVhSMZeTQZkxVp3H7xjOrsuk69YVtL 2SGSRUsF5BmchxhuwSrYlAiJF/QlMGmcHJlMNDhPjPPfC1P1P4byPwD9h8jeFg3N N+24SA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; bh=u4EuAjlYxlLaulOhsUuHK2HUYn6tP5Zwls/xq5yij 2M=; b=oZofEIlEGBg1FfqUECaFjtawk2gZWmong803QYCGZOOHHV4aq2b8cTS90 JT3aIK+/woQe6By+gaPq0Tx9ghqZBwJevLFanreme5nx95WhAtYCXAtVan5/7Zor YBhnGW5GZODpyB38zgjCVyZM+QbbxtDrrgyJEpExNVMS3yQQu1G9+O8eF4ZgEwVw 16cY+gePpZJhq0sW8a5kRl1AiUOL8oaE4G4h4gsfS5ZWugRzO545tHfj0KGHDOLg dln6TCMIQ7w+ENC3MMxpRYwoNCHHkLizN5iXbAbdZiAcejWWX6F4hIDGvAtu3hvQ d1ku1Par2FYFTh8DEsB8ikFmF9aRg== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrheejgddugeegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkfgjfhgggfgtsehtufertddttddvnecuhfhrohhmpefvhhhomhgr shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecugg ftrfgrthhtvghrnhepudeggfdvfeduffdtfeeglefghfeukefgfffhueejtdetuedtjeeu ieeivdffgeehnecukfhppeejjedrudefgedrvddtfedrudekgeenucevlhhushhtvghruf hiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehthhhomhgrshesmhhonhhjrghl ohhnrdhnvght X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id EB0AC108005F; Wed, 10 Feb 2021 16:17:54 -0500 (EST) From: Thomas Monjalon To: Matan Azrad Cc: Maxime Coquelin , "dev@dpdk.org" , "Xueming(Steven) Li" Date: Wed, 10 Feb 2021 22:17:53 +0100 Message-ID: <2087811.Wx4xBajQNY@thomas> In-Reply-To: References: <1612776481-151396-1-git-send-email-matan@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH] vdpa/mlx5: fix polling threads scheduling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > >> When the event mode is with 0 fixed delay, the polling-thread will > >> never give-up CPU. > >> > >> So, when multi-polling-threads are active, the context-switch between > >> them will be managed by the system which may affect latency according > >> to the time-out decided by the system. > >> > >> In order to fix multi-devices polling thread scheduling, this patch > >> forces rescheduling for each CQ poll iteration. > >> > >> Move the polling thread to SCHED_RR mode with maximum priority to > >> complete the fairness. > >> > >> Fixes: 6956a48cabbb ("vdpa/mlx5: set polling mode default delay to > >> zero") > >> > >> Signed-off-by: Matan Azrad > > > > Reviewed-by: Maxime Coquelin > > Acked-by: Xueming Li converted to nvidia.com Applied, thanks