From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by dpdk.org (Postfix) with ESMTP id 86AE51B331 for ; Mon, 12 Feb 2018 14:55:34 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 0241D21623; Mon, 12 Feb 2018 08:55:34 -0500 (EST) Received: from frontend1 ([10.202.2.160]) by compute1.internal (MEProxy); Mon, 12 Feb 2018 08:55:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc; s=mesmtp; bh=EhA9Ui1cjapU8ayKXPUjn4NVYU zUoK5zjshszWOPFQA=; b=kp5s6PlDhD/RVDmTlVgKYAK1kEz7hgyToSI4YIBbOS PmpWhUNVBc3gaIm2r8NS99WyGkH/A9LKH6m134dioAlDdtCUJptbyVdjOWhq4ncP rQF0ugRofBaT9XBt48JZMAftE79akdaMNKFLk6/YhOp7LAuS4qgV7Ov3mIH5iLE+ A= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc; s=fm2; bh=EhA9Ui 1cjapU8ayKXPUjn4NVYUzUoK5zjshszWOPFQA=; b=A9OS8SYiHnwqzISzxloFd2 9IH+wgj1Ccrug/SzIxsbFbAk4Jkn2ZW1n8gRz1BWul+DncI+aEEquLZumtLwsJkk XO/pb/gliuSdLYdndWN6oBI+Xmk2YJRLVbLsDlOSkWjNGZ7gNJWtsyIceUyMvW5B 0jfH8yLo47HH6W3AOxldQ9f7GH3nkXX8XwBxm+/vY37V9By1QVAOMnVFzJWL0gfx roXlU4UJxA5qnK65JuRSZhg1JtAmdDFOHbFXtotiLjrU0mN4mNOff+OZSw0v3SYP MWU731TEV0l9xF6rhlNGB0CWqpPdhXsII8ovaIt0+rDUNDklKciN0gOMlsAC6fFA == X-ME-Sender: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 9B47F7E137; Mon, 12 Feb 2018 08:55:33 -0500 (EST) From: Thomas Monjalon To: Qi Zhang Cc: dev@dpdk.org, jingjing.wu@intel.com, beilei.xing@intel.com, arybchenko@solarflare.com, konstantin.ananyev@intel.com Date: Mon, 12 Feb 2018 14:55:24 +0100 Message-ID: <2148652.5DtpRIH0Mh@xps> In-Reply-To: <20180212045314.171616-2-qi.z.zhang@intel.com> References: <20180212045314.171616-1-qi.z.zhang@intel.com> <20180212045314.171616-2-qi.z.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Subject: Re: [dpdk-dev] [PATCH 1/4] ether: support deferred queue setup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Feb 2018 13:55:34 -0000 As a general comment, please review wording and explanations of this patchset. 12/02/2018 05:53, Qi Zhang: > +/** < Deferred queue setup / release capability */ > +#define DEV_DEFERRED_RX_QUEUE_SETUP 0x00000001 > +#define DEV_DEFERRED_TX_QUEUE_SETUP 0x00000002 > +#define DEV_DEFERRED_RX_QUEUE_RELEASE 0x00000004 > +#define DEV_DEFERRED_TX_QUEUE_RELEASE 0x00000008 Please document each value. > @@ -1029,6 +1035,8 @@ struct rte_eth_dev_info { > /** Configured number of rx/tx queues */ > uint16_t nb_rx_queues; /**< Number of RX queues. */ > uint16_t nb_tx_queues; /**< Number of TX queues. */ > + uint64_t deferred_queue_config_capa; > + /**< a queue can be setup/release after dev_start */ Please refer to DEV_DEFERRED_* flags.