Re: [dpdk-dev] [PATCH 2/3] net/mlx5: fix compilation issue with atomic128 exchange

[Thomas Monjalon <thomas@monjalon.net>]

17/07/2020 16:28, Viacheslav Ovsiienko:
> For naw the rte_atomic128_cmp_exchange() is available on x86-64

Typo: now

> and ARM64 architectures. The patch fixes the compilation condition
> for the code using this atomic transaction.

What is fixed exactly?
How "not (ppc or 32)" is different of "x86_64 or arm64"?

> -#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_32)
> +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64)
> +	rte_int128_t src;
> +
> +	memset(&src, 0, sizeof(src));
> +	*ts = src;
> +	/* if (*from == *ts) *from = *src else *ts = *from; */
> +	rte_atomic128_cmp_exchange(from, ts, &src, 0,
> +				   __ATOMIC_RELAXED, __ATOMIC_RELAXED);
> +#else
>  	rte_atomic64_t *cqe = (rte_atomic64_t *)from;
>  
>  	/* Power architecture does not support 16B compare-and-swap. */
> @@ -665,14 +673,6 @@
>  		ps[1] = op;
>  		return;
>  	}
> -#else
> -	rte_int128_t src;
> -
> -	memset(&src, 0, sizeof(src));
> -	*ts = src;
> -	/* if (*from == *ts) *from = *src else *ts = *from; */
> -	rte_atomic128_cmp_exchange(from, ts, &src, 0,
> -				   __ATOMIC_RELAXED, __ATOMIC_RELAXED);
>  #endif