From: Thomas Monjalon <thomas@monjalon.net>
To: Shun Hao <shunh@nvidia.com>
Cc: viacheslavo@nvidia.com, matan@nvidia.com, orika@nvidia.com,
Bing Zhao <bingz@nvidia.com>,
dev@dpdk.org, rasland@nvidia.com
Subject: Re: [PATCH v1] net/mlx5: fix action flag data type
Date: Mon, 14 Nov 2022 12:00:57 +0100 [thread overview]
Message-ID: <22857477.6Emhk5qWAg@thomas> (raw)
In-Reply-To: <20221101100724.3190709-1-shunh@nvidia.com>
01/11/2022 11:07, Shun Hao:
> This patch fixes this by making all action flags definition as 64-bit
> data type.
No, it is defining as unsigned long long.
[...]
> /* Actions */
> -#define MLX5_FLOW_ACTION_DROP (1u << 0)
> -#define MLX5_FLOW_ACTION_QUEUE (1u << 1)
> -#define MLX5_FLOW_ACTION_RSS (1u << 2)
> -#define MLX5_FLOW_ACTION_FLAG (1u << 3)
> -#define MLX5_FLOW_ACTION_MARK (1u << 4)
> -#define MLX5_FLOW_ACTION_COUNT (1u << 5)
> -#define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
> -#define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
> -#define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
> -#define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
> -#define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
> -#define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
> -#define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
> -#define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
> -#define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
> -#define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
> -#define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
> -#define MLX5_FLOW_ACTION_JUMP (1u << 17)
> -#define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
> -#define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
> -#define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
> -#define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
> -#define MLX5_FLOW_ACTION_ENCAP (1u << 22)
> -#define MLX5_FLOW_ACTION_DECAP (1u << 23)
> -#define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
> -#define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
> -#define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
> -#define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
> +#define MLX5_FLOW_ACTION_DROP (1ull << 0)
> +#define MLX5_FLOW_ACTION_QUEUE (1ull << 1)
> +#define MLX5_FLOW_ACTION_RSS (1ull << 2)
> +#define MLX5_FLOW_ACTION_FLAG (1ull << 3)
> +#define MLX5_FLOW_ACTION_MARK (1ull << 4)
> +#define MLX5_FLOW_ACTION_COUNT (1ull << 5)
> +#define MLX5_FLOW_ACTION_PORT_ID (1ull << 6)
> +#define MLX5_FLOW_ACTION_OF_POP_VLAN (1ull << 7)
> +#define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1ull << 8)
> +#define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1ull << 9)
> +#define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1ull << 10)
> +#define MLX5_FLOW_ACTION_SET_IPV4_SRC (1ull << 11)
> +#define MLX5_FLOW_ACTION_SET_IPV4_DST (1ull << 12)
> +#define MLX5_FLOW_ACTION_SET_IPV6_SRC (1ull << 13)
> +#define MLX5_FLOW_ACTION_SET_IPV6_DST (1ull << 14)
> +#define MLX5_FLOW_ACTION_SET_TP_SRC (1ull << 15)
> +#define MLX5_FLOW_ACTION_SET_TP_DST (1ull << 16)
> +#define MLX5_FLOW_ACTION_JUMP (1ull << 17)
> +#define MLX5_FLOW_ACTION_SET_TTL (1ull << 18)
> +#define MLX5_FLOW_ACTION_DEC_TTL (1ull << 19)
> +#define MLX5_FLOW_ACTION_SET_MAC_SRC (1ull << 20)
> +#define MLX5_FLOW_ACTION_SET_MAC_DST (1ull << 21)
> +#define MLX5_FLOW_ACTION_ENCAP (1ull << 22)
> +#define MLX5_FLOW_ACTION_DECAP (1ull << 23)
> +#define MLX5_FLOW_ACTION_INC_TCP_SEQ (1ull << 24)
> +#define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1ull << 25)
> +#define MLX5_FLOW_ACTION_INC_TCP_ACK (1ull << 26)
> +#define MLX5_FLOW_ACTION_DEC_TCP_ACK (1ull << 27)
> #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
> #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
> #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
The correct fix would be to use the macro RTE_BIT64.
Please can you convert the whole mlx5 to avoid using such unclear bit shifts?
prev parent reply other threads:[~2022-11-14 11:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 10:07 Shun Hao
2022-11-03 11:41 ` Raslan Darawsheh
2022-11-14 11:00 ` Thomas Monjalon [this message]
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