From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B51B6A00C4; Mon, 14 Nov 2022 12:01:01 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 957DF40150; Mon, 14 Nov 2022 12:01:01 +0100 (CET) Received: from out5-smtp.messagingengine.com (out5-smtp.messagingengine.com [66.111.4.29]) by mails.dpdk.org (Postfix) with ESMTP id C4BBB4014F for ; Mon, 14 Nov 2022 12:01:00 +0100 (CET) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id E40E45C0136; Mon, 14 Nov 2022 06:00:59 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Mon, 14 Nov 2022 06:00:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1668423659; x= 1668510059; bh=uU+i0jojbZHGxcLdSWEWXc7OKz0eBGuQ6pjgZmAjWI4=; b=P IazNr0hcsCbORRtvoWU0tGV2YkZc4ElrxRDFiGNz6DWYCx17EVqcVKiDYhHPQh9k ZtTOYy/wATHFUERn60aTQuXF+VhSco6iuXus5p5khZ0yZarym6ehYi/nx+Ijw7BV h/M7MKNup4JDJkVAkYp2nC1tFQLFQu59A7nIKlK+9Wtx2yLCFHURCwXdpTrjdDrY My2ZPofNGMqVAb4Lu0NnPJORyqqOV9jG+M9PUtmCdCmeUD2+y1KRNRnSPb7AdjaF OiUN7cnGzse+3NZySxgHhnXdMCJId6yWZlQdczVR4J8lX30v+YlG4jLitigGjTen 4ie04QFuhrrTHkE2bdh5A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t=1668423659; x= 1668510059; bh=uU+i0jojbZHGxcLdSWEWXc7OKz0eBGuQ6pjgZmAjWI4=; b=A 3kT4x2UxbDLSUuVF8OdjAGDuCnixzuLO9O7Ha/KPHEOgCLt+xIicyLsHi/MN8Lp5 NVz4+wwl46ELjwQ86gGnxBLt37YHH7oHDQLj89jdO9xFnd/WFz70kUmseaFK4EGt MPyqr4z5LtOT6HdNpFVc8Kopyy/RZsU8IK/oxaTiWntdM0qCQjtvDH9BxrXJ45vZ tNWgQp6IMOHQ0UuUQL59IdQB59+mmNxxg2KF91pr7iLOO+AjjIrZj76KHSQGUIrc QteOGrlSzGkXQAXE5PT7rLrAKwEth7JYZH9Za27wC/qyposYaV+qQKUMP+Bj+GOo LzFWbk8r7JN1ngQMlfXeg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvgedrgedugdduhedvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkjghfggfgtgesthfuredttddtvdenucfhrhhomhepvfhhohhm rghsucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenuc ggtffrrghtthgvrhhnpedtjeeiieefhedtfffgvdelteeufeefheeujefgueetfedttdei kefgkeduhedtgfenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfh hrohhmpehthhhomhgrshesmhhonhhjrghlohhnrdhnvght X-ME-Proxy: Feedback-ID: i47234305:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 14 Nov 2022 06:00:58 -0500 (EST) From: Thomas Monjalon To: Shun Hao Cc: viacheslavo@nvidia.com, matan@nvidia.com, orika@nvidia.com, Bing Zhao , dev@dpdk.org, rasland@nvidia.com Subject: Re: [PATCH v1] net/mlx5: fix action flag data type Date: Mon, 14 Nov 2022 12:00:57 +0100 Message-ID: <22857477.6Emhk5qWAg@thomas> In-Reply-To: <20221101100724.3190709-1-shunh@nvidia.com> References: <20221101100724.3190709-1-shunh@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 01/11/2022 11:07, Shun Hao: > This patch fixes this by making all action flags definition as 64-bit > data type. No, it is defining as unsigned long long. [...] > /* Actions */ > -#define MLX5_FLOW_ACTION_DROP (1u << 0) > -#define MLX5_FLOW_ACTION_QUEUE (1u << 1) > -#define MLX5_FLOW_ACTION_RSS (1u << 2) > -#define MLX5_FLOW_ACTION_FLAG (1u << 3) > -#define MLX5_FLOW_ACTION_MARK (1u << 4) > -#define MLX5_FLOW_ACTION_COUNT (1u << 5) > -#define MLX5_FLOW_ACTION_PORT_ID (1u << 6) > -#define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7) > -#define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8) > -#define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9) > -#define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10) > -#define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11) > -#define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12) > -#define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13) > -#define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14) > -#define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15) > -#define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16) > -#define MLX5_FLOW_ACTION_JUMP (1u << 17) > -#define MLX5_FLOW_ACTION_SET_TTL (1u << 18) > -#define MLX5_FLOW_ACTION_DEC_TTL (1u << 19) > -#define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20) > -#define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21) > -#define MLX5_FLOW_ACTION_ENCAP (1u << 22) > -#define MLX5_FLOW_ACTION_DECAP (1u << 23) > -#define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24) > -#define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25) > -#define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26) > -#define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27) > +#define MLX5_FLOW_ACTION_DROP (1ull << 0) > +#define MLX5_FLOW_ACTION_QUEUE (1ull << 1) > +#define MLX5_FLOW_ACTION_RSS (1ull << 2) > +#define MLX5_FLOW_ACTION_FLAG (1ull << 3) > +#define MLX5_FLOW_ACTION_MARK (1ull << 4) > +#define MLX5_FLOW_ACTION_COUNT (1ull << 5) > +#define MLX5_FLOW_ACTION_PORT_ID (1ull << 6) > +#define MLX5_FLOW_ACTION_OF_POP_VLAN (1ull << 7) > +#define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1ull << 8) > +#define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1ull << 9) > +#define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1ull << 10) > +#define MLX5_FLOW_ACTION_SET_IPV4_SRC (1ull << 11) > +#define MLX5_FLOW_ACTION_SET_IPV4_DST (1ull << 12) > +#define MLX5_FLOW_ACTION_SET_IPV6_SRC (1ull << 13) > +#define MLX5_FLOW_ACTION_SET_IPV6_DST (1ull << 14) > +#define MLX5_FLOW_ACTION_SET_TP_SRC (1ull << 15) > +#define MLX5_FLOW_ACTION_SET_TP_DST (1ull << 16) > +#define MLX5_FLOW_ACTION_JUMP (1ull << 17) > +#define MLX5_FLOW_ACTION_SET_TTL (1ull << 18) > +#define MLX5_FLOW_ACTION_DEC_TTL (1ull << 19) > +#define MLX5_FLOW_ACTION_SET_MAC_SRC (1ull << 20) > +#define MLX5_FLOW_ACTION_SET_MAC_DST (1ull << 21) > +#define MLX5_FLOW_ACTION_ENCAP (1ull << 22) > +#define MLX5_FLOW_ACTION_DECAP (1ull << 23) > +#define MLX5_FLOW_ACTION_INC_TCP_SEQ (1ull << 24) > +#define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1ull << 25) > +#define MLX5_FLOW_ACTION_INC_TCP_ACK (1ull << 26) > +#define MLX5_FLOW_ACTION_DEC_TCP_ACK (1ull << 27) > #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28) > #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29) > #define MLX5_FLOW_ACTION_SET_META (1ull << 30) The correct fix would be to use the macro RTE_BIT64. Please can you convert the whole mlx5 to avoid using such unclear bit shifts?