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From: Thomas Monjalon <thomas@monjalon.net>
To: "Xueming(Steven) Li" <xuemingl@nvidia.com>
Cc: dev@dpdk.org, "stable@dpdk.org" <stable@dpdk.org>,
	Slava Ovsiienko <viacheslavo@nvidia.com>
Subject: Re: [dpdk-dev] [PATCH v2] net/mlx5: fix LAG representor probe on PF1 PCI
Date: Wed, 12 May 2021 12:35:58 +0200	[thread overview]
Message-ID: <2288344.hZCFdvDj1X@thomas> (raw)
In-Reply-To: <DM6PR12MB375371BC4FEAF1F80EA39299DF539@DM6PR12MB3753.namprd12.prod.outlook.com>

> > In case of bonding, orchestrator wants to use same devargs for LAG and non-
> > LAG scenario to probe representor on PF1 using PF1 PCI address like
> > "<DBDF_PF1>,representor=pf1vf[0-3]".
> > 
> > This patch changes PCI address check policy to allow PF1 PCI address for
> > representors on PF1.
> > 
> > Note: detaching PF0 device can't remove representors on PF1. It's
> > recommended to use primary(PF0) PCI address to probe representors on
> > both PFs.
> > 
> > Fixes: f926cce3fa94 ("net/mlx5: refactor bonding representor probing")
> > 
> > Cc: stable@dpdk.org
> > Signed-off-by: Xueming Li <xuemingl@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

Applied to next-net-mlx, thanks.



      reply	other threads:[~2021-05-12 10:36 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-22  7:24 [dpdk-dev] [PATCH] net/mlx5: probe LAG representor with PF1 PCI address Xueming Li
2021-05-06 11:27 ` Slava Ovsiienko
2021-05-10 13:13 ` [dpdk-dev] [PATCH v2] net/mlx5: fix LAG representor probe on PF1 PCI Xueming Li
2021-05-11  7:44   ` Slava Ovsiienko
2021-05-12 10:35     ` Thomas Monjalon [this message]

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