DPDK patches and discussions
 help / color / mirror / Atom feed
From: Yongseok Koh <yskoh@mellanox.com>
To: Ferruh Yigit <ferruh.yigit@intel.com>
Cc: Shahaf Shuler <shahafs@mellanox.com>, "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH v4 3/4] net/mlx5: remove device register remap
Date: Wed, 10 Apr 2019 19:12:50 +0000	[thread overview]
Message-ID: <235F78D4-58FC-4A3A-AD43-0DC051EB89FF@mellanox.com> (raw)
In-Reply-To: <69b151d0-f21d-8b5c-89d3-3ceada5a7126@intel.com>


> On Apr 10, 2019, at 10:50 AM, Ferruh Yigit <ferruh.yigit@intel.com> wrote:
> 
> On 4/10/2019 12:13 AM, Yongseok Koh wrote:
>> UAR (User Access Region) register does not need to be remapped for primary
>> process but it should be remapped only for secondary process. UAR register
>> table is in the process private structure in rte_eth_devices[],
>> 	(struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private
>> 
>> The actual UAR table follows the data structure and the table is used for
>> both Tx and Rx.
>> 
>> For Tx, BlueFlame in UAR is used to ring the doorbell. MLX5_TX_BFREG(txq)
>> is defined to get a register for the txq. Processes access its own private
>> data to acquire the register from the UAR table.
>> 
>> For Rx, the doorbell in UAR is required in arming CQ event. However, it is
>> a known issue that the register isn't remapped for secondary process.
>> 
>> Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
> 
> <...>
> 
>> @@ -229,13 +229,99 @@ mlx5_tx_queue_release(void *dpdk_txq)
>> 		}
>> }
>> 
>> +/**
>> + * Initialize Tx UAR registers for primary process.
>> + *
>> + * @param txq_ctrl
>> + *   Pointer to Tx queue control structure.
>> + */
>> +static void
>> +txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
>> +{
>> +	struct mlx5_priv *priv = txq_ctrl->priv;
>> +	struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
>> +
>> +	assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
>> +	assert(ppriv);
>> +	ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
>> +#ifndef RTE_ARCH_64
>> +	struct mlx5_priv *priv = txq_ctrl->priv;
>> +	struct mlx5_txq_data *txq = &txq_ctrl->txq;
>> +	unsigned int lock_idx;
>> +	/* Assign an UAR lock according to UAR page number */
>> +	lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
>> +		   MLX5_UAR_PAGE_NUM_MASK;
>> +	txq->uar_lock = &priv->uar_lock[lock_idx];
>> +#endif
>> +}
> 
> This won't compile for arch is not 64bits, since 'page_size' in that block is
> not defined.

It is embarrassing that I have committed so many mistakes on this last patchset.
So many contexts in my head... Or, this patches must be haunted. :-(

I always test 32-bit but it looks like a mistake when rebasing it, not sure...
My apologies. I've sent out v5.

For your convenience, here's the diff.

$ git diff yskoh/upstr-remove-uar-remap
diff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h
index 904c4f5c03..6224b3be1a 100644
--- a/drivers/net/mlx4/mlx4.h
+++ b/drivers/net/mlx4/mlx4.h
@@ -56,16 +56,6 @@
 /** Enable extending memsegs when creating a MR. */
 #define MLX4_MR_EXT_MEMSEG_EN_KVARG "mr_ext_memseg_en"

-/* Reserved address space for UAR mapping. */
-#define MLX4_UAR_SIZE (1ULL << (sizeof(uintptr_t) * 4))
-
-/* Offset of reserved UAR address space to hugepage memory. Offset is used here
- * to minimize possibility of address next to hugepage being used by other code
- * in either primary or secondary process, failing to map TX UAR would make TX
- * packets invisible to HW.
- */
-#define MLX4_UAR_OFFSET (2ULL << (sizeof(uintptr_t) * 4))
-
 enum {
        PCI_VENDOR_ID_MELLANOX = 0x15b3,
 };
diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h
index bfe6655800..69b6960e94 100644
--- a/drivers/net/mlx5/mlx5_defs.h
+++ b/drivers/net/mlx5/mlx5_defs.h
@@ -91,16 +91,6 @@
 /* Timeout in seconds to get a valid link status. */
 #define MLX5_LINK_STATUS_TIMEOUT 10

-/* Reserved address space for UAR mapping. */
-#define MLX5_UAR_SIZE (1ULL << (sizeof(uintptr_t) * 4))
-
-/* Offset of reserved UAR address space to hugepage memory. Offset is used here
- * to minimize possibility of address next to hugepage being used by other code
- * in either primary or secondary process, failing to map TX UAR would make TX
- * packets invisible to HW.
- */
-#define MLX5_UAR_OFFSET (1ULL << (sizeof(uintptr_t) * 4))
-
 /* Maximum number of UAR pages used by a port,
  * These are the size and mask for an array of mutexes used to synchronize
  * the access to port's UARs on platforms that do not support 64 bit writes.
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 5fb1761955..9965b2b771 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -240,18 +240,19 @@ txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl)
 {
        struct mlx5_priv *priv = txq_ctrl->priv;
        struct mlx5_proc_priv *ppriv = MLX5_PROC_PRIV(PORT_ID(priv));
+#ifndef RTE_ARCH_64
+       unsigned int lock_idx;
+       const size_t page_size = sysconf(_SC_PAGESIZE);
+#endif

        assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
        assert(ppriv);
        ppriv->uar_table[txq_ctrl->txq.idx] = txq_ctrl->bf_reg;
 #ifndef RTE_ARCH_64
-       struct mlx5_priv *priv = txq_ctrl->priv;
-       struct mlx5_txq_data *txq = &txq_ctrl->txq;
-       unsigned int lock_idx;
        /* Assign an UAR lock according to UAR page number */
        lock_idx = (txq_ctrl->uar_mmap_offset / page_size) &
                   MLX5_UAR_PAGE_NUM_MASK;
-       txq->uar_lock = &priv->uar_lock[lock_idx];
+       txq_ctrl->txq.uar_lock = &priv->uar_lock[lock_idx];
 #endif
 }

  parent reply	other threads:[~2019-04-10 19:12 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-25 19:36 [dpdk-dev] [PATCH 0/3] net/mlx: " Yongseok Koh
2019-03-25 19:36 ` Yongseok Koh
2019-03-25 19:36 ` [dpdk-dev] [PATCH 1/3] net/mlx5: fix recursive inclusion of header file Yongseok Koh
2019-03-25 19:36   ` Yongseok Koh
2019-03-25 19:36 ` [dpdk-dev] [PATCH 2/3] net/mlx5: remove device register remap Yongseok Koh
2019-03-25 19:36   ` Yongseok Koh
2019-03-25 19:36 ` [dpdk-dev] [PATCH 3/3] net/mlx4: " Yongseok Koh
2019-03-25 19:36   ` Yongseok Koh
2019-04-01 21:22 ` [dpdk-dev] [PATCH v2 0/3] net/mlx: " Yongseok Koh
2019-04-01 21:22   ` Yongseok Koh
2019-04-01 21:22   ` [dpdk-dev] [PATCH v2 1/3] net/mlx5: fix recursive inclusion of header file Yongseok Koh
2019-04-01 21:22     ` Yongseok Koh
2019-04-02  5:39     ` Shahaf Shuler
2019-04-02  5:39       ` Shahaf Shuler
2019-04-01 21:22   ` [dpdk-dev] [PATCH v2 2/3] net/mlx5: remove device register remap Yongseok Koh
2019-04-01 21:22     ` Yongseok Koh
2019-04-02  6:50     ` Shahaf Shuler
2019-04-02  6:50       ` Shahaf Shuler
2019-04-01 21:22   ` [dpdk-dev] [PATCH v2 3/3] net/mlx4: " Yongseok Koh
2019-04-01 21:22     ` Yongseok Koh
2019-04-05  1:33 ` [dpdk-dev] [PATCH v3 0/4] net/mlx: " Yongseok Koh
2019-04-05  1:33   ` Yongseok Koh
2019-04-05  1:33   ` [dpdk-dev] [PATCH v3 1/4] net/mlx5: fix recursive inclusion of header file Yongseok Koh
2019-04-05  1:33     ` Yongseok Koh
2019-04-05  1:33   ` [dpdk-dev] [PATCH v3 2/4] net/mlx5: remove redundant queue index Yongseok Koh
2019-04-05  1:33     ` Yongseok Koh
2019-04-08  5:24     ` Shahaf Shuler
2019-04-08  5:24       ` Shahaf Shuler
2019-04-05  1:33   ` [dpdk-dev] [PATCH v3 3/4] net/mlx5: remove device register remap Yongseok Koh
2019-04-05  1:33     ` Yongseok Koh
2019-04-08  5:48     ` Shahaf Shuler
2019-04-08  5:48       ` Shahaf Shuler
2019-04-09 19:36       ` Yongseok Koh
2019-04-09 19:36         ` Yongseok Koh
2019-04-05  1:33   ` [dpdk-dev] [PATCH v3 4/4] net/mlx4: " Yongseok Koh
2019-04-05  1:33     ` Yongseok Koh
2019-04-09 23:13 ` [dpdk-dev] [PATCH v4 0/4] net/mlx: " Yongseok Koh
2019-04-09 23:13   ` Yongseok Koh
2019-04-09 23:13   ` [dpdk-dev] [PATCH v4 1/4] net/mlx5: fix recursive inclusion of header file Yongseok Koh
2019-04-09 23:13     ` Yongseok Koh
2019-04-09 23:13   ` [dpdk-dev] [PATCH v4 2/4] net/mlx5: remove redundant queue index Yongseok Koh
2019-04-09 23:13     ` Yongseok Koh
2019-04-09 23:13   ` [dpdk-dev] [PATCH v4 3/4] net/mlx5: remove device register remap Yongseok Koh
2019-04-09 23:13     ` Yongseok Koh
2019-04-10 17:50     ` Ferruh Yigit
2019-04-10 17:50       ` Ferruh Yigit
2019-04-10 19:12       ` Yongseok Koh [this message]
2019-04-10 19:12         ` Yongseok Koh
2019-04-09 23:13   ` [dpdk-dev] [PATCH v4 4/4] net/mlx4: " Yongseok Koh
2019-04-09 23:13     ` Yongseok Koh
2019-04-10  6:58   ` [dpdk-dev] [PATCH v4 0/4] net/mlx: " Shahaf Shuler
2019-04-10  6:58     ` Shahaf Shuler
2019-04-10 17:50     ` Ferruh Yigit
2019-04-10 17:50       ` Ferruh Yigit
2019-04-10 18:41 ` [dpdk-dev] [PATCH v5 " Yongseok Koh
2019-04-10 18:41   ` Yongseok Koh
2019-04-10 18:41   ` [dpdk-dev] [PATCH v5 1/4] net/mlx5: fix recursive inclusion of header file Yongseok Koh
2019-04-10 18:41     ` Yongseok Koh
2019-04-10 18:41   ` [dpdk-dev] [PATCH v5 2/4] net/mlx5: remove redundant queue index Yongseok Koh
2019-04-10 18:41     ` Yongseok Koh
2019-04-10 18:41   ` [dpdk-dev] [PATCH v5 3/4] net/mlx5: remove device register remap Yongseok Koh
2019-04-10 18:41     ` Yongseok Koh
2019-04-10 18:41   ` [dpdk-dev] [PATCH v5 4/4] net/mlx4: " Yongseok Koh
2019-04-10 18:41     ` Yongseok Koh
2019-04-11  8:40   ` [dpdk-dev] [PATCH v5 0/4] net/mlx: " Shahaf Shuler
2019-04-11  8:40     ` Shahaf Shuler

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=235F78D4-58FC-4A3A-AD43-0DC051EB89FF@mellanox.com \
    --to=yskoh@mellanox.com \
    --cc=dev@dpdk.org \
    --cc=ferruh.yigit@intel.com \
    --cc=shahafs@mellanox.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).