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From: Thomas Monjalon <thomas@monjalon.net>
To: Jerin Jacob <jerinjacobk@gmail.com>
Cc: dpdk-dev <dev@dpdk.org>, Bruce Richardson <bruce.richardson@intel.com>
Subject: Re: [dpdk-dev] [PATCH] config: increase default maximum number of NUMA nodes
Date: Thu, 04 Feb 2021 11:28:40 +0100	[thread overview]
Message-ID: <2455385.Mn0tqrlHz1@thomas> (raw)
In-Reply-To: <CALBAE1M1n591eRHBMsa0oXtGhameCcjJXqbcbUKpQ8GXPZTfpA@mail.gmail.com>

04/02/2021 07:19, Jerin Jacob:
> On Thu, Feb 4, 2021 at 2:49 AM Thomas Monjalon <thomas@monjalon.net> wrote:
> >
> > AMD CPU can present a high number of NUMA nodes.
> > The default should be 32 for better compatibility.
> 
> The typical configuration is 4 nodes[1] for AMD. Just wondering, Is it
> an exception case? if so, Do we need to consume more memory for normal
> cases?
> 
> [1]
> https://developer.amd.com/wp-content/resources/56308-NUMA%20Topology%20for%20AMD%20EPYC%E2%84%A2%20Naples%20Family%20Processors.PDF

As you can read in
https://www.dell.com/support/kbdoc/fr-fr/000137696/amd-rome-is-it-for-real-architecture-and-initial-hpc-performance
there is an option "CCX as NUMA Domain.
This option exposes each CCX as a NUMA node.
On a system with dual-socket CPUs with 16 CCXs per CPU,
this setting will expose 32 NUMA domains."
and
"Enabling this option is expected to help virtualized environments."

I would not say it is exceptional.
And in my understanding, the memory cost is not so high for DPDK.
Do you see some large arrays depending on RTE_MAX_NUMA_NODES?



  reply	other threads:[~2021-02-04 10:28 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-03 21:18 Thomas Monjalon
2021-02-04  6:19 ` Jerin Jacob
2021-02-04 10:28   ` Thomas Monjalon [this message]
2021-02-04 11:39     ` Jerin Jacob
2021-02-04  9:56 ` Bruce Richardson
2021-02-05 16:36   ` Thomas Monjalon
2021-02-04 10:56 ` Asaf Penso

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