From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 28330A0C3F; Wed, 28 Apr 2021 05:35:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 058B440697; Wed, 28 Apr 2021 05:35:19 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 3B8B140041 for ; Wed, 28 Apr 2021 05:35:17 +0200 (CEST) IronPort-SDR: WdSyHCn3VsTuo6FuH3C3sKkgkuRdsULBIqOT2YG8AvO3nJyEPTET0GZ3mevDgleSOeXPrY0mEi zQzPPtZ0CZBg== X-IronPort-AV: E=McAfee;i="6200,9189,9967"; a="194533010" X-IronPort-AV: E=Sophos;i="5.82,257,1613462400"; d="scan'208";a="194533010" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2021 20:35:16 -0700 IronPort-SDR: NZf3Z85sxwVvUbI/ctrhkMw1pUGlzZp9PxamSQUVuZtJ5G4DUZW2vv9fUE4UNB3p4+IfUaQEAu k1+Vwb/4234g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,257,1613462400"; d="scan'208";a="386365138" Received: from fmsmsx605.amr.corp.intel.com ([10.18.126.85]) by orsmga003.jf.intel.com with ESMTP; 27 Apr 2021 20:35:15 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Tue, 27 Apr 2021 20:35:14 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by SHSMSX601.ccr.corp.intel.com (10.109.6.141) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2106.2; Wed, 28 Apr 2021 11:35:13 +0800 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2106.013; Wed, 28 Apr 2021 11:35:13 +0800 From: "Zhang, Qi Z" To: "Wang, Haiyue" , "dev@dpdk.org" CC: "Wang, Liang-min" , "david.marchand@redhat.com" , "Xing, Beilei" , "Guo, Jia" Thread-Topic: [PATCH v4 3/3] net/i40e: enable PCI bus master after reset Thread-Index: AQHXO25e2+sTU1xVd0+ToAEXDxUPc6rJSBVw Date: Wed, 28 Apr 2021 03:35:12 +0000 Message-ID: <250553b6da7643a3940efa536248c2bf@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210427133912.261993-1-haiyue.wang@intel.com> <20210427133912.261993-4-haiyue.wang@intel.com> In-Reply-To: <20210427133912.261993-4-haiyue.wang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v4 3/3] net/i40e: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Wang, Haiyue > Sent: Tuesday, April 27, 2021 9:39 PM > To: dev@dpdk.org > Cc: Zhang, Qi Z ; Wang, Liang-min > ; david.marchand@redhat.com; Wang, Haiyue > ; Xing, Beilei ; Guo, Jia > > Subject: [PATCH v4 3/3] net/i40e: enable PCI bus master after reset >=20 > The VF reset can be triggerred by the PF reset event, in this case, the P= CI bus > master will be cleared, then the VF is not allowed to issue any Memory or= I/O > Requests. >=20 > So after the reset event is detected, always enable the PCI bus master. >=20 > And align the VF reset event handling in device close module as the AVF d= river > does. >=20 > Signed-off-by: Haiyue Wang > --- > drivers/net/i40e/i40e_ethdev_vf.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/net/i40e/i40e_ethdev_vf.c > b/drivers/net/i40e/i40e_ethdev_vf.c > index 3c258ba7c..8b041e94c 100644 > --- a/drivers/net/i40e/i40e_ethdev_vf.c > +++ b/drivers/net/i40e/i40e_ethdev_vf.c > @@ -1212,7 +1212,6 @@ i40evf_check_vf_reset_done(struct rte_eth_dev > *dev) > if (i >=3D MAX_RESET_WAIT_CNT) > return -1; >=20 > - vf->vf_reset =3D false; > vf->pend_msg &=3D ~PFMSG_RESET_IMPENDING; >=20 > return 0; > @@ -1391,6 +1390,7 @@ i40evf_handle_pf_event(struct rte_eth_dev *dev, > uint8_t *msg, > switch (pf_msg->event) { > case VIRTCHNL_EVENT_RESET_IMPENDING: > PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING > event"); > + vf->vf_reset =3D true; > rte_eth_dev_callback_process(dev, > RTE_ETH_EVENT_INTR_RESET, NULL); > break; > @@ -2487,6 +2487,11 @@ i40evf_dev_close(struct rte_eth_dev *dev) > i40e_shutdown_adminq(hw); > i40evf_disable_irq0(hw); >=20 > + if (vf->vf_reset) > + rte_pci_set_bus_master(RTE_ETH_DEV_TO_PCI(dev), true); > + > + vf->vf_reset =3D false; > + > rte_free(vf->vf_res); > vf->vf_res =3D NULL; > rte_free(vf->aq_resp); > -- > 2.31.1 Acked-by: Qi Zhang