From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 1745C5682 for ; Tue, 27 Oct 2015 19:50:18 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP; 27 Oct 2015 11:50:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,206,1444719600"; d="scan'208";a="804640414" Received: from orsmsx110.amr.corp.intel.com ([10.22.240.8]) by orsmga001.jf.intel.com with ESMTP; 27 Oct 2015 11:50:18 -0700 Received: from orsmsx114.amr.corp.intel.com ([169.254.8.29]) by ORSMSX110.amr.corp.intel.com ([169.254.3.191]) with mapi id 14.03.0248.002; Tue, 27 Oct 2015 11:50:16 -0700 From: "Brandeburg, Jesse" To: Vlad Zolotarov , Thomas Monjalon , "Ananyev, Konstantin" , "Zhang, Helin" , "Rustad, Mark D" , "Skidmore, Donald C" , "Tantilov, Emil S" Thread-Topic: [dpdk-dev] [PATCH v4] ixgbe_pmd: enforce RS bit on every EOP descriptor for devices newer than 82598 Thread-Index: AQHREOLSEIydJz4k5kuEWML5SCeRzZ6AI4YA//+LOvA= Date: Tue, 27 Oct 2015 18:50:15 +0000 Message-ID: <253CF818969A9240AB2054BF91F2C2BC3024C1FD@ORSMSX114.amr.corp.intel.com> References: <1440085070-13989-1-git-send-email-vladz@cloudius-systems.com> <55DAD1C9.3010802@cloudius-systems.com> <1764015.lv7zT9MUyf@xps13> <562FC6D4.8000202@cloudius-systems.com> In-Reply-To: <562FC6D4.8000202@cloudius-systems.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsIiwiaWQiOiJjNzdlYjg2NS05YzNlLTRmMWYtODMyNS01N2M4Y2Y4NTNhMmMiLCJwcm9wcyI6W3sibiI6IkludGVsRGF0YUNsYXNzaWZpY2F0aW9uIiwidmFscyI6W3sidmFsdWUiOiJDVFBfSUMifV19XX0sIlN1YmplY3RMYWJlbHMiOltdLCJUTUNWZXJzaW9uIjoiMTUuNC4xMC4xOSIsIlRydXN0ZWRMYWJlbEhhc2giOiI4MVhyVndFa1pCblpyMzMzVFh5UmN0cXVpcUsrSTdManlPdm1ENjlnWVQwPSJ9 x-inteldataclassification: CTP_IC x-originating-ip: [10.22.254.138] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 29 Oct 2015 08:37:49 +0100 Cc: "dev@dpdk.org" , "Kirsher, Jeffrey T" Subject: Re: [dpdk-dev] [PATCH v4] ixgbe_pmd: enforce RS bit on every EOP descriptor for devices newer than 82598 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Oct 2015 18:50:19 -0000 +ixgbe developers. -----Original Message----- From: Vlad Zolotarov [mailto:vladz@cloudius-systems.com]=20 Sent: Tuesday, October 27, 2015 11:48 AM To: Thomas Monjalon; Ananyev, Konstantin; Zhang, Helin Cc: dev@dpdk.org; Kirsher, Jeffrey T; Brandeburg, Jesse Subject: Re: [dpdk-dev] [PATCH v4] ixgbe_pmd: enforce RS bit on every EOP d= escriptor for devices newer than 82598 On 10/27/15 20:09, Thomas Monjalon wrote: > Any Follow-up to this discussion? > Should we mark this patch as rejected? Hmmm... This patch fixes an obvious spec violation. Why would it be=20 rejected? > > 2015-08-24 11:11, Vlad Zolotarov: >> On 08/20/15 18:37, Vlad Zolotarov wrote: >>> According to 82599 and x540 HW specifications RS bit *must* be >>> set in the last descriptor of *every* packet. >>> >>> Before this patch there were 3 types of Tx callbacks that were setting >>> RS bit every tx_rs_thresh descriptors. This patch introduces a set of >>> new callbacks, one for each type mentioned above, that will set the RS >>> bit in every EOP descriptor. >>> >>> ixgbe_set_tx_function() will set the appropriate Tx callback according >>> to the device family. >> [+Jesse and Jeff] >> >> I've started to look at the i40e PMD and it has the same RS bit >> deferring logic >> as ixgbe PMD has (surprise, surprise!.. ;)). To recall, i40e PMD uses a >> descriptor write-back >> completion mode. >> >> From the HW Spec it's unclear if RS bit should be set on *every* descr= iptor >> with EOP bit. However I noticed that Linux driver, before it moved to >> HEAD write-back mode, was setting RS >> bit on every EOP descriptor. >> >> So, here is a question to Intel guys: could u, pls., clarify this point? >> >> Thanks in advance, >> vlad > >