From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id EDD7447CE for ; Fri, 21 Apr 2017 14:19:29 +0200 (CEST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP; 21 Apr 2017 05:19:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,229,1488873600"; d="scan'208";a="92597511" Received: from fyigit-mobl1.ger.corp.intel.com (HELO [10.237.220.59]) ([10.237.220.59]) by fmsmga006.fm.intel.com with ESMTP; 21 Apr 2017 05:19:27 -0700 To: "Lu, Wenzhuo" , "Dai, Wei" , "Zhang, Helin" , "Ananyev, Konstantin" Cc: "dev@dpdk.org" References: <1492657566-26395-1-git-send-email-wei.dai@intel.com> <6A0DE07E22DDAD4C9103DF62FEBC09093B59B4A6@shsmsx102.ccr.corp.intel.com> From: Ferruh Yigit Message-ID: <2574363d-96b0-358d-d32b-83ec9a6532a2@intel.com> Date: Fri, 21 Apr 2017 13:19:27 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.0.1 MIME-Version: 1.0 In-Reply-To: <6A0DE07E22DDAD4C9103DF62FEBC09093B59B4A6@shsmsx102.ccr.corp.intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Subject: Re: [dpdk-dev] [PATCH] net/ixgbe: align register setting when RSC is disabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Apr 2017 12:19:30 -0000 On 4/21/2017 3:21 AM, Lu, Wenzhuo wrote: > Hi, > > >> -----Original Message----- >> From: Dai, Wei >> Sent: Thursday, April 20, 2017 11:06 AM >> To: Zhang, Helin; Ananyev, Konstantin; Lu, Wenzhuo; Dai, Wei >> Cc: dev@dpdk.org >> Subject: [PATCH] net/ixgbe: align register setting when RSC is disabled >> >> When RSC is not used, the RSC_DIS of register RFCTL should be set according >> to ixgbe datasheet. >> >> Signed-off-by: Wei Dai > Acked-by: Wenzhuo Lu Applied to dpdk-next-net/master, thanks.