From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 241F01B605 for ; Thu, 21 Mar 2019 19:47:11 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Mar 2019 11:47:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,253,1549958400"; d="scan'208";a="330760446" Received: from irsmsx110.ger.corp.intel.com ([163.33.3.25]) by fmsmga005.fm.intel.com with ESMTP; 21 Mar 2019 11:47:09 -0700 Received: from irsmsx156.ger.corp.intel.com (10.108.20.68) by irsmsx110.ger.corp.intel.com (163.33.3.25) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 21 Mar 2019 18:47:08 +0000 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.210]) by IRSMSX156.ger.corp.intel.com ([169.254.3.101]) with mapi id 14.03.0415.000; Thu, 21 Mar 2019 18:43:22 +0000 From: "Ananyev, Konstantin" To: Joyce Kong , "dev@dpdk.org" CC: "nd@arm.com" , "jerinj@marvell.com" , "chaozhu@linux.vnet.ibm.com" , "Richardson, Bruce" , "thomas@monjalon.net" , "hemant.agrawal@nxp.com" , "honnappa.nagarahalli@arm.com" , "gavin.hu@arm.com" Thread-Topic: [PATCH v4 1/3] rwlock: reimplement with atomic builtins Thread-Index: AQHU3uXEnKM+YN5pSkOJgc6LoMXa5aYWbYaQ Date: Thu, 21 Mar 2019 18:43:21 +0000 Message-ID: <2601191342CEEE43887BDE71AB977258013655E71E@irsmsx105.ger.corp.intel.com> References: <1544672265-219262-2-git-send-email-joyce.kong@arm.com> <1553063109-57574-2-git-send-email-joyce.kong@arm.com> In-Reply-To: <1553063109-57574-2-git-send-email-joyce.kong@arm.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNGFjYTFjZDQtZGYxNC00YjdmLTkwYjAtY2I1MTYzMzA2YzcyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiSFF1T05iTEVDWXFmQkxXWWlQcFNtZVhFbGlxcnhQWFdtYXlDVmVlUytRdFRCRGZDclhRRmdHSkNUcU16Tkk1ZyJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v4 1/3] rwlock: reimplement with atomic builtins X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Mar 2019 18:47:12 -0000 > -----Original Message----- > From: Joyce Kong [mailto:joyce.kong@arm.com] > Sent: Wednesday, March 20, 2019 6:25 AM > To: dev@dpdk.org > Cc: nd@arm.com; jerinj@marvell.com; Ananyev, Konstantin ; chaozhu@linux.vnet.ibm.com; Richardson, > Bruce ; thomas@monjalon.net; hemant.agrawal@n= xp.com; honnappa.nagarahalli@arm.com; > gavin.hu@arm.com > Subject: [PATCH v4 1/3] rwlock: reimplement with atomic builtins >=20 > The __sync builtin based implementation generates full memory > barriers ('dmb ish') on Arm platforms. Using C11 atomic builtins > to generate one way barriers. >=20 > Here is the assembly code of __sync_compare_and_swap builtin. > __sync_bool_compare_and_swap(dst, exp, src); > 0x000000000090f1b0 <+16>: e0 07 40 f9 ldr x0, [sp, #8] > 0x000000000090f1b4 <+20>: e1 0f 40 79 ldrh w1, [sp, #6] > 0x000000000090f1b8 <+24>: e2 0b 40 79 ldrh w2, [sp, #4] > 0x000000000090f1bc <+28>: 21 3c 00 12 and w1, w1, #0xffff > 0x000000000090f1c0 <+32>: 03 7c 5f 48 ldxrh w3, [x0] > 0x000000000090f1c4 <+36>: 7f 00 01 6b cmp w3, w1 > 0x000000000090f1c8 <+40>: 61 00 00 54 b.ne 0x90f1d4 > // b.any > 0x000000000090f1cc <+44>: 02 fc 04 48 stlxrh w4, w2, [x0] > 0x000000000090f1d0 <+48>: 84 ff ff 35 cbnz w4, 0x90f1c0 > > 0x000000000090f1d4 <+52>: bf 3b 03 d5 dmb ish > 0x000000000090f1d8 <+56>: e0 17 9f 1a cset w0, eq // eq =3D non= e >=20 > Signed-off-by: Gavin Hu > Signed-off-by: Joyce Kong > Tested-by: Joyce Kong > Acked-by: Jerin Jacob > --- > lib/librte_eal/common/include/generic/rte_rwlock.h | 29 +++++++++++-----= ------ > 1 file changed, 15 insertions(+), 14 deletions(-) >=20 > diff --git a/lib/librte_eal/common/include/generic/rte_rwlock.h b/lib/lib= rte_eal/common/include/generic/rte_rwlock.h > index b05d85a..de94ca9 100644 > --- a/lib/librte_eal/common/include/generic/rte_rwlock.h > +++ b/lib/librte_eal/common/include/generic/rte_rwlock.h > @@ -64,14 +64,14 @@ rte_rwlock_read_lock(rte_rwlock_t *rwl) > int success =3D 0; >=20 > while (success =3D=3D 0) { > - x =3D rwl->cnt; > + x =3D __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED); > /* write lock is held */ > if (x < 0) { > rte_pause(); > continue; > } > - success =3D rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt, > - (uint32_t)x, (uint32_t)(x + 1)); > + success =3D __atomic_compare_exchange_n(&rwl->cnt, &x, x+1, 1, As a nit, here and in trylock: 'x+1' spaces missing, needs to be 'x + 1'. Apart from that: Acked-by: Konstantin Ananyev From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 44F3AA00E6 for ; Thu, 21 Mar 2019 19:47:14 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0E0071B607; Thu, 21 Mar 2019 19:47:13 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 241F01B605 for ; Thu, 21 Mar 2019 19:47:11 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Mar 2019 11:47:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,253,1549958400"; d="scan'208";a="330760446" Received: from irsmsx110.ger.corp.intel.com ([163.33.3.25]) by fmsmga005.fm.intel.com with ESMTP; 21 Mar 2019 11:47:09 -0700 Received: from irsmsx156.ger.corp.intel.com (10.108.20.68) by irsmsx110.ger.corp.intel.com (163.33.3.25) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 21 Mar 2019 18:47:08 +0000 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.210]) by IRSMSX156.ger.corp.intel.com ([169.254.3.101]) with mapi id 14.03.0415.000; Thu, 21 Mar 2019 18:43:22 +0000 From: "Ananyev, Konstantin" To: Joyce Kong , "dev@dpdk.org" CC: "nd@arm.com" , "jerinj@marvell.com" , "chaozhu@linux.vnet.ibm.com" , "Richardson, Bruce" , "thomas@monjalon.net" , "hemant.agrawal@nxp.com" , "honnappa.nagarahalli@arm.com" , "gavin.hu@arm.com" Thread-Topic: [PATCH v4 1/3] rwlock: reimplement with atomic builtins Thread-Index: AQHU3uXEnKM+YN5pSkOJgc6LoMXa5aYWbYaQ Date: Thu, 21 Mar 2019 18:43:21 +0000 Message-ID: <2601191342CEEE43887BDE71AB977258013655E71E@irsmsx105.ger.corp.intel.com> References: <1544672265-219262-2-git-send-email-joyce.kong@arm.com> <1553063109-57574-2-git-send-email-joyce.kong@arm.com> In-Reply-To: <1553063109-57574-2-git-send-email-joyce.kong@arm.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNGFjYTFjZDQtZGYxNC00YjdmLTkwYjAtY2I1MTYzMzA2YzcyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiSFF1T05iTEVDWXFmQkxXWWlQcFNtZVhFbGlxcnhQWFdtYXlDVmVlUytRdFRCRGZDclhRRmdHSkNUcU16Tkk1ZyJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v4 1/3] rwlock: reimplement with atomic builtins X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190321184321.3BI2xxX-EbVATCNlWu-G6bCniMglvTgeLDmuaOoP1BY@z> > -----Original Message----- > From: Joyce Kong [mailto:joyce.kong@arm.com] > Sent: Wednesday, March 20, 2019 6:25 AM > To: dev@dpdk.org > Cc: nd@arm.com; jerinj@marvell.com; Ananyev, Konstantin ; chaozhu@linux.vnet.ibm.com; Richardson, > Bruce ; thomas@monjalon.net; hemant.agrawal@n= xp.com; honnappa.nagarahalli@arm.com; > gavin.hu@arm.com > Subject: [PATCH v4 1/3] rwlock: reimplement with atomic builtins >=20 > The __sync builtin based implementation generates full memory > barriers ('dmb ish') on Arm platforms. Using C11 atomic builtins > to generate one way barriers. >=20 > Here is the assembly code of __sync_compare_and_swap builtin. > __sync_bool_compare_and_swap(dst, exp, src); > 0x000000000090f1b0 <+16>: e0 07 40 f9 ldr x0, [sp, #8] > 0x000000000090f1b4 <+20>: e1 0f 40 79 ldrh w1, [sp, #6] > 0x000000000090f1b8 <+24>: e2 0b 40 79 ldrh w2, [sp, #4] > 0x000000000090f1bc <+28>: 21 3c 00 12 and w1, w1, #0xffff > 0x000000000090f1c0 <+32>: 03 7c 5f 48 ldxrh w3, [x0] > 0x000000000090f1c4 <+36>: 7f 00 01 6b cmp w3, w1 > 0x000000000090f1c8 <+40>: 61 00 00 54 b.ne 0x90f1d4 > // b.any > 0x000000000090f1cc <+44>: 02 fc 04 48 stlxrh w4, w2, [x0] > 0x000000000090f1d0 <+48>: 84 ff ff 35 cbnz w4, 0x90f1c0 > > 0x000000000090f1d4 <+52>: bf 3b 03 d5 dmb ish > 0x000000000090f1d8 <+56>: e0 17 9f 1a cset w0, eq // eq =3D non= e >=20 > Signed-off-by: Gavin Hu > Signed-off-by: Joyce Kong > Tested-by: Joyce Kong > Acked-by: Jerin Jacob > --- > lib/librte_eal/common/include/generic/rte_rwlock.h | 29 +++++++++++-----= ------ > 1 file changed, 15 insertions(+), 14 deletions(-) >=20 > diff --git a/lib/librte_eal/common/include/generic/rte_rwlock.h b/lib/lib= rte_eal/common/include/generic/rte_rwlock.h > index b05d85a..de94ca9 100644 > --- a/lib/librte_eal/common/include/generic/rte_rwlock.h > +++ b/lib/librte_eal/common/include/generic/rte_rwlock.h > @@ -64,14 +64,14 @@ rte_rwlock_read_lock(rte_rwlock_t *rwl) > int success =3D 0; >=20 > while (success =3D=3D 0) { > - x =3D rwl->cnt; > + x =3D __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED); > /* write lock is held */ > if (x < 0) { > rte_pause(); > continue; > } > - success =3D rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt, > - (uint32_t)x, (uint32_t)(x + 1)); > + success =3D __atomic_compare_exchange_n(&rwl->cnt, &x, x+1, 1, As a nit, here and in trylock: 'x+1' spaces missing, needs to be 'x + 1'. Apart from that: Acked-by: Konstantin Ananyev