From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id DB8D6A49 for ; Tue, 7 May 2019 12:40:34 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 May 2019 03:40:34 -0700 X-ExtLoop1: 1 Received: from irsmsx110.ger.corp.intel.com ([163.33.3.25]) by orsmga001.jf.intel.com with ESMTP; 07 May 2019 03:40:32 -0700 Received: from irsmsx112.ger.corp.intel.com (10.108.20.5) by irsmsx110.ger.corp.intel.com (163.33.3.25) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 7 May 2019 11:40:30 +0100 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.31]) by irsmsx112.ger.corp.intel.com ([169.254.1.101]) with mapi id 14.03.0415.000; Tue, 7 May 2019 11:40:30 +0100 From: "Ananyev, Konstantin" To: David Christensen , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on power CPUs Thread-Index: AQHVBEFeC6dDtPCjiUCfrzdhTbENSqZfeexQ Date: Tue, 7 May 2019 10:40:29 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772580148AA219D@irsmsx105.ger.corp.intel.com> References: <1557170647-99966-1-git-send-email-drc@linux.vnet.ibm.com> In-Reply-To: <1557170647-99966-1-git-send-email-drc@linux.vnet.ibm.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZWI3MzI1YjItNTYwOC00YTQ3LWFiNGUtODg1MDk0ZWE0YzA5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZUtXMUxkZDhDWnBoS0RjUGZHdjZlQXZQR3Z1TVR4bFwvcjJqZVk3Y0o3QzNKV2JHbnRoMHRSUStXaml2MDFDUm4ifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on power CPUs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 May 2019 10:40:35 -0000 >=20 > The memory barrier test fails on IBM Power 9 systems. Add additional > barriers to accommodate the weakly ordered model used on Power CPUs. >=20 > Signed-off-by: David Christensen > --- > v2: > * Removed ifdef's for PPC since the rte_smp_*mb() macros are already > customized for each CPU architecture >=20 > app/test/test_barrier.c | 2 ++ > 1 file changed, 2 insertions(+) >=20 > diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c > index a022708..0bf82cf 100644 > --- a/app/test/test_barrier.c > +++ b/app/test/test_barrier.c > @@ -92,12 +92,14 @@ struct lcore_plock_test { > other =3D self ^ 1; >=20 > l->flag[self] =3D 1; > + rte_smp_wmb(); > l->victim =3D self; >=20 > store_load_barrier(l->utype); >=20 > while (l->flag[other] =3D=3D 1 && l->victim =3D=3D self) > rte_pause(); > + rte_smp_rmb(); > } >=20 > static void > -- Acked-by: Konstantin Ananyev > 1.8.3.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 96107A0096 for ; Tue, 7 May 2019 12:40:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5421F343C; Tue, 7 May 2019 12:40:36 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id DB8D6A49 for ; Tue, 7 May 2019 12:40:34 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 May 2019 03:40:34 -0700 X-ExtLoop1: 1 Received: from irsmsx110.ger.corp.intel.com ([163.33.3.25]) by orsmga001.jf.intel.com with ESMTP; 07 May 2019 03:40:32 -0700 Received: from irsmsx112.ger.corp.intel.com (10.108.20.5) by irsmsx110.ger.corp.intel.com (163.33.3.25) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 7 May 2019 11:40:30 +0100 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.31]) by irsmsx112.ger.corp.intel.com ([169.254.1.101]) with mapi id 14.03.0415.000; Tue, 7 May 2019 11:40:30 +0100 From: "Ananyev, Konstantin" To: David Christensen , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on power CPUs Thread-Index: AQHVBEFeC6dDtPCjiUCfrzdhTbENSqZfeexQ Date: Tue, 7 May 2019 10:40:29 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772580148AA219D@irsmsx105.ger.corp.intel.com> References: <1557170647-99966-1-git-send-email-drc@linux.vnet.ibm.com> In-Reply-To: <1557170647-99966-1-git-send-email-drc@linux.vnet.ibm.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZWI3MzI1YjItNTYwOC00YTQ3LWFiNGUtODg1MDk0ZWE0YzA5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZUtXMUxkZDhDWnBoS0RjUGZHdjZlQXZQR3Z1TVR4bFwvcjJqZVk3Y0o3QzNKV2JHbnRoMHRSUStXaml2MDFDUm4ifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 4/4] test: fix memory barrier test failure on power CPUs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190507104029.L5HsHZo6I0Zbuux1KM936olOJxrLoIMFL5Nn75WSoTM@z> >=20 > The memory barrier test fails on IBM Power 9 systems. Add additional > barriers to accommodate the weakly ordered model used on Power CPUs. >=20 > Signed-off-by: David Christensen > --- > v2: > * Removed ifdef's for PPC since the rte_smp_*mb() macros are already > customized for each CPU architecture >=20 > app/test/test_barrier.c | 2 ++ > 1 file changed, 2 insertions(+) >=20 > diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c > index a022708..0bf82cf 100644 > --- a/app/test/test_barrier.c > +++ b/app/test/test_barrier.c > @@ -92,12 +92,14 @@ struct lcore_plock_test { > other =3D self ^ 1; >=20 > l->flag[self] =3D 1; > + rte_smp_wmb(); > l->victim =3D self; >=20 > store_load_barrier(l->utype); >=20 > while (l->flag[other] =3D=3D 1 && l->victim =3D=3D self) > rte_pause(); > + rte_smp_rmb(); > } >=20 > static void > -- Acked-by: Konstantin Ananyev > 1.8.3.1