From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 72612593E for ; Thu, 16 Oct 2014 02:32:04 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 15 Oct 2014 17:39:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,862,1389772800"; d="scan'208";a="400979668" Received: from irsmsx101.ger.corp.intel.com ([163.33.3.153]) by FMSMGA003.fm.intel.com with ESMTP; 15 Oct 2014 17:32:38 -0700 Received: from irsmsx152.ger.corp.intel.com (163.33.192.66) by IRSMSX101.ger.corp.intel.com (163.33.3.153) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 16 Oct 2014 01:39:52 +0100 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.174]) by IRSMSX152.ger.corp.intel.com ([169.254.6.118]) with mapi id 14.03.0195.001; Thu, 16 Oct 2014 01:39:52 +0100 From: "Ananyev, Konstantin" To: Chao Zhu , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture Thread-Index: AQHP2W25SswllW2KyUmFT2/7y09pypwx6h8A Date: Thu, 16 Oct 2014 00:39:52 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725821393C8F@IRSMSX105.ger.corp.intel.com> References: <1411724186-8036-1-git-send-email-bjzhuc@cn.ibm.com> <1411724186-8036-3-git-send-email-bjzhuc@cn.ibm.com> In-Reply-To: <1411724186-8036-3-git-send-email-bjzhuc@cn.ibm.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Oct 2014 00:32:06 -0000 Hi, > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Chao Zhu > Sent: Friday, September 26, 2014 10:36 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power arc= hitecture >=20 > The atomic operations implemented with assembly code in DPDK only > support x86. This patch add architecture specific atomic operations for > IBM Power architecture. >=20 > Signed-off-by: Chao Zhu > --- > .../common/include/powerpc/arch/rte_atomic.h | 387 ++++++++++++++= ++++++ > .../common/include/powerpc/arch/rte_atomic_arch.h | 318 ++++++++++++++= ++ > 2 files changed, 705 insertions(+), 0 deletions(-) > create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_atomic= .h > create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_atomic= _arch.h >=20 ... > + > diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h > b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h > new file mode 100644 > index 0000000..fe5666e > --- /dev/null > + ... >+#define rte_arch_rmb() asm volatile("sync" : : : "memory") >+ > +#define rte_arch_compiler_barrier() do { \ > + asm volatile ("" : : : "memory"); \ > +} while(0) I don't know much about PPC architecture, but as I remember it uses a weak= ly-ordering memory model. Is that correct? If so, then you probably need rte_arch_compiler_barrier() to be "sync" inst= ruction (like mb()s above) . The reason is that IA has much stronger memory ordering model and there are= a lot of places in the code where it implies that ordering. For example - ring enqueue/dequeue functions.=09 Konstantin