From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 5A0DA7E87 for ; Thu, 16 Oct 2014 12:52:52 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 16 Oct 2014 04:00:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,862,1389772800"; d="scan'208";a="401186813" Received: from irsmsx104.ger.corp.intel.com ([163.33.3.159]) by FMSMGA003.fm.intel.com with ESMTP; 16 Oct 2014 03:53:25 -0700 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.174]) by IRSMSX104.ger.corp.intel.com ([169.254.5.248]) with mapi id 14.03.0195.001; Thu, 16 Oct 2014 11:59:29 +0100 From: "Ananyev, Konstantin" To: "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture Thread-Index: AQHP2W25SswllW2KyUmFT2/7y09pypwx6h8AgAAwugCAAI9TIIAAADww Date: Thu, 16 Oct 2014 10:59:27 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725821393F72@IRSMSX105.ger.corp.intel.com> References: <1411724186-8036-1-git-send-email-bjzhuc@cn.ibm.com> <1411724186-8036-3-git-send-email-bjzhuc@cn.ibm.com> <2601191342CEEE43887BDE71AB97725821393C8F@IRSMSX105.ger.corp.intel.com> <2601191342CEEE43887BDE71AB97725821393F5D@IRSMSX105.ger.corp.intel.com> In-Reply-To: <2601191342CEEE43887BDE71AB97725821393F5D@IRSMSX105.ger.corp.intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Oct 2014 10:52:53 -0000 >=20 >=20 > From: Chao CH Zhu [mailto:bjzhuc@cn.ibm.com] > Sent: Thursday, October 16, 2014 4:14 AM > To: Ananyev, Konstantin > Cc: dev@dpdk.org > Subject: RE: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power= architecture >=20 > Konstantin, >=20 > In my understanding, compiler barrier is a kind of software barrier which= prevents the compiler from moving memory accesses across > the barrier. Yes, compiler_barrier() right now only guarantees that the compiler wouldn'= t reorder instructions across it while emitting the code. > This should be architecture-independent. And the "sync" instruction is a = hardware barrier which depends on PowerPC > architecture. I understand what "sync" does. >So I think the compiler barrier should be the same on x86 and PowerPC. Any= comments? Please correct me if I was > wrong. The thing is that current DPDK code will not work correctly on system with = weak memory ordering - IA has quite strict memory ordering model and there is a code inside DPDK t= hat relies on the fact that CPU would follow that model. For such places in the code - compiler barrier is enough for IA, but is not= enough for PPC.=20 Do you worry about the names here- compiler barrier will become a HW one? := )? In that case what you probably can do: Create a new architecture dependent macro: rte_barrier(). That would expand into rte_compiler_barrier() for IA and to rte_mb() for P= PC. Got through all references of rte_compiler_barrier() inside DPDK and replac= e it with rte_barrier(). Konstantin >=20 > Thanks a lot! >=20 > Best Regards! > ------------------------------ > Chao Zhu >=20 >=20 >=20 >=20 > From: =A0 =A0 =A0 =A0"Ananyev, Konstantin" > To: =A0 =A0 =A0 =A0Chao CH Zhu/China/IBM@IBMCN, "dev@dpdk.org" > Date: =A0 =A0 =A0 =A02014/10/16 08:38 > Subject: =A0 =A0 =A0 =A0RE: [dpdk-dev] [PATCH 02/12] Add atomic operation= s for IBM Power =A0 =A0 =A0 =A0architecture > ________________________________________ >=20 >=20 >=20 >=20 > Hi, >=20 > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Chao Zhu > > Sent: Friday, September 26, 2014 10:36 AM > > To: dev@dpdk.org > > Subject: [dpdk-dev] [PATCH 02/12] Add atomic operations for IBM Power a= rchitecture > > > > The atomic operations implemented with assembly code in DPDK only > > support x86. This patch add architecture specific atomic operations for > > IBM Power architecture. > > > > Signed-off-by: Chao Zhu > > --- > > =A0.../common/include/powerpc/arch/rte_atomic.h =A0 =A0 =A0 | =A0387 ++= ++++++++++++++++++ > > =A0.../common/include/powerpc/arch/rte_atomic_arch.h =A0| =A0318 ++++++= ++++++++++ > > =A02 files changed, 705 insertions(+), 0 deletions(-) > > =A0create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_at= omic.h > > =A0create mode 100644 lib/librte_eal/common/include/powerpc/arch/rte_at= omic_arch.h > > > ... > > + > > diff --git a/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch= .h > > b/lib/librte_eal/common/include/powerpc/arch/rte_atomic_arch.h > > new file mode 100644 > > index 0000000..fe5666e > > --- /dev/null > > + > ... > >+#define =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rte_arch_rmb() asm volatile("sy= nc" : : : "memory") > >+ > > +#define =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rte_arch_compiler_barrier() do= { =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0\ > > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 asm volatile ("" : : : "memory"); =A0= =A0 =A0 =A0 =A0 =A0 =A0 =A0 \ > > +} while(0) >=20 > I don't know much about PPC architecture, but as I remember it uses a =A0= weakly-ordering memory model. > Is that correct? > If so, then you probably need rte_arch_compiler_barrier() to be "sync" in= struction (like mb()s above) . > The reason is that IA has much stronger memory ordering model and there a= re a lot of places in the code where it implies > that =A0ordering. > For example - ring enqueue/dequeue functions. >=20 > Konstantin