From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 112947FB0 for ; Mon, 17 Nov 2014 13:23:50 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 17 Nov 2014 04:34:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,402,1413270000"; d="scan'208";a="609063600" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by orsmga001.jf.intel.com with ESMTP; 17 Nov 2014 04:34:05 -0800 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.101]) by IRSMSX102.ger.corp.intel.com ([169.254.2.93]) with mapi id 14.03.0195.001; Mon, 17 Nov 2014 12:34:04 +0000 From: "Ananyev, Konstantin" To: Yerden Zhumabekov , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2 3/4] hash: add fallback to software CRC32 implementation Thread-Index: AQHQAccfoFR5xZz6XkStvDedHRayi5xkvu0Q Date: Mon, 17 Nov 2014 12:34:04 +0000 Message-ID: <2601191342CEEE43887BDE71AB977258213AE40F@IRSMSX105.ger.corp.intel.com> References: <1409724351-23786-1-git-send-email-e_zhumabekov@sts.kz> <1416160760-16087-4-git-send-email-e_zhumabekov@sts.kz> In-Reply-To: <1416160760-16087-4-git-send-email-e_zhumabekov@sts.kz> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 3/4] hash: add fallback to software CRC32 implementation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 17 Nov 2014 12:23:51 -0000 Hi Yerden, > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Yerden Zhumabekov > Sent: Sunday, November 16, 2014 5:59 PM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH v2 3/4] hash: add fallback to software CRC32 i= mplementation >=20 > Initially, SSE4.2 support is detected via CPUID instruction. >=20 > Added rte_hash_crc_set_alg() function to detect and set CRC32 > implementation if necessary. SSE4.2 is allowed by default. If it's > not available, fall back to sw implementation. >=20 > Signed-off-by: Yerden Zhumabekov > --- > lib/librte_hash/rte_hash_crc.h | 60 ++++++++++++++++++++++++++++++++++= ++++-- > 1 file changed, 58 insertions(+), 2 deletions(-) >=20 > diff --git a/lib/librte_hash/rte_hash_crc.h b/lib/librte_hash/rte_hash_cr= c.h > index 74e2d92..178b162 100644 > --- a/lib/librte_hash/rte_hash_crc.h > +++ b/lib/librte_hash/rte_hash_crc.h > @@ -45,7 +45,11 @@ extern "C" { > #endif >=20 > #include > +#ifdef RTE_MACHINE_CPUFLAG_SSE4_2 > #include > +#endif > +#include > +#include >=20 > /* Lookup table for software implementation of CRC32C */ > static const uint32_t crc32c_table[256] =3D { > @@ -152,8 +156,42 @@ crc32c_2words(uint64_t data, uint32_t init_val) > return init_val; > } >=20 > +enum crc32_alg_t { > + CRC32_SW =3D 0, > + CRC32_SSE42, > + CRC32_AUTODETECT > +}; > + > +/* Default algorithm is left for autodetection, > + * it is detected on first run of hash function > + */ > +static enum crc32_alg_t crc32_alg =3D CRC32_AUTODETECT; > + > +/** > + * Allow or disallow use of SSE4.2 instrinsics for CRC32 hash > + * hash calculation. > + * > + * @param flag > + * unsigned integer flag > + * - (CRC32_SW) Don't use SSE4.2 intrinsics > + * - (CRC32_SSE42) Use SSE4.2 intrinsics if available, set by default > + */ > +static inline void > +rte_hash_crc_set_alg(enum crc32_alg_t alg) > +{ > + int sse42_supp =3D rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_2); > + enum crc32_alg_t alg_supp =3D sse42_supp ? CRC32_SSE42 : CRC32_SW; > + > + if (alg =3D=3D CRC32_SSE42) > + crc32_alg =3D alg_supp; > + else > + crc32_alg =3D CRC32_SW; > +} > + Wonder can we define that function with __attribute__((constructor))? Then, I suppose we can remove CRC32_AUTODETECT, and remove: if (unlikely(crc32_alg =3D=3D CRC32_AUTODETECT)) rte_hash_crc_set_alg(CRC32_SSE42); =20 from rte_hash_crc_*byte(). Konstantin > /** > * Use single crc32 instruction to perform a hash on a 4 byte value. > + * Fall back to software crc32 implementation in case SSE4.2 is > + * not supported > * > * @param data > * Data to perform hash on. > @@ -165,11 +203,21 @@ crc32c_2words(uint64_t data, uint32_t init_val) > static inline uint32_t > rte_hash_crc_4byte(uint32_t data, uint32_t init_val) > { > - return _mm_crc32_u32(init_val, data); > + if (unlikely(crc32_alg =3D=3D CRC32_AUTODETECT)) > + rte_hash_crc_set_alg(CRC32_SSE42); > + > +#ifdef RTE_MACHINE_CPUFLAG_SSE4_2 > + if (likely(crc32_alg =3D=3D CRC32_SSE42)) > + return _mm_crc32_u32(init_val, data); > +#endif > + > + return crc32c_1word(data, init_val); > } >=20 > /** > * Use single crc32 instruction to perform a hash on a 8 byte value. > + * Fall back to software crc32 implementation in case SSE4.2 is > + * not supported > * > * @param data > * Data to perform hash on. > @@ -181,7 +229,15 @@ rte_hash_crc_4byte(uint32_t data, uint32_t init_val) > static inline uint32_t > rte_hash_crc_8byte(uint64_t data, uint32_t init_val) > { > - return _mm_crc32_u64(init_val, data); > + if (unlikely(crc32_alg =3D=3D CRC32_AUTODETECT)) > + rte_hash_crc_set_alg(CRC32_SSE42); > + > +#ifdef RTE_MACHINE_CPUFLAG_SSE4_2 > + if (likely(crc32_alg =3D=3D CRC32_SSE42)) > + return _mm_crc32_u64(init_val, data); > +#endif > + > + return crc32c_2words(data, init_val); > } >=20 > /** > -- > 1.7.9.5