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From: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
To: "Richardson, Bruce" <bruce.richardson@intel.com>,
	Olivier MATZ <olivier.matz@6wind.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
	"Damjan Marion \(damarion\)" <damarion@cisco.com>
Subject: Re: [dpdk-dev] rte_mbuf.next in 2nd cacheline
Date: Mon, 15 Jun 2015 13:54:19 +0000	[thread overview]
Message-ID: <2601191342CEEE43887BDE71AB97725836A0A838@irsmsx105.ger.corp.intel.com> (raw)
In-Reply-To: <20150615134409.GA7500@bricha3-MOBL3>



> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Bruce Richardson
> Sent: Monday, June 15, 2015 2:44 PM
> To: Olivier MATZ
> Cc: dev@dpdk.org; Damjan Marion (damarion)
> Subject: Re: [dpdk-dev] rte_mbuf.next in 2nd cacheline
> 
> On Mon, Jun 15, 2015 at 03:20:22PM +0200, Olivier MATZ wrote:
> > Hi Damjan,
> >
> > On 06/10/2015 11:47 PM, Damjan Marion (damarion) wrote:
> > >
> > > Hi,
> > >
> > > We noticed 7% performance improvement by simply moving rte_mbuf.next field to the 1st cache line.
> > >
> > > Currently, it falls under /* second cache line - fields only used in slow path or on TX */
> > > but it is actually used at several places in rx fast path. (e.g.: i40e_rx_alloc_bufs() is setting that field to NULL).
> > >
> > > Is there anything we can do here (stop using next field, or move it to 1st cache line)?
> >
> > Agree, this is also something I noticed, see:
> > http://dpdk.org/ml/archives/dev/2015-February/014400.html
> >
> > I did not have the time to do performance testing, but it's something
> > I'd like to do as soon as I can. I don't see any obvious reason not to
> > do it.
> >
> > It seems we currently just have enough room to do it (8 bytes are
> > remaining in the first cache line when compiled in 64 bits).
> 
> This, to me, is the obvious reason not to do it! It prevents us from taking in
> any other offload fields in the RX fast-path into the mbuf.
> 
> That being said, I can see why we might want to look to move it - but from the
> work done in the ixgbe driver, I'd be hopeful we can get as much performance with
> it on the second cache line for most cases, through judicious use of prefetching,
> or otherwise.
> 
> It took a lot of work and investigation to get free space in the mbuf - especially
> in cache line 0, and I'd like to avoid just filling the cache line up again as
> long as we possibly can!

Yep, agree with Bruce here.
Plus, with packet_type going to be 4B and vlan_tci_outer,
we just don't have 8 free bytes at the first cache line any more.
Konstantin

> 
> /Bruce
> 
> >
> >
> > Regards,
> > Olivier
> >
> >
> > >
> > > Thanks,
> > >
> > > Damjan
> > >
> > >
> > >
> > >

  reply	other threads:[~2015-06-15 13:54 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-10 21:47 Damjan Marion (damarion)
2015-06-15 13:20 ` Olivier MATZ
2015-06-15 13:44   ` Bruce Richardson
2015-06-15 13:54     ` Ananyev, Konstantin [this message]
2015-06-15 14:05       ` Olivier MATZ
2015-06-15 14:12         ` Bruce Richardson
2015-06-15 14:30           ` Olivier MATZ
2015-06-15 14:46             ` Bruce Richardson
2015-06-15 14:52             ` Ananyev, Konstantin
2015-06-15 15:19               ` Olivier MATZ
2015-06-15 15:23                 ` Bruce Richardson
2015-06-15 15:28                   ` Ananyev, Konstantin
2015-06-15 15:39                     ` Bruce Richardson
2015-06-15 15:59                       ` Ananyev, Konstantin
2015-06-15 16:02                         ` Bruce Richardson
2015-06-15 16:10                           ` Ananyev, Konstantin
2015-06-15 16:23                             ` Bruce Richardson
2015-06-15 18:34                               ` Ananyev, Konstantin
2015-06-15 20:47                                 ` Stephen Hemminger
2015-06-16  8:20                                   ` Bruce Richardson
2015-06-17 13:55           ` Damjan Marion (damarion)
2015-06-17 14:04             ` Thomas Monjalon
2015-06-17 14:06             ` Bruce Richardson
2015-06-17 14:23               ` Damjan Marion (damarion)
2015-06-17 16:32                 ` Thomas Monjalon
     [not found]               ` <0DE313B5-C9F0-4879-9D92-838ED088202C@cisco.com>
     [not found]                 ` <27EA8870B328F74E88180827A0F816396BD43720@xmb-aln-x10.cisco.com>
     [not found]                   ` <59AF69C657FD0841A61C55336867B5B0345592CD@IRSMSX103.ger.corp.intel.com>
     [not found]                     ` <1FD9B82B8BF2CF418D9A1000154491D97450B186@ORSMSX102.amr.corp.intel.com>
     [not found]                       ` <27EA8870B328F74E88180827A0F816396BD43891@xmb-aln-x10.cisco.com>
     [not found]                         ` <2601191342CEEE43887BDE71AB97725836A1237C@irsmsx105.ger.corp.intel.com>
2015-06-17 18:50                           ` Ananyev, Konstantin

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