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From: "Ananyev, Konstantin" <konstantin.ananyev@intel.com>
To: WangDong <dong.wang.pro@hotmail.com>, "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH 1/2] eal:Introduce rte_dma_wmb/rte_dma_rmb.
Date: Thu, 2 Jul 2015 16:51:53 +0000	[thread overview]
Message-ID: <2601191342CEEE43887BDE71AB97725836A21C12@irsmsx105.ger.corp.intel.com> (raw)
In-Reply-To: <BLU436-SMTP81994005EFD015E8B339BDBFAB0@phx.gbl>



> -----Original Message-----
> From: Ananyev, Konstantin
> Sent: Thursday, July 02, 2015 4:52 PM
> To: 'WangDong'; dev@dpdk.org
> Subject: RE: [dpdk-dev] [PATCH 1/2] eal:Introduce rte_dma_wmb/rte_dma_rmb.
> 
> Hi Dong,
> 
> > -----Original Message-----
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of WangDong
> > Sent: Sunday, June 28, 2015 4:23 PM
> > To: dev@dpdk.org
> > Subject: [dpdk-dev] [PATCH 1/2] eal:Introduce rte_dma_wmb/rte_dma_rmb.
> >
> > These macro can be used to replace current PMD's compiler memory barrier (volatile varible) and rte_wmb.
> > In x86, they implement to compiler memory barrier.
> > In power, they implement to processor memory barrier.
> >
> > ---
> >  .../common/include/arch/ppc_64/rte_atomic.h        |  4 ++++
> >  .../common/include/arch/x86/rte_atomic.h           |  4 ++++
> >  lib/librte_eal/common/include/generic/rte_atomic.h | 25 ++++++++++++++++++++++
> >  3 files changed, 33 insertions(+)
> >
> > diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
> > index fb7af2b..8f4129d 100644
> > --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
> > +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
> > @@ -72,6 +72,10 @@ extern "C" {
> >   */
> >  #define	rte_rmb() {asm volatile("sync" : : : "memory"); }
> >
> > +#define rte_dma_wmb() {asm volatile("sync" : : : "memory"); }
> > +
> > +#define rte_dma_rmb() {asm volatile("sync" : : : "memory");
> 
> As a nit, probably better:
> 
> +#define rte_dma_wmb()  rte_rmb()
> +#define rte_dma_rmb()    rte_wmb()
> 
> Here?
> 
> Konstantin

BTW, forgot to mention, git am threw a warning when I applied tha patch:

$ git am patchv1/5884
Applying: eal:Introduce rte_dma_wmb/rte_dma_rmb.
/local/kananye1/dpdk.org-asmb1/.git/rebase-apply/patch:17: trailing whitespace.
#define rte_dma_rmb() {asm volatile("sync" : : : "memory");
warning: 1 line adds whitespace errors.
 
Konstantin


> 
> > +
> >  /*------------------------- 16 bit atomic operations -------------------------*/
> >  /* To be compatible with Power7, use GCC built-in functions for 16 bit
> >   * operations */
> > diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic.h b/lib/librte_eal/common/include/arch/x86/rte_atomic.h
> > index e93e8ee..7cfbe8f 100644
> > --- a/lib/librte_eal/common/include/arch/x86/rte_atomic.h
> > +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic.h
> > @@ -53,6 +53,10 @@ extern "C" {
> >
> >  #define	rte_rmb() _mm_lfence()
> >
> > +#define rte_dma_wmb() rte_compiler_barrier()
> > +
> > +#define rte_dma_rmb() rte_compiler_barrier()
> > +
> >  /*------------------------- 16 bit atomic operations -------------------------*/
> >
> >  #ifndef RTE_FORCE_INTRINSICS
> > diff --git a/lib/librte_eal/common/include/generic/rte_atomic.h b/lib/librte_eal/common/include/generic/rte_atomic.h
> > index 6c7581a..a51eeee 100644
> > --- a/lib/librte_eal/common/include/generic/rte_atomic.h
> > +++ b/lib/librte_eal/common/include/generic/rte_atomic.h
> > @@ -72,6 +72,31 @@ static inline void rte_wmb(void);
> >   */
> >  static inline void rte_rmb(void);
> >
> > +/**
> > + * Write memory barrier for DMA.
> > + *
> > + * Be used in PMD, unlike rte_wmb() which use processor memory barrier,
> > + * this memory barrier focus on performance, if compiler memory barrier
> > + * is sufficient for guarantee memory ordering, this function will
> > + * use compiler memory barrier.
> > + *
> > + * This function is architecture dependent.
> > + */
> > +static inline void rte_dma_wmb(void);
> > +
> > +/**
> > + * Read memory barrier for DMA.
> > + *
> > + * Be used in PMD, unlike rte_rmb() which use processor memory barrier,
> > + * this memory barrier focus on performance, if compiler memory barrier
> > + * is sufficient for guarantee memory ordering, this function will
> > + * use compiler memory barrier.
> > + *
> > + * This function is architecture dependent.
> > + */
> > +static inline void rte_dma_rmb(void);
> > +
> > +
> >  #endif /* __DOXYGEN__ */
> >
> >  /**
> > --
> > 2.1.0

  parent reply	other threads:[~2015-07-02 16:51 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-06-28 15:23 WangDong
2015-07-02 15:51 ` Ananyev, Konstantin
2015-07-06 15:48   ` Wang Dong
2015-07-02 16:51 ` Ananyev, Konstantin [this message]
  -- strict thread matches above, loose matches on Subject: below --
2015-06-28 15:19 WangDong

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