From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 9A43D8E82 for ; Tue, 20 Oct 2015 15:55:56 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 20 Oct 2015 06:55:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,707,1437462000"; d="scan'208";a="798064918" Received: from irsmsx107.ger.corp.intel.com ([163.33.3.99]) by orsmga001.jf.intel.com with ESMTP; 20 Oct 2015 06:55:53 -0700 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.75]) by IRSMSX107.ger.corp.intel.com ([169.254.10.49]) with mapi id 14.03.0248.002; Tue, 20 Oct 2015 14:55:52 +0100 From: "Ananyev, Konstantin" To: "Lu, Wenzhuo" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2 6/6] ixgbe: implementation for fdir new modes' config Thread-Index: AQHQ+nheBgmo4JdIK0CX+2+wNQ3jI550eD3A Date: Tue, 20 Oct 2015 13:55:52 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836AB2CA7@irsmsx105.ger.corp.intel.com> References: <1443161125-1035-1-git-send-email-wenzhuo.lu@intel.com> <1443504682-17752-1-git-send-email-wenzhuo.lu@intel.com> <1443504682-17752-7-git-send-email-wenzhuo.lu@intel.com> In-Reply-To: <1443504682-17752-7-git-send-email-wenzhuo.lu@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 6/6] ixgbe: implementation for fdir new modes' config X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Oct 2015 13:55:57 -0000 Hi Wenzhuo, Few questions/comments from me, see below. Thanks Konstantin > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Wenzhuo Lu > Sent: Tuesday, September 29, 2015 6:31 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH v2 6/6] ixgbe: implementation for fdir new mod= es' config >=20 > Implement the new CLIs for fdir mac vlan and tunnel modes, including > flow_director_filter and flow_director_mask. Set the mask of fdir. > Add, delete or update the entities of filter. >=20 > Signed-off-by: Wenzhuo Lu > --- > drivers/net/ixgbe/ixgbe_ethdev.h | 3 + > drivers/net/ixgbe/ixgbe_fdir.c | 241 ++++++++++++++++++++++++++++++++-= ------ > 2 files changed, 202 insertions(+), 42 deletions(-) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_e= thdev.h > index c3d4f4f..9cc45a0 100644 > --- a/drivers/net/ixgbe/ixgbe_ethdev.h > +++ b/drivers/net/ixgbe/ixgbe_ethdev.h > @@ -133,6 +133,9 @@ struct ixgbe_hw_fdir_mask { > uint16_t src_port_mask; > uint16_t dst_port_mask; > uint16_t flex_bytes_mask; > + uint8_t mac_addr_mask; > + uint32_t tunnel_id_mask; > + uint8_t tunnel_type_mask; > }; >=20 > struct ixgbe_hw_fdir_info { > diff --git a/drivers/net/ixgbe/ixgbe_fdir.c b/drivers/net/ixgbe/ixgbe_fdi= r.c > index 5c8b833..87e7081 100644 > --- a/drivers/net/ixgbe/ixgbe_fdir.c > +++ b/drivers/net/ixgbe/ixgbe_fdir.c > @@ -105,6 +105,8 @@ > rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\ > } while (0) >=20 > +#define DEFAULT_VXLAN_PORT 4789 > + > static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhas= h); > static int fdir_set_input_mask_82599(struct rte_eth_dev *dev, > const struct rte_eth_fdir_masks *input_mask); > @@ -113,7 +115,8 @@ static int ixgbe_set_fdir_flex_conf(struct rte_eth_de= v *dev, > static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl); > static int ixgbe_fdir_filter_to_atr_input( > const struct rte_eth_fdir_filter *fdir_filter, > - union ixgbe_atr_input *input); > + union ixgbe_atr_input *input, > + enum rte_fdir_mode mode); > static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_= input, > uint32_t key); > static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input, > @@ -122,7 +125,8 @@ static uint32_t atr_compute_perfect_hash_82599(union = ixgbe_atr_input *input, > enum rte_fdir_pballoc_type pballoc); > static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, > union ixgbe_atr_input *input, uint8_t queue, > - uint32_t fdircmd, uint32_t fdirhash); > + uint32_t fdircmd, uint32_t fdirhash, > + enum rte_fdir_mode mode); > static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw, > union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd, > uint32_t fdirhash); > @@ -243,9 +247,15 @@ configure_fdir_flags(const struct rte_fdir_conf *con= f, uint32_t *fdirctrl) > *fdirctrl |=3D (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) << > IXGBE_FDIRCTRL_FLEX_SHIFT; >=20 > - if (conf->mode =3D=3D RTE_FDIR_MODE_PERFECT) { > + if (conf->mode >=3D RTE_FDIR_MODE_PERFECT) { I think better if (conf->mode >=3D RTE_FDIR_MODE_PERFECT && conf->mode <= =3D RTE_FDIR_MODE_PERFECT_TUNNEL) To make sure that future expansion of RTE_FDIR_MODE_* wouldn't break that c= ode. > *fdirctrl |=3D IXGBE_FDIRCTRL_PERFECT_MATCH; > *fdirctrl |=3D (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT); > + if (conf->mode =3D=3D RTE_FDIR_MODE_PERFECT_MAC_VLAN) > + *fdirctrl |=3D (IXGBE_FDIRCTRL_FILTERMODE_MACVLAN > + << IXGBE_FDIRCTRL_FILTERMODE_SHIFT); > + else if (conf->mode =3D=3D RTE_FDIR_MODE_PERFECT_TUNNEL) > + *fdirctrl |=3D (IXGBE_FDIRCTRL_FILTERMODE_CLOUD > + << IXGBE_FDIRCTRL_FILTERMODE_SHIFT); > } >=20 > return 0; > @@ -294,8 +304,18 @@ fdir_set_input_mask_82599(struct rte_eth_dev *dev, > uint16_t dst_ipv6m =3D 0; > uint16_t src_ipv6m =3D 0; >=20 > + enum rte_fdir_mode mode =3D dev->data->dev_conf.fdir_conf.mode; > + > PMD_INIT_FUNC_TRACE(); >=20 > + /* set the default UDP port for VxLAN */ > + IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, DEFAULT_VXLAN_PORT); Hmm, why is that done by default? As I understand it is x550 specific register and is not present in older HW= (82599), no? > + > + /* some bits must be set for mac vlan or tunnel mode */ > + if (mode =3D=3D RTE_FDIR_MODE_PERFECT_MAC_VLAN > + || mode =3D=3D RTE_FDIR_MODE_PERFECT_TUNNEL) > + fdirm |=3D IXGBE_FDIRM_L4P | IXGBE_FDIRM_L3P; > + > /* > * Program the relevant mask registers. If src/dst_port or src/dst_add= r > * are zero, then assume a full mask for that field. Also assume that > @@ -323,26 +343,36 @@ fdir_set_input_mask_82599(struct rte_eth_dev *dev, >=20 > IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); >=20 > - /* store the TCP/UDP port masks, bit reversed from port layout */ > - fdirtcpm =3D reverse_fdir_bitmasks(input_mask->dst_port_mask, > - input_mask->src_port_mask); > - > - /* write all the same so that UDP, TCP and SCTP use the same mask */ > - IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); > - IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); > - IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); > - info->mask.src_port_mask =3D input_mask->src_port_mask; > - info->mask.dst_port_mask =3D input_mask->dst_port_mask; > + if (mode !=3D RTE_FDIR_MODE_PERFECT_MAC_VLAN && > + mode !=3D RTE_FDIR_MODE_PERFECT_TUNNEL) { > + /* > + * store the TCP/UDP port masks, > + * bit reversed from port layout > + */ > + fdirtcpm =3D reverse_fdir_bitmasks(input_mask->dst_port_mask, > + input_mask->src_port_mask); >=20 > - /* Store source and destination IPv4 masks (big-endian) */ > - IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, ~(input_mask->ipv4_mask.src_ip)); > - IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, ~(input_mask->ipv4_mask.dst_ip)); > - info->mask.src_ipv4_mask =3D input_mask->ipv4_mask.src_ip; > - info->mask.dst_ipv4_mask =3D input_mask->ipv4_mask.dst_ip; > + /* > + * write all the same so that UDP, > + * TCP and SCTP use the same mask > + */ > + IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); > + info->mask.src_port_mask =3D input_mask->src_port_mask; > + info->mask.dst_port_mask =3D input_mask->dst_port_mask; > + > + /* Store source and destination IPv4 masks (big-endian) */ > + IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, > + ~(input_mask->ipv4_mask.src_ip)); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, > + ~(input_mask->ipv4_mask.dst_ip)); > + info->mask.src_ipv4_mask =3D input_mask->ipv4_mask.src_ip; > + info->mask.dst_ipv4_mask =3D input_mask->ipv4_mask.dst_ip; > + } >=20 > - if (dev->data->dev_conf.fdir_conf.mode =3D=3D RTE_FDIR_MODE_SIGNATURE) = { > + if (mode =3D=3D RTE_FDIR_MODE_SIGNATURE) { > /* > - * IPv6 mask is only meaningful in signature mode > * Store source and destination IPv6 masks (bit reversed) > */ > IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m); > @@ -354,6 +384,69 @@ fdir_set_input_mask_82599(struct rte_eth_dev *dev, > info->mask.dst_ipv6_mask =3D dst_ipv6m; > } >=20 > + if (mode =3D=3D RTE_FDIR_MODE_PERFECT_MAC_VLAN > + || mode =3D=3D RTE_FDIR_MODE_PERFECT_TUNNEL) { > + fdiripv6m =3D ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT); > + fdiripv6m |=3D IXGBE_FDIRIP6M_ALWAYS_MASK; > + if (mode =3D=3D RTE_FDIR_MODE_PERFECT_MAC_VLAN) > + fdiripv6m |=3D IXGBE_FDIRIP6M_TUNNEL_TYPE | > + IXGBE_FDIRIP6M_TNI_VNI; > + > + switch (input_mask->mac_addr_mask & 0xFF) { > + case 0x00: > + /* Mask inner MAC */ > + fdiripv6m |=3D IXGBE_FDIRIP6M_INNER_MAC; > + break; > + case 0xFF: > + break; > + default: > + PMD_INIT_LOG(ERR, "invalid mac_addr_mask"); > + return -EINVAL; I thought it is possible to mask any byte in MAC... Am I missing something here?=20 > + } > + info->mask.mac_addr_mask =3D input_mask->mac_addr_mask; > + > + if (mode =3D=3D RTE_FDIR_MODE_PERFECT_TUNNEL) { > + switch (input_mask->tunnel_type_mask) { > + case 0: > + /* Mask turnnel type */ > + fdiripv6m |=3D IXGBE_FDIRIP6M_TUNNEL_TYPE; > + break; > + case 1: > + break; > + default: > + PMD_INIT_LOG(ERR, "invalid tunnel_type_mask"); > + return -EINVAL; > + } > + info->mask.tunnel_type_mask =3D > + input_mask->tunnel_type_mask; > + > + switch (input_mask->tunnel_id_mask & 0xFFFFFFFF) { > + case 0x0: > + /* Mask vxlan id */ > + fdiripv6m |=3D IXGBE_FDIRIP6M_TNI_VNI; > + break; > + case 0x00FFFFFF: > + fdiripv6m |=3D IXGBE_FDIRIP6M_TNI_VNI_24; > + break; > + case 0xFFFFFFFF: > + break; > + default: > + PMD_INIT_LOG(ERR, "invalid tunnel_id_mask"); > + return -EINVAL; > + } > + info->mask.tunnel_id_mask =3D > + input_mask->tunnel_id_mask; > + } > + > + IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, fdiripv6m); > + > + IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF); > + } Probably worth to put into a separate function: fdir_set_input_mask_x550() = or something. > + > return IXGBE_SUCCESS; > } >=20 > @@ -431,6 +524,7 @@ ixgbe_fdir_configure(struct rte_eth_dev *dev) > int err; > uint32_t fdirctrl, pbsize; > int i; > + enum rte_fdir_mode mode =3D dev->data->dev_conf.fdir_conf.mode; >=20 > PMD_INIT_FUNC_TRACE(); >=20 > @@ -440,6 +534,13 @@ ixgbe_fdir_configure(struct rte_eth_dev *dev) > hw->mac.type !=3D ixgbe_mac_X550EM_x) > return -ENOSYS; >=20 > + /* x550 supports mac-vlan and tunnel mode but other NICs not */ > + if (hw->mac.type !=3D ixgbe_mac_X550 && > + hw->mac.type !=3D ixgbe_mac_X550EM_x && > + mode !=3D RTE_FDIR_MODE_SIGNATURE && > + mode !=3D RTE_FDIR_MODE_PERFECT) > + return -ENOSYS; > + > err =3D configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl)= ; > if (err) > return err; > @@ -488,7 +589,7 @@ ixgbe_fdir_configure(struct rte_eth_dev *dev) > */ > static int > ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_fi= lter, > - union ixgbe_atr_input *input) > + union ixgbe_atr_input *input, enum rte_fdir_mode mode) > { > input->formatted.vlan_id =3D fdir_filter->input.flow_ext.vlan_tci; > input->formatted.flex_bytes =3D (uint16_t)( > @@ -521,8 +622,7 @@ ixgbe_fdir_filter_to_atr_input(const struct rte_eth_f= dir_filter *fdir_filter, > input->formatted.flow_type =3D IXGBE_ATR_FLOW_TYPE_IPV6; > break; > default: > - PMD_DRV_LOG(ERR, " Error on flow_type input"); > - return -EINVAL; > + break; > } >=20 > switch (fdir_filter->input.flow_type) { > @@ -558,8 +658,23 @@ ixgbe_fdir_filter_to_atr_input(const struct rte_eth_= fdir_filter *fdir_filter, > sizeof(input->formatted.dst_ip)); > break; > default: > - PMD_DRV_LOG(ERR, " Error on flow_type input"); > - return -EINVAL; > + break; > + } > + > + if (mode =3D=3D RTE_FDIR_MODE_PERFECT_MAC_VLAN) { > + rte_memcpy( > + input->formatted.inner_mac, > + fdir_filter->input.flow.mac_vlan_flow.mac_addr.addr_bytes, > + sizeof(input->formatted.inner_mac)); > + } else if (mode =3D=3D RTE_FDIR_MODE_PERFECT_TUNNEL) { > + rte_memcpy( > + input->formatted.inner_mac, > + fdir_filter->input.flow.tunnel_flow.mac_addr.addr_bytes, > + sizeof(input->formatted.inner_mac)); > + input->formatted.tunnel_type =3D > + fdir_filter->input.flow.tunnel_flow.tunnel_type; > + input->formatted.tni_vni =3D > + fdir_filter->input.flow.tunnel_flow.tunnel_id; > } >=20 > return 0; > @@ -743,20 +858,51 @@ atr_compute_sig_hash_82599(union ixgbe_atr_input *i= nput, > static int > fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, > union ixgbe_atr_input *input, uint8_t queue, > - uint32_t fdircmd, uint32_t fdirhash) > + uint32_t fdircmd, uint32_t fdirhash, > + enum rte_fdir_mode mode) > { > uint32_t fdirport, fdirvlan; > + u32 addr_low, addr_high; > + u32 tunnel_type =3D 0; > int err =3D 0; >=20 > - /* record the IPv4 address (big-endian) */ > - IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]); > - IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]); > - > - /* record source and destination port (little-endian)*/ > - fdirport =3D IXGBE_NTOHS(input->formatted.dst_port); > - fdirport <<=3D IXGBE_FDIRPORT_DESTINATION_SHIFT; > - fdirport |=3D IXGBE_NTOHS(input->formatted.src_port); > - IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); > + if (mode =3D=3D RTE_FDIR_MODE_PERFECT) { > + /* record the IPv4 address (big-endian) */ > + IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, > + input->formatted.src_ip[0]); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, > + input->formatted.dst_ip[0]); > + > + /* record source and destination port (little-endian)*/ > + fdirport =3D IXGBE_NTOHS(input->formatted.dst_port); > + fdirport <<=3D IXGBE_FDIRPORT_DESTINATION_SHIFT; > + fdirport |=3D IXGBE_NTOHS(input->formatted.src_port); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); > + } else { else if (mode =3D=3D MAC_VLAN || mode =3D=3D TUNNEL)=20 Again, to avoid breakage with future expansions. > + /* for mac vlan and tunnel modes */ > + addr_low =3D ((u32)input->formatted.inner_mac[0] | > + ((u32)input->formatted.inner_mac[1] << 8) | > + ((u32)input->formatted.inner_mac[2] << 16) | > + ((u32)input->formatted.inner_mac[3] << 24)); > + addr_high =3D ((u32)input->formatted.inner_mac[4] | > + ((u32)input->formatted.inner_mac[5] << 8)); > + > + if (mode =3D=3D RTE_FDIR_MODE_PERFECT_MAC_VLAN) { > + IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), addr_high); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), 0); > + } else { > + /* tunnel mode */ > + if (input->formatted.tunnel_type !=3D > + RTE_FDIR_TUNNEL_TYPE_NVGRE) > + tunnel_type =3D 0x80000000; > + tunnel_type |=3D addr_high; > + IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), tunnel_type); > + IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), > + input->formatted.tni_vni); > + } > + } >=20 > /* record vlan (little-endian) and flex_bytes(big-endian) */ > fdirvlan =3D input->formatted.flex_bytes; > @@ -917,12 +1063,13 @@ ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev, > return -ENOTSUP; > } >=20 > - if (dev->data->dev_conf.fdir_conf.mode =3D=3D RTE_FDIR_MODE_PERFECT) > + if (dev->data->dev_conf.fdir_conf.mode >=3D RTE_FDIR_MODE_PERFECT) > is_perfect =3D TRUE; >=20 > memset(&input, 0, sizeof(input)); >=20 > - err =3D ixgbe_fdir_filter_to_atr_input(fdir_filter, &input); > + err =3D ixgbe_fdir_filter_to_atr_input(fdir_filter, &input, > + dev->data->dev_conf.fdir_conf.mode); > if (err) > return err; >=20 > @@ -966,7 +1113,8 @@ ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev, >=20 > if (is_perfect) { > err =3D fdir_write_perfect_filter_82599(hw, &input, queue, > - fdircmd_flags, fdirhash); > + fdircmd_flags, fdirhash, > + dev->data->dev_conf.fdir_conf.mode); > } else { > err =3D fdir_add_signature_filter_82599(hw, &input, queue, > fdircmd_flags, fdirhash); > @@ -1018,7 +1166,7 @@ ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct= rte_eth_fdir_info *fdir_info > fdir_info->mode =3D dev->data->dev_conf.fdir_conf.mode; > max_num =3D (1 << (FDIRENTRIES_NUM_SHIFT + > (fdirctrl & FDIRCTRL_PBALLOC_MASK))); > - if (fdir_info->mode =3D=3D RTE_FDIR_MODE_PERFECT) > + if (fdir_info->mode >=3D RTE_FDIR_MODE_PERFECT) > fdir_info->guarant_spc =3D max_num; > else if (fdir_info->mode =3D=3D RTE_FDIR_MODE_SIGNATURE) > fdir_info->guarant_spc =3D max_num * 4; > @@ -1032,11 +1180,20 @@ ixgbe_fdir_info_get(struct rte_eth_dev *dev, stru= ct rte_eth_fdir_info *fdir_info > fdir_info->mask.ipv6_mask.dst_ip); > fdir_info->mask.src_port_mask =3D info->mask.src_port_mask; > fdir_info->mask.dst_port_mask =3D info->mask.dst_port_mask; > + fdir_info->mask.mac_addr_mask =3D info->mask.mac_addr_mask; > + fdir_info->mask.tunnel_id_mask =3D info->mask.tunnel_id_mask; > + fdir_info->mask.tunnel_type_mask =3D info->mask.tunnel_type_mask; > fdir_info->max_flexpayload =3D IXGBE_FDIR_MAX_FLEX_LEN; > - fdir_info->flow_types_mask[0] =3D IXGBE_FDIR_FLOW_TYPES; > + > + if (fdir_info->mode =3D=3D RTE_FDIR_MODE_PERFECT_MAC_VLAN > + || fdir_info->mode =3D=3D RTE_FDIR_MODE_PERFECT_TUNNEL) > + fdir_info->flow_types_mask[0] =3D 0; > + else > + fdir_info->flow_types_mask[0] =3D IXGBE_FDIR_FLOW_TYPES; > + > fdir_info->flex_payload_unit =3D sizeof(uint16_t); > fdir_info->max_flex_payload_segment_num =3D 1; > - fdir_info->flex_payload_limit =3D 62; > + fdir_info->flex_payload_limit =3D IXGBE_MAX_FLX_SOURCE_OFF; > fdir_info->flex_conf.nb_payloads =3D 1; > fdir_info->flex_conf.flex_set[0].type =3D RTE_ETH_RAW_PAYLOAD; > fdir_info->flex_conf.flex_set[0].src_offset[0] =3D offset; > @@ -1095,7 +1252,7 @@ ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struc= t rte_eth_fdir_stats *fdir_st > reg =3D IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); > max_num =3D (1 << (FDIRENTRIES_NUM_SHIFT + > (reg & FDIRCTRL_PBALLOC_MASK))); > - if (dev->data->dev_conf.fdir_conf.mode =3D=3D RTE_FDIR_MODE_PERFECT) > + if (dev->data->dev_conf.fdir_conf.mode >=3D RTE_FDIR_MODE_PERFECT) > fdir_stats->guarant_cnt =3D max_num - fdir_stats->free; > else if (dev->data->dev_conf.fdir_conf.mode =3D=3D RTE_FDIR_MODE_SIGNAT= URE) > fdir_stats->guarant_cnt =3D max_num * 4 - fdir_stats->free; > -- > 1.9.3