From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 3D35F5A6C for ; Mon, 2 Nov 2015 17:54:53 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP; 02 Nov 2015 08:54:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,234,1444719600"; d="scan'208";a="592623632" Received: from irsmsx101.ger.corp.intel.com ([163.33.3.153]) by FMSMGA003.fm.intel.com with ESMTP; 02 Nov 2015 08:54:25 -0800 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.75]) by IRSMSX101.ger.corp.intel.com ([169.254.1.33]) with mapi id 14.03.0248.002; Mon, 2 Nov 2015 16:54:24 +0000 From: "Ananyev, Konstantin" To: Jerin Jacob , "dev@dpdk.org" Thread-Topic: [PATCH 2/3] arm64: acl: add neon based acl implementation Thread-Index: AQHRFXmY1zN5Lln6OkywaSyh4UxBO56I8ckg Date: Mon, 2 Nov 2015 16:54:24 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836AB86A5@irsmsx105.ger.corp.intel.com> References: <1446473921-12706-1-git-send-email-jerin.jacob@caviumnetworks.com> <1446473921-12706-2-git-send-email-jerin.jacob@caviumnetworks.com> <1446473921-12706-3-git-send-email-jerin.jacob@caviumnetworks.com> In-Reply-To: <1446473921-12706-3-git-send-email-jerin.jacob@caviumnetworks.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 2/3] arm64: acl: add neon based acl implementation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Nov 2015 16:54:53 -0000 Hi Jacob, > diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c > index d60219f..e2fdebd 100644 > --- a/lib/librte_acl/rte_acl.c > +++ b/lib/librte_acl/rte_acl.c > @@ -55,11 +55,32 @@ rte_acl_classify_avx2(__rte_unused const struct rte_a= cl_ctx *ctx, > return -ENOTSUP; > } >=20 > +int __attribute__ ((weak)) > +rte_acl_classify_sse(__rte_unused const struct rte_acl_ctx *ctx, > + __rte_unused const uint8_t **data, > + __rte_unused uint32_t *results, > + __rte_unused uint32_t num, > + __rte_unused uint32_t categories) > +{ > + return -ENOTSUP; > +} > + > +int __attribute__ ((weak)) > +rte_acl_classify_neon(__rte_unused const struct rte_acl_ctx *ctx, > + __rte_unused const uint8_t **data, > + __rte_unused uint32_t *results, > + __rte_unused uint32_t num, > + __rte_unused uint32_t categories) > +{ > + return -ENOTSUP; > +} > + > static const rte_acl_classify_t classify_fns[] =3D { > [RTE_ACL_CLASSIFY_DEFAULT] =3D rte_acl_classify_scalar, > [RTE_ACL_CLASSIFY_SCALAR] =3D rte_acl_classify_scalar, > [RTE_ACL_CLASSIFY_SSE] =3D rte_acl_classify_sse, > [RTE_ACL_CLASSIFY_AVX2] =3D rte_acl_classify_avx2, > + [RTE_ACL_CLASSIFY_NEON] =3D rte_acl_classify_neon, > }; >=20 > /* by default, use always available scalar code path. */ > @@ -93,6 +114,9 @@ rte_acl_init(void) > { > enum rte_acl_classify_alg alg =3D RTE_ACL_CLASSIFY_DEFAULT; >=20 > +#ifdef RTE_ARCH_ARM64 > + alg =3D RTE_ACL_CLASSIFY_NEON; > +#else On ARM, is there any specific cpu flag that you can use to determine is NEO= N isa is supported or not? It would be good to avoid extra conditional compilation here if possible. Another question - did I get it right that NEON isa is supported on all possible RTE_ARCH_ARM64 cpu models you plan to support? Konstantin