From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id EE352378E for ; Tue, 3 Nov 2015 11:23:58 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 03 Nov 2015 02:23:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,238,1444719600"; d="scan'208";a="841912999" Received: from irsmsx106.ger.corp.intel.com ([163.33.3.31]) by fmsmga002.fm.intel.com with ESMTP; 03 Nov 2015 02:23:56 -0800 Received: from irsmsx111.ger.corp.intel.com (10.108.20.4) by IRSMSX106.ger.corp.intel.com (163.33.3.31) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 3 Nov 2015 10:23:56 +0000 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.75]) by irsmsx111.ger.corp.intel.com ([169.254.2.212]) with mapi id 14.03.0248.002; Tue, 3 Nov 2015 10:23:56 +0000 From: "Ananyev, Konstantin" To: Jerin Jacob Thread-Topic: [PATCH 2/3] arm64: acl: add neon based acl implementation Thread-Index: AQHRFXmY1zN5Lln6OkywaSyh4UxBO56I8ckggADEH4CAAGDnQA== Date: Tue, 3 Nov 2015 10:23:55 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836AB8AA2@irsmsx105.ger.corp.intel.com> References: <1446473921-12706-1-git-send-email-jerin.jacob@caviumnetworks.com> <1446473921-12706-2-git-send-email-jerin.jacob@caviumnetworks.com> <1446473921-12706-3-git-send-email-jerin.jacob@caviumnetworks.com> <2601191342CEEE43887BDE71AB97725836AB86A5@irsmsx105.ger.corp.intel.com> <20151103043051.GA2228@localhost.localdomain> In-Reply-To: <20151103043051.GA2228@localhost.localdomain> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] [PATCH 2/3] arm64: acl: add neon based acl implementation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Nov 2015 10:23:59 -0000 Hi Jacob, > -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Tuesday, November 03, 2015 4:31 AM > To: Ananyev, Konstantin > Cc: dev@dpdk.org; thomas.monjalon@6wind.com; Hunt, David; viktorin@rehive= tech.com > Subject: Re: [PATCH 2/3] arm64: acl: add neon based acl implementation >=20 > On Mon, Nov 02, 2015 at 04:54:24PM +0000, Ananyev, Konstantin wrote: > > Hi Jacob, > > > > > diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c > > > index d60219f..e2fdebd 100644 > > > --- a/lib/librte_acl/rte_acl.c > > > +++ b/lib/librte_acl/rte_acl.c > > > @@ -55,11 +55,32 @@ rte_acl_classify_avx2(__rte_unused const struct r= te_acl_ctx *ctx, > > > return -ENOTSUP; > > > } > > > > > > +int __attribute__ ((weak)) > > > +rte_acl_classify_sse(__rte_unused const struct rte_acl_ctx *ctx, > > > + __rte_unused const uint8_t **data, > > > + __rte_unused uint32_t *results, > > > + __rte_unused uint32_t num, > > > + __rte_unused uint32_t categories) > > > +{ > > > + return -ENOTSUP; > > > +} > > > + > > > +int __attribute__ ((weak)) > > > +rte_acl_classify_neon(__rte_unused const struct rte_acl_ctx *ctx, > > > + __rte_unused const uint8_t **data, > > > + __rte_unused uint32_t *results, > > > + __rte_unused uint32_t num, > > > + __rte_unused uint32_t categories) > > > +{ > > > + return -ENOTSUP; > > > +} > > > + > > > static const rte_acl_classify_t classify_fns[] =3D { > > > [RTE_ACL_CLASSIFY_DEFAULT] =3D rte_acl_classify_scalar, > > > [RTE_ACL_CLASSIFY_SCALAR] =3D rte_acl_classify_scalar, > > > [RTE_ACL_CLASSIFY_SSE] =3D rte_acl_classify_sse, > > > [RTE_ACL_CLASSIFY_AVX2] =3D rte_acl_classify_avx2, > > > + [RTE_ACL_CLASSIFY_NEON] =3D rte_acl_classify_neon, > > > }; > > > > > > /* by default, use always available scalar code path. */ > > > @@ -93,6 +114,9 @@ rte_acl_init(void) > > > { > > > enum rte_acl_classify_alg alg =3D RTE_ACL_CLASSIFY_DEFAULT; > > > > > > +#ifdef RTE_ARCH_ARM64 > > > + alg =3D RTE_ACL_CLASSIFY_NEON; > > > +#else >=20 > Hi Konstantin, > > > > On ARM, is there any specific cpu flag that you can use to determine is= NEON > > isa is supported or not? >=20 > Yes, on armv7(RTE_CPUFLAG_NEON). On armv8-a NEON is mandatory. >=20 > > It would be good to avoid extra conditional compilation here if possibl= e. > neon acl is verified/ported only on armv8. While adding the armv7 support= the > check can be extended for cpuflag based on RTE_CPUFLAG_NEON on armv7 Ok, and is there a flag that allows to distinguish between armv7 and arm8 t= hen at runtime? It is probably ok like that, but with all that conditional compilations it = gets too messy. Another thing - if you can distinguish between armv7 and armv8 at runtime, = then you probably can set alg =3D RTE_ACL_CLASSIFY_DEFAULT for armv7 and alg =3D RTE_ACL_CLAS= SIFY_NEON for arm8? Konstantin >=20 > > Another question - did I get it right that NEON isa is supported on all > > possible RTE_ARCH_ARM64 cpu models you plan to support? >=20 > Yes >=20 > > Konstantin > > > >