From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id AFBA437A4 for ; Tue, 3 Nov 2015 16:57:32 +0100 (CET) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP; 03 Nov 2015 07:57:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,239,1444719600"; d="scan'208";a="841609919" Received: from irsmsx108.ger.corp.intel.com ([163.33.3.3]) by orsmga002.jf.intel.com with ESMTP; 03 Nov 2015 07:57:32 -0800 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.75]) by IRSMSX108.ger.corp.intel.com ([169.254.11.138]) with mapi id 14.03.0248.002; Tue, 3 Nov 2015 15:57:24 +0000 From: "Ananyev, Konstantin" To: Jerin Jacob , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter Thread-Index: AQHRFk/G1QYZXbLuaU2JRfi6HnPKFJ6Kc5LA Date: Tue, 3 Nov 2015 15:57:24 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836AB8F01@irsmsx105.ger.corp.intel.com> References: <1446565921-18088-1-git-send-email-jerin.jacob@caviumnetworks.com> In-Reply-To: <1446565921-18088-1-git-send-email-jerin.jacob@caviumnetworks.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM_OPS configuration parameter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Nov 2015 15:57:33 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob > Sent: Tuesday, November 03, 2015 3:52 PM > To: dev@dpdk.org > Subject: [dpdk-dev] [RFC ][PATCH] Introduce RTE_ARCH_STRONGLY_ORDERED_MEM= _OPS configuration parameter >=20 > rte_ring implementation needs explicit memory barrier > in weakly ordered architecture like ARM unlike > strongly ordered architecture like X86 >=20 > Introducing RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > configuration to abstract such dependency so that other > weakly ordered architectures can reuse this infrastructure. Looks a bit clumsy. Please try to follow this suggestion instead: http://dpdk.org/ml/archives/dev/2015-October/025505.html Konstantin >=20 > Signed-off-by: Jerin Jacob > --- > config/common_bsdapp | 5 +++++ > config/common_linuxapp | 5 +++++ > config/defconfig_arm64-armv8a-linuxapp-gcc | 1 + > config/defconfig_arm64-thunderx-linuxapp-gcc | 1 + > lib/librte_ring/rte_ring.h | 20 ++++++++++++++++++++ > 5 files changed, 32 insertions(+) >=20 > diff --git a/config/common_bsdapp b/config/common_bsdapp > index b37dcf4..c8d1f63 100644 > --- a/config/common_bsdapp > +++ b/config/common_bsdapp > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=3Dn > CONFIG_RTE_ARCH_STRICT_ALIGN=3Dn >=20 > # > +# Machine has strongly-ordered memory operations on normal memory like x= 86 > +# > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=3Dy > + > +# > # Compile to share library > # > CONFIG_RTE_BUILD_SHARED_LIB=3Dn > diff --git a/config/common_linuxapp b/config/common_linuxapp > index 0de43d5..d040a74 100644 > --- a/config/common_linuxapp > +++ b/config/common_linuxapp > @@ -79,6 +79,11 @@ CONFIG_RTE_FORCE_INTRINSICS=3Dn > CONFIG_RTE_ARCH_STRICT_ALIGN=3Dn >=20 > # > +# Machine has strongly-ordered memory operations on normal memory like x= 86 > +# > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=3Dy > + > +# > # Compile to share library > # > CONFIG_RTE_BUILD_SHARED_LIB=3Dn > diff --git a/config/defconfig_arm64-armv8a-linuxapp-gcc b/config/defconfi= g_arm64-armv8a-linuxapp-gcc > index 6ea38a5..5289152 100644 > --- a/config/defconfig_arm64-armv8a-linuxapp-gcc > +++ b/config/defconfig_arm64-armv8a-linuxapp-gcc > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH=3D"arm64" > CONFIG_RTE_ARCH_ARM64=3Dy > CONFIG_RTE_ARCH_64=3Dy > CONFIG_RTE_ARCH_ARM_NEON=3Dy > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=3Dn >=20 > CONFIG_RTE_FORCE_INTRINSICS=3Dy >=20 > diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defcon= fig_arm64-thunderx-linuxapp-gcc > index e8fccc7..79fa9e6 100644 > --- a/config/defconfig_arm64-thunderx-linuxapp-gcc > +++ b/config/defconfig_arm64-thunderx-linuxapp-gcc > @@ -37,6 +37,7 @@ CONFIG_RTE_ARCH=3D"arm64" > CONFIG_RTE_ARCH_ARM64=3Dy > CONFIG_RTE_ARCH_64=3Dy > CONFIG_RTE_ARCH_ARM_NEON=3Dy > +CONFIG_RTE_ARCH_STRONGLY_ORDERED_MEM_OPS=3Dn >=20 > CONFIG_RTE_FORCE_INTRINSICS=3Dy >=20 > diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h > index af68888..1ccd186 100644 > --- a/lib/librte_ring/rte_ring.h > +++ b/lib/librte_ring/rte_ring.h > @@ -457,7 +457,12 @@ __rte_ring_mp_do_enqueue(struct rte_ring *r, void * = const *obj_table, >=20 > /* write entries in ring */ > ENQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_wmb(); > +#endif >=20 > /* if we exceed the watermark */ > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > @@ -552,7 +557,12 @@ __rte_ring_sp_do_enqueue(struct rte_ring *r, void * = const *obj_table, >=20 > /* write entries in ring */ > ENQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_wmb(); > +#endif >=20 > /* if we exceed the watermark */ > if (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) { > @@ -643,7 +653,12 @@ __rte_ring_mc_do_dequeue(struct rte_ring *r, void **= obj_table, >=20 > /* copy in table */ > DEQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_rmb(); > +#endif >=20 > /* > * If there are other dequeues in progress that preceded us, > @@ -727,7 +742,12 @@ __rte_ring_sc_do_dequeue(struct rte_ring *r, void **= obj_table, >=20 > /* copy in table */ > DEQUEUE_PTRS(); > + > +#ifdef RTE_ARCH_STRONGLY_ORDERED_MEM_OPS > rte_compiler_barrier(); > +#else > + rte_rmb(); > +#endif >=20 > __RING_STAT_ADD(r, deq_success, n); > r->cons.tail =3D cons_next; > -- > 2.1.0