From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 08E6B95DE for ; Mon, 7 Dec 2015 16:21:36 +0100 (CET) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP; 07 Dec 2015 07:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,395,1444719600"; d="scan'208";a="8933089" Received: from irsmsx109.ger.corp.intel.com ([163.33.3.23]) by fmsmga004.fm.intel.com with ESMTP; 07 Dec 2015 07:21:35 -0800 Received: from irsmsx155.ger.corp.intel.com (163.33.192.3) by IRSMSX109.ger.corp.intel.com (163.33.3.23) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 7 Dec 2015 15:21:33 +0000 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.203]) by irsmsx155.ger.corp.intel.com ([169.254.14.190]) with mapi id 14.03.0248.002; Mon, 7 Dec 2015 15:21:33 +0000 From: "Ananyev, Konstantin" To: Jerin Jacob , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 1/2] mbuf: fix performance/cache resource issue with 128-byte cache line targets Thread-Index: AQHRMD83I2PPlXB2GkuW7U0sf/5hWZ6/lqgQ Date: Mon, 7 Dec 2015 15:21:33 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836AD15BE@irsmsx105.ger.corp.intel.com> References: <1449417564-29600-1-git-send-email-jerin.jacob@caviumnetworks.com> <1449417564-29600-2-git-send-email-jerin.jacob@caviumnetworks.com> In-Reply-To: <1449417564-29600-2-git-send-email-jerin.jacob@caviumnetworks.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 1/2] mbuf: fix performance/cache resource issue with 128-byte cache line targets X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Dec 2015 15:21:37 -0000 Hi Jerin, > -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Sunday, December 06, 2015 3:59 PM > To: dev@dpdk.org > Cc: thomas.monjalon@6wind.com; Richardson, Bruce; olivier.matz@6wind.com;= Dumitrescu, Cristian; Ananyev, Konstantin; Jerin > Jacob > Subject: [dpdk-dev] [PATCH 1/2] mbuf: fix performance/cache resource issu= e with 128-byte cache line targets >=20 > No need to split mbuf structure to two cache lines for 128-byte cache lin= e > size targets as it can fit on a single 128-byte cache line. >=20 > Signed-off-by: Jerin Jacob > --- > app/test/test_mbuf.c | 4 ++++ > lib/librte_eal/linuxapp/eal/include/exec-env/rte_kni_common.h | 4 ++++ > lib/librte_mbuf/rte_mbuf.h | 2 ++ > 3 files changed, 10 insertions(+) >=20 > diff --git a/app/test/test_mbuf.c b/app/test/test_mbuf.c > index b32bef6..5e21075 100644 > --- a/app/test/test_mbuf.c > +++ b/app/test/test_mbuf.c > @@ -930,7 +930,11 @@ test_failing_mbuf_sanity_check(void) > static int > test_mbuf(void) > { > +#if RTE_CACHE_LINE_SIZE =3D=3D 64 > RTE_BUILD_BUG_ON(sizeof(struct rte_mbuf) !=3D RTE_CACHE_LINE_SIZE * 2); > +#elif RTE_CACHE_LINE_SIZE =3D=3D 128 > + RTE_BUILD_BUG_ON(sizeof(struct rte_mbuf) !=3D RTE_CACHE_LINE_SIZE); > +#endif >=20 > /* create pktmbuf pool if it does not exist */ > if (pktmbuf_pool =3D=3D NULL) { > diff --git a/lib/librte_eal/linuxapp/eal/include/exec-env/rte_kni_common.= h b/lib/librte_eal/linuxapp/eal/include/exec- > env/rte_kni_common.h > index bd1cc09..e724af7 100644 > --- a/lib/librte_eal/linuxapp/eal/include/exec-env/rte_kni_common.h > +++ b/lib/librte_eal/linuxapp/eal/include/exec-env/rte_kni_common.h > @@ -121,8 +121,12 @@ struct rte_kni_mbuf { > uint32_t pkt_len; /**< Total pkt len: sum of all segment data_len= . */ > uint16_t data_len; /**< Amount of data in segment buffer. */ >=20 > +#if RTE_CACHE_LINE_SIZE =3D=3D 64 > /* fields on second cache line */ > char pad3[8] __attribute__((__aligned__(RTE_CACHE_LINE_SIZE))); > +#elif RTE_CACHE_LINE_SIZE =3D=3D 128 > + char pad3[24]; > +#endif > void *pool; > void *next; > }; > diff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h > index f234ac9..0bf55e0 100644 > --- a/lib/librte_mbuf/rte_mbuf.h > +++ b/lib/librte_mbuf/rte_mbuf.h > @@ -813,8 +813,10 @@ struct rte_mbuf { >=20 > uint16_t vlan_tci_outer; /**< Outer VLAN Tag Control Identifier (CPU o= rder) */ >=20 > +#if RTE_CACHE_LINE_SIZE =3D=3D 64 > /* second cache line - fields only used in slow path or on TX */ > MARKER cacheline1 __rte_cache_aligned; > +#endif I suppose you'll need to keep same space reserved for first 64B even on sys= tems with 128B cache-line. Otherwise we can endup with different mbuf format for systems with 128B cac= he-line. Another thing - now we have __rte_cache_aligned all over the places, and I = don't know is to double=20 sizes of all these structures is a good idea.=20 Again, #if RTE_CACHE_LINE_SIZE =3D=3D 64 ... all over the places looks a b= it clumsy. Wonder can we have __rte_cache_aligned/ RTE_CACHE_LINE_SIZE architecture sp= ecific, but introduce RTE_CACHE_MIN_LINE_SIZE(=3D=3D64)/ __rte_cache_min_aligned an= d used it for mbuf (and might be other places). Konstantin