From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 91C2395DE for ; Thu, 4 Feb 2016 19:55:13 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 04 Feb 2016 10:55:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,396,1449561600"; d="scan'208";a="877162170" Received: from irsmsx101.ger.corp.intel.com ([163.33.3.153]) by orsmga001.jf.intel.com with ESMTP; 04 Feb 2016 10:55:11 -0800 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.237]) by IRSMSX101.ger.corp.intel.com ([169.254.1.113]) with mapi id 14.03.0248.002; Thu, 4 Feb 2016 18:55:10 +0000 From: "Ananyev, Konstantin" To: "Lu, Wenzhuo" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2 5/6] ixgbe: support VxLAN & NVGRE TX checksum off-load Thread-Index: AQHRTmx6pDjluNdEOkuM1xLphszVbZ8cWdZw Date: Thu, 4 Feb 2016 18:55:10 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836B03304@irsmsx105.ger.corp.intel.com> References: <1452496044-17524-1-git-send-email-wenzhuo.lu@intel.com> <1452735516-4527-1-git-send-email-wenzhuo.lu@intel.com> <1452735516-4527-6-git-send-email-wenzhuo.lu@intel.com> In-Reply-To: <1452735516-4527-6-git-send-email-wenzhuo.lu@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 5/6] ixgbe: support VxLAN & NVGRE TX checksum off-load X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Feb 2016 18:55:14 -0000 Hi Wenzhuo, > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Wenzhuo Lu > Sent: Thursday, January 14, 2016 1:39 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH v2 5/6] ixgbe: support VxLAN & NVGRE TX checks= um off-load >=20 > The patch add VxLAN & NVGRE TX checksum off-load. When the flag of > outer IP header checksum offload is set, we'll set the context > descriptor to enable this checksum off-load. >=20 > Signed-off-by: Wenzhuo Lu > --- > drivers/net/ixgbe/ixgbe_rxtx.c | 52 ++++++++++++++++++++++++++++++++++--= ------ > drivers/net/ixgbe/ixgbe_rxtx.h | 6 ++++- > lib/librte_mbuf/rte_mbuf.h | 2 ++ > 3 files changed, 49 insertions(+), 11 deletions(-) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxt= x.c > index 512ac3a..fea2495 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > @@ -85,7 +85,8 @@ > PKT_TX_VLAN_PKT | \ > PKT_TX_IP_CKSUM | \ > PKT_TX_L4_MASK | \ > - PKT_TX_TCP_SEG) > + PKT_TX_TCP_SEG | \ > + PKT_TX_OUTER_IP_CKSUM) I think you also need to update dev_info.tx_offload_capa, couldn't find where you doing it. >=20 > static inline struct rte_mbuf * > rte_rxmbuf_alloc(struct rte_mempool *mp) > @@ -364,9 +365,11 @@ ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq, > uint32_t ctx_idx; > uint32_t vlan_macip_lens; > union ixgbe_tx_offload tx_offload_mask; > + uint32_t seqnum_seed =3D 0; >=20 > ctx_idx =3D txq->ctx_curr; > - tx_offload_mask.data =3D 0; > + tx_offload_mask.data[0] =3D 0; > + tx_offload_mask.data[1] =3D 0; > type_tucmd_mlhl =3D 0; >=20 > /* Specify which HW CTX to upload. */ > @@ -430,9 +433,20 @@ ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq, > } > } >=20 > + if (ol_flags & PKT_TX_OUTER_IP_CKSUM) { > + tx_offload_mask.outer_l3_len |=3D ~0; > + tx_offload_mask.outer_l2_len |=3D ~0; > + seqnum_seed |=3D tx_offload.outer_l3_len > + << IXGBE_ADVTXD_OUTER_IPLEN; > + seqnum_seed |=3D tx_offload.outer_l2_len > + << IXGBE_ADVTXD_TUNNEL_LEN; > + } I don't have an X550 card off-hand, but reading through datasheet - it does= n't seem right. When OUTER_IP_CKSUM is enabled MACLEN becomes outer_l2_len and=20 TUNNEL_LEN should be: outer_l4_len + tunnel_hdr_len + inner_l2_len. So I think that in our case TUNNEL_LEN should be set to l2_len.=20 > + > txq->ctx_cache[ctx_idx].flags =3D ol_flags; > - txq->ctx_cache[ctx_idx].tx_offload.data =3D > - tx_offload_mask.data & tx_offload.data; > + txq->ctx_cache[ctx_idx].tx_offload.data[0] =3D > + tx_offload_mask.data[0] & tx_offload.data[0]; > + txq->ctx_cache[ctx_idx].tx_offload.data[1] =3D > + tx_offload_mask.data[1] & tx_offload.data[1]; > txq->ctx_cache[ctx_idx].tx_offload_mask =3D tx_offload_mask; >=20 > ctx_txd->type_tucmd_mlhl =3D rte_cpu_to_le_32(type_tucmd_mlhl); > @@ -441,7 +455,7 @@ ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq, > vlan_macip_lens |=3D ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLA= N_SHIFT); > ctx_txd->vlan_macip_lens =3D rte_cpu_to_le_32(vlan_macip_lens); > ctx_txd->mss_l4len_idx =3D rte_cpu_to_le_32(mss_l4len_idx); > - ctx_txd->seqnum_seed =3D 0; > + ctx_txd->seqnum_seed =3D seqnum_seed; > } >=20 > /* > @@ -454,16 +468,24 @@ what_advctx_update(struct ixgbe_tx_queue *txq, uint= 64_t flags, > { > /* If match with the current used context */ > if (likely((txq->ctx_cache[txq->ctx_curr].flags =3D=3D flags) && > - (txq->ctx_cache[txq->ctx_curr].tx_offload.data =3D=3D > - (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)= ))) { > + (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] =3D=3D > + (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0] > + & tx_offload.data[0])) && > + (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] =3D=3D > + (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1] > + & tx_offload.data[1])))) { > return txq->ctx_curr; > } >=20 > /* What if match with the next context */ > txq->ctx_curr ^=3D 1; > if (likely((txq->ctx_cache[txq->ctx_curr].flags =3D=3D flags) && > - (txq->ctx_cache[txq->ctx_curr].tx_offload.data =3D=3D > - (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)= ))) { > + (txq->ctx_cache[txq->ctx_curr].tx_offload.data[0] =3D=3D > + (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[0] > + & tx_offload.data[0])) && > + (txq->ctx_cache[txq->ctx_curr].tx_offload.data[1] =3D=3D > + (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data[1] > + & tx_offload.data[1])))) { > return txq->ctx_curr; > } >=20 > @@ -492,6 +514,12 @@ tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags) > cmdtype |=3D IXGBE_ADVTXD_DCMD_VLE; > if (ol_flags & PKT_TX_TCP_SEG) > cmdtype |=3D IXGBE_ADVTXD_DCMD_TSE; > + if (ol_flags & PKT_TX_OUTER_IP_CKSUM) > + cmdtype |=3D (1 << IXGBE_ADVTXD_OUTERIPCS_SHIFT); > + if (ol_flags & PKT_TX_VXLAN_PKT) > + cmdtype &=3D ~(1 << IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE); > + else > + cmdtype |=3D (1 << IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE); > return cmdtype; > } >=20 > @@ -588,8 +616,10 @@ ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx= _pkts, > uint64_t tx_ol_req; > uint32_t ctx =3D 0; > uint32_t new_ctx; > - union ixgbe_tx_offload tx_offload =3D {0}; > + union ixgbe_tx_offload tx_offload; >=20 > + tx_offload.data[0] =3D 0; > + tx_offload.data[1] =3D 0; > txq =3D tx_queue; > sw_ring =3D txq->sw_ring; > txr =3D txq->tx_ring; > @@ -623,6 +653,8 @@ ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_= pkts, > tx_offload.l4_len =3D tx_pkt->l4_len; > tx_offload.vlan_tci =3D tx_pkt->vlan_tci; > tx_offload.tso_segsz =3D tx_pkt->tso_segsz; > + tx_offload.outer_l2_len =3D tx_pkt->outer_l2_len; > + tx_offload.outer_l3_len =3D tx_pkt->outer_l3_len; >=20 > /* If new context need be built or reuse the exist ctx. */ > ctx =3D what_advctx_update(txq, tx_ol_req, > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.h b/drivers/net/ixgbe/ixgbe_rxt= x.h > index 475a800..c15f9fa 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.h > +++ b/drivers/net/ixgbe/ixgbe_rxtx.h > @@ -163,7 +163,7 @@ enum ixgbe_advctx_num { >=20 > /** Offload features */ > union ixgbe_tx_offload { > - uint64_t data; > + uint64_t data[2]; I wonder what is there any performance impact of increasing size of tx_offl= oad? > struct { > uint64_t l2_len:7; /**< L2 (MAC) Header Length. */ > uint64_t l3_len:9; /**< L3 (IP) Header Length. */ > @@ -171,6 +171,10 @@ union ixgbe_tx_offload { > uint64_t tso_segsz:16; /**< TCP TSO segment size */ > uint64_t vlan_tci:16; > /**< VLAN Tag Control Identifier (CPU order). */ > + > + /* fields for TX offloading of tunnels */ > + uint64_t outer_l3_len:8; /**< Outer L3 (IP) Hdr Length. */ > + uint64_t outer_l2_len:8; /**< Outer L2 (MAC) Hdr Length. */ > }; > }; >=20 > diff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h > index 5ad5e59..1bda00e 100644 > --- a/lib/librte_mbuf/rte_mbuf.h > +++ b/lib/librte_mbuf/rte_mbuf.h > @@ -103,6 +103,8 @@ extern "C" { >=20 > /* add new TX flags here */ >=20 > +#define PKT_TX_VXLAN_PKT (1ULL << 48) /**< TX packet is a VxLAN pac= ket. */ > + >>From reading X550 spec, I don't really understand what for we need to speci= fy is it GRE or VXLAN packet, so probably we don't need that flag for now at all? If we really do, might bw worth to organise it like KT_TX_L4_CKSUM (as enum= ) and reserve few values for future expansion (2 or 3 bits?). Konstantin