From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 0132B559A for ; Fri, 29 Jul 2016 10:45:45 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 29 Jul 2016 01:45:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,438,1464678000"; d="scan'208";a="1031377169" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by fmsmga002.fm.intel.com with ESMTP; 29 Jul 2016 01:45:44 -0700 Received: from irsmsx155.ger.corp.intel.com (163.33.192.3) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 29 Jul 2016 09:45:43 +0100 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.102]) by irsmsx155.ger.corp.intel.com ([169.254.14.102]) with mapi id 14.03.0248.002; Fri, 29 Jul 2016 09:45:42 +0100 From: "Ananyev, Konstantin" To: "Tan, Jianfeng" , "dev@dpdk.org" CC: "Wu, Jingjing" Thread-Topic: [dpdk-dev] [PATCH v3] i40: fix the VXLAN TSO issue Thread-Index: AQHR4OuRj8tsDfn/UEOgoq07xjxfg6Au/l6AgAAp6VA= Date: Fri, 29 Jul 2016 08:45:42 +0000 Message-ID: <2601191342CEEE43887BDE71AB97725836B8AF7D@irsmsx105.ger.corp.intel.com> References: <1467865627-23524-1-git-send-email-zhe.tao@intel.com> <1468843009-14517-1-git-send-email-zhe.tao@intel.com> <3d08c8b3-fc33-ddbc-196b-c43a65d5779f@intel.com> In-Reply-To: <3d08c8b3-fc33-ddbc-196b-c43a65d5779f@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3] i40: fix the VXLAN TSO issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jul 2016 08:45:46 -0000 Hi Jianfeng, >=20 > Hi, >=20 > On 7/18/2016 7:56 PM, Zhe Tao wrote: > > Problem: > > When using the TSO + VXLAN feature in i40e, the outer UDP length > > fields in the multiple UDP segments which are TSOed by the i40e will > > have a wrong value. > > > > Fix this problem by adding the tunnel type field in the i40e > > descriptor which was missed before. > > > > Fixes: 77b8301733c3 ("i40e: VXLAN Tx checksum offload") > > > > Signed-off-by: Zhe Tao > > --- > > v2: edited the comments > > v3: added external IP offload flag when TSO is enabled for tunnelling > > packets > > > > app/test-pmd/csumonly.c | 29 +++++++++++++++++++++-------- > > drivers/net/i40e/i40e_rxtx.c | 12 +++++++++--- > > lib/librte_mbuf/rte_mbuf.h | 16 +++++++++++++++- > > 3 files changed, 45 insertions(+), 12 deletions(-) > > > ... > > diff --git a/lib/librte_mbuf/rte_mbuf.h b/lib/librte_mbuf/rte_mbuf.h > > index 15e3a10..90812ea 100644 > > --- a/lib/librte_mbuf/rte_mbuf.h > > +++ b/lib/librte_mbuf/rte_mbuf.h > > @@ -133,6 +133,17 @@ extern "C" { > > /* add new TX flags here */ > > > > /** > > + * Bits 45:48 used for the tunnel type. > > + * When doing Tx offload like TSO or checksum, the HW needs to > > +configure the > > + * tunnel type into the HW descriptors. > > + */ > > +#define PKT_TX_TUNNEL_VXLAN (1ULL << 45) > > +#define PKT_TX_TUNNEL_GRE (2ULL << 45) > > +#define PKT_TX_TUNNEL_IPIP (3ULL << 45) > > +/* add new TX TUNNEL type here */ > > +#define PKT_TX_TUNNEL_MASK (0xFULL << 45) > > + >=20 > Above flag bits are added so that i40e driver can tell tunnel type of thi= s packet (udp or gre or ipip), just interested to know how about just do > a simple analysis like below without introducing these flags? >=20 > if outer_ether.proto =3D=3D ipv4 > l4_proto =3D ipv4_hdr->next_proto; > else outer_ether.proto =3D=3D ipv6 > l4_proto =3D ipv6_hdr->next_proto; >=20 > switch (l4_proto) > case ipv4: > case ipv6: > tunnel_type =3D ipip; > break; > case udp: > tunnel_type =3D udp; > break; > case gre: > tunnel_type =3D gre; > break; > default: > error; Right now none of our PMDs reads/writes actual packet data, and I think it is better to keep it that way. It is an upper layer responsibility to specify which offload needs to be enabled and provide necessary information.=20 Konstantin=20 >=20 > Thanks, > Jianfeng >=20 >=20 > > +/** > > * Second VLAN insertion (QinQ) flag. > > */ > > #define PKT_TX_QINQ_PKT (1ULL << 49) /**< TX packet with double = VLAN inserted. */ > > @@ -867,7 +878,10 @@ struct rte_mbuf { > > union { > > uint64_t tx_offload; /**< combined for easy fetch */ > > struct { > > - uint64_t l2_len:7; /**< L2 (MAC) Header Length. */ > > + uint64_t l2_len:7; > > + /**< L2 (MAC) Header Length if it isn't a tunneling pkt. > > + * for tunnel it is outer L4 len+tunnel len+inner L2 len > > + */ > > uint64_t l3_len:9; /**< L3 (IP) Header Length. */ > > uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */ > > uint64_t tso_segsz:16; /**< TCP TSO segment size */