From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id CC9742C0B for ; Mon, 21 Nov 2016 00:21:46 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 20 Nov 2016 15:21:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,523,1473145200"; d="scan'208";a="1071314884" Received: from irsmsx153.ger.corp.intel.com ([163.33.192.75]) by fmsmga001.fm.intel.com with ESMTP; 20 Nov 2016 15:21:44 -0800 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.43]) by IRSMSX153.ger.corp.intel.com ([169.254.9.203]) with mapi id 14.03.0248.002; Sun, 20 Nov 2016 23:21:43 +0000 From: "Ananyev, Konstantin" To: Satha Rao , "Zhang, Helin" CC: "Wu, Jingjing" , "jerin.jacob@caviumnetworks.com" , "jianbo.liu@linaro.org" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2] i40e: Fix eth_i40e_dev_init sequence on ThunderX Thread-Index: AQHSQZrGhw5cVB/e7UKRC3ZACwqCQaDihZRg Date: Sun, 20 Nov 2016 23:21:43 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772583F0DE265@irsmsx105.ger.corp.intel.com> References: <1479473533-9393-1-git-send-email-skoteshwar@caviumnetworks.com> In-Reply-To: <1479473533-9393-1-git-send-email-skoteshwar@caviumnetworks.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] i40e: Fix eth_i40e_dev_init sequence on ThunderX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 20 Nov 2016 23:21:47 -0000 Hi >=20 > i40e_asq_send_command: rd32 & wr32 under ThunderX gives unpredictable > results. To solve this include rte memory barriers >=20 > Signed-off-by: Satha Rao > --- > drivers/net/i40e/base/i40e_osdep.h | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) >=20 > diff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40e/base/i= 40e_osdep.h > index 38e7ba5..ffa3160 100644 > --- a/drivers/net/i40e/base/i40e_osdep.h > +++ b/drivers/net/i40e/base/i40e_osdep.h > @@ -158,7 +158,13 @@ do { = \ > ((volatile uint32_t *)((char *)(a)->hw_addr + (reg))) > static inline uint32_t i40e_read_addr(volatile void *addr) > { > +#if defined(RTE_ARCH_ARM64) > + uint32_t val =3D rte_le_to_cpu_32(I40E_PCI_REG(addr)); > + rte_rmb(); > + return val; If you really need an rmb/wmb with MMIO read/writes on ARM, I think you can avoid #ifdefs here and use rte_smp_rmb/rte_smp_wmb. BTW, I suppose if you need it for i40e, you would need it for other devices= too. Konstantin > +#else > return rte_le_to_cpu_32(I40E_PCI_REG(addr)); > +#endif > } > #define I40E_PCI_REG_WRITE(reg, value) \ > do { I40E_PCI_REG((reg)) =3D rte_cpu_to_le_32(value); } while (0) > @@ -171,8 +177,16 @@ static inline uint32_t i40e_read_addr(volatile void = *addr) > I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), (reg)), (value)) >=20 > #define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg))) > +#if defined(RTE_ARCH_ARM64) > +#define wr32(a, reg, value) \ > + do { \ > + I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value)); \ > + rte_wmb(); \ > + } while (0) > +#else > #define wr32(a, reg, value) \ > I40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value)) > +#endif > #define flush(a) i40e_read_addr(I40E_PCI_REG_ADDR((a), (I40E_GLGEN_STAT)= )) >=20 > #define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0])) > -- > 2.7.4