From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 5A0A23989 for ; Wed, 30 Nov 2016 18:52:05 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP; 30 Nov 2016 09:52:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,574,1473145200"; d="scan'208";a="1075699754" Received: from irsmsx110.ger.corp.intel.com ([163.33.3.25]) by fmsmga001.fm.intel.com with ESMTP; 30 Nov 2016 09:52:03 -0800 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.43]) by irsmsx110.ger.corp.intel.com ([163.33.3.25]) with mapi id 14.03.0248.002; Wed, 30 Nov 2016 17:52:02 +0000 From: "Ananyev, Konstantin" To: Jerin Jacob , "Richardson, Bruce" CC: Satha Rao , "Zhang, Helin" , "Wu, Jingjing" , "jianbo.liu@linaro.org" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2] i40e: Fix eth_i40e_dev_init sequence on ThunderX Thread-Index: AQHSRET1xy4DjrTkUkKXMwHPEfUdnKDlBToAgABUjYCADIBIAA== Date: Wed, 30 Nov 2016 17:52:02 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772583F0E2477@irsmsx105.ger.corp.intel.com> References: <1479473533-9393-1-git-send-email-skoteshwar@caviumnetworks.com> <2601191342CEEE43887BDE71AB9772583F0DE265@irsmsx105.ger.corp.intel.com> <20161121221638.GA17380@svelivela-lt.caveonetworks.com> <20161122134654.GA58712@bricha3-MOBL3.ger.corp.intel.com> <20161122184930.GA11048@svelivela-lt.caveonetworks.com> In-Reply-To: <20161122184930.GA11048@svelivela-lt.caveonetworks.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] i40e: Fix eth_i40e_dev_init sequence on ThunderX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Nov 2016 17:52:05 -0000 Hi Jerin, >=20 > On Tue, Nov 22, 2016 at 01:46:54PM +0000, Bruce Richardson wrote: > > On Tue, Nov 22, 2016 at 03:46:38AM +0530, Jerin Jacob wrote: > > > On Sun, Nov 20, 2016 at 11:21:43PM +0000, Ananyev, Konstantin wrote: > > > > Hi > > > > > > > > > > i40e_asq_send_command: rd32 & wr32 under ThunderX gives unpredict= able > > > > > results. To solve this include rte memory = barriers > > > > > > > > > > Signed-off-by: Satha Rao > > > > > --- > > > > > drivers/net/i40e/base/i40e_osdep.h | 14 ++++++++++++++ > > > > > 1 file changed, 14 insertions(+) > > > > > > > > > > diff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40= e/base/i40e_osdep.h > > > > > index 38e7ba5..ffa3160 100644 > > > > > --- a/drivers/net/i40e/base/i40e_osdep.h > > > > > +++ b/drivers/net/i40e/base/i40e_osdep.h > > > > > @@ -158,7 +158,13 @@ do { = \ > > > > > ((volatile uint32_t *)((char *)(a)->hw_addr + (reg))) > > > > > static inline uint32_t i40e_read_addr(volatile void *addr) > > > > > { > > > > > +#if defined(RTE_ARCH_ARM64) > > > > > + uint32_t val =3D rte_le_to_cpu_32(I40E_PCI_REG(addr)); > > > > > + rte_rmb(); > > > > > + return val; > > > > > > > > If you really need an rmb/wmb with MMIO read/writes on ARM, > > > > I think you can avoid #ifdefs here and use rte_smp_rmb/rte_smp_wmb. > > > > BTW, I suppose if you need it for i40e, you would need it for other= devices too. > > > > > > Yes. ARM would need for all devices(typically, the devices on externa= l PCI bus). > > > I guess rte_smp_rmb may not be the correct abstraction. So we need mo= re of > > > rte_rmb() as we need only non smp variant on IO side. I guess then it= make sense to > > > create new abstraction in eal with following variants so that each ar= ch > > > gets opportunity to make what it makes sense that specific platform > > > > > > rte_readb_relaxed > > > rte_readw_relaxed > > > rte_readl_relaxed > > > rte_readq_relaxed > > > rte_writeb_relaxed > > > rte_writew_relaxed > > > rte_writel_relaxed > > > rte_writeq_relaxed > > > rte_readb > > > rte_readw > > > rte_readl > > > rte_readq > > > rte_writeb > > > rte_writew > > > rte_writel > > > rte_writeq > > > > > > Thoughts ? > > > > > > > That seems like a lot of API calls! > > Perhaps you can clarify - why would the rte_smp_rmb() not work for you? >=20 > Currently arm64 mapped DMB as rte_smp_rmb() for smp case. >=20 > Ideally for io barrier and non smp case, we need to map it as DSB and it = is > bit heavier than DMB Ok, so you need some new macro, like rte_io_(r|w)mb or so, that would expan= d into dmb for ARM, correct? >=20 > The linux kernel arm64 mappings > http://lxr.free-electrons.com/source/arch/arm64/include/asm/io.h#L142 >=20 > DMB vs DSB > https://community.arm.com/thread/3833 >=20 > The relaxed one are without any barriers.(the use case like accessing on > chip peripherals may need only relaxed versions) >=20 > Thoughts on new rte EAL abstraction? Looks like a lot of macros but if you guys think that would help - NP with = that :) Again, in that case we probably can get rid of driver specific pci reg read= /write defines. Konstantin >=20 > > > > /Bruce