From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 8564F7CD2 for ; Mon, 4 Sep 2017 18:49:31 +0200 (CEST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Sep 2017 09:49:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,475,1498546800"; d="scan'208";a="1010834195" Received: from irsmsx154.ger.corp.intel.com ([163.33.192.96]) by orsmga003.jf.intel.com with ESMTP; 04 Sep 2017 09:49:29 -0700 Received: from irsmsx105.ger.corp.intel.com ([169.254.7.75]) by IRSMSX154.ger.corp.intel.com ([169.254.12.83]) with mapi id 14.03.0319.002; Mon, 4 Sep 2017 17:49:28 +0100 From: "Ananyev, Konstantin" To: "Rybalchenko, Kirill" , "dev@dpdk.org" CC: "Rybalchenko, Kirill" , "Chilikin, Andrey" , "Xing, Beilei" , "Wu, Jingjing" Thread-Topic: [dpdk-dev] [PATCH v2 1/4] net/i40e: implement dynamic mapping of sw flow types to hw pctypes Thread-Index: AQHTIzN23wRq8msP/kCpTOEW9hJRzqKk8L4g Date: Mon, 4 Sep 2017 16:49:27 +0000 Message-ID: <2601191342CEEE43887BDE71AB9772584F2463D4@irsmsx105.ger.corp.intel.com> References: <1503569908-104074-1-git-send-email-kirill.rybalchenko@intel.com> <1504278166-32769-1-git-send-email-kirill.rybalchenko@intel.com> <1504278166-32769-2-git-send-email-kirill.rybalchenko@intel.com> In-Reply-To: <1504278166-32769-2-git-send-email-kirill.rybalchenko@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 1/4] net/i40e: implement dynamic mapping of sw flow types to hw pctypes X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Sep 2017 16:49:33 -0000 Hi Kirill, > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Kirill Rybalchenko > Sent: Friday, September 1, 2017 4:03 PM > To: dev@dpdk.org > Cc: Rybalchenko, Kirill ; Chilikin, Andrey = ; Xing, Beilei ; > Wu, Jingjing > Subject: [dpdk-dev] [PATCH v2 1/4] net/i40e: implement dynamic mapping of= sw flow types to hw pctypes >=20 > Implement dynamic mapping of software flow types to hardware pctypes. > This allows to add new flow types and pctypes for DDP without changing > API of the driver. The mapping table is located in private > data area for particular network adapter and can be individually > modified with set of appropriate functions. >=20 > Signed-off-by: Kirill Rybalchenko > --- > v2 > Re-arrange patchset to avoid compillation errors. > Remove usage of statically defined flow types and pctypes. > --- > drivers/net/i40e/i40e_ethdev.c | 347 ++++++++++----------------------= ------ > drivers/net/i40e/i40e_ethdev.h | 16 +- > drivers/net/i40e/i40e_ethdev_vf.c | 36 ++-- > drivers/net/i40e/i40e_fdir.c | 51 +++--- > drivers/net/i40e/i40e_flow.c | 2 +- > drivers/net/i40e/i40e_rxtx.c | 57 +++++++ > drivers/net/i40e/i40e_rxtx.h | 1 + > 7 files changed, 190 insertions(+), 320 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethde= v.c > index 8e0580c..56a96f5 100644 > --- a/drivers/net/i40e/i40e_ethdev.c > +++ b/drivers/net/i40e/i40e_ethdev.c > @@ -1062,6 +1062,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev) > return 0; > } > i40e_set_default_ptype_table(dev); > + i40e_set_default_pctype_table(dev); > pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > intr_handle =3D &pci_dev->intr_handle; >=20 > @@ -2971,7 +2972,7 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct r= te_eth_dev_info *dev_info) > dev_info->hash_key_size =3D (I40E_PFQF_HKEY_MAX_INDEX + 1) * > sizeof(uint32_t); > dev_info->reta_size =3D pf->hash_lut_size; > - dev_info->flow_type_rss_offloads =3D I40E_RSS_OFFLOAD_ALL; > + dev_info->flow_type_rss_offloads =3D pf->adapter->flow_types_msk; >=20 > dev_info->default_rxconf =3D (struct rte_eth_rxconf) { > .rx_thresh =3D { > @@ -6562,104 +6563,36 @@ i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct= ether_addr *addr) >=20 > /* Configure hash enable flags for RSS */ > uint64_t > -i40e_config_hena(uint64_t flags, enum i40e_mac_type type) > +i40e_config_hena(uint64_t flags, struct i40e_adapter *adapter) > { As a nit here and in few other functions below, to keep more conventional o= rder of parameters: i40e_config_hena(struct i40e_adapter *adapter, ....) probably even better: 'const struct i40e_adapter *adapter' whenever possibl= e. > uint64_t hena =3D 0; > + int i; >=20 > if (!flags) > return hena; >=20 > - if (flags & ETH_RSS_FRAG_IPV4) > - hena |=3D 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4; > - if (flags & ETH_RSS_NONFRAG_IPV4_TCP) { > - if (type =3D=3D I40E_MAC_X722) { > - hena |=3D (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | > - (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK); > - } else > - hena |=3D 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP; > - } > - if (flags & ETH_RSS_NONFRAG_IPV4_UDP) { > - if (type =3D=3D I40E_MAC_X722) { > - hena |=3D (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | > - (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | > - (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP); > - } else > - hena |=3D 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP; > - } > - if (flags & ETH_RSS_NONFRAG_IPV4_SCTP) > - hena |=3D 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP; > - if (flags & ETH_RSS_NONFRAG_IPV4_OTHER) > - hena |=3D 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER; > - if (flags & ETH_RSS_FRAG_IPV6) > - hena |=3D 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6; > - if (flags & ETH_RSS_NONFRAG_IPV6_TCP) { > - if (type =3D=3D I40E_MAC_X722) { > - hena |=3D (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | > - (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK); > - } else > - hena |=3D 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP; > + for (i =3D 0; i < I40E_FLOW_TYPE_MAX; i++) { > + if (flags & (1ULL << i)) > + hena |=3D adapter->pcypes_tbl[i]; > } > - if (flags & ETH_RSS_NONFRAG_IPV6_UDP) { > - if (type =3D=3D I40E_MAC_X722) { > - hena |=3D (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | > - (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | > - (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP); > - } else > - hena |=3D 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP; > - } > - if (flags & ETH_RSS_NONFRAG_IPV6_SCTP) > - hena |=3D 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP; > - if (flags & ETH_RSS_NONFRAG_IPV6_OTHER) > - hena |=3D 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER; > - if (flags & ETH_RSS_L2_PAYLOAD) > - hena |=3D 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD; >=20 > return hena; > } >=20 ... >=20 > -enum i40e_filter_pctype > -i40e_flowtype_to_pctype(uint16_t flow_type) > -{ > - static const enum i40e_filter_pctype pctype_table[] =3D { > - [RTE_ETH_FLOW_FRAG_IPV4] =3D I40E_FILTER_PCTYPE_FRAG_IPV4, > - [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =3D > - I40E_FILTER_PCTYPE_NONF_IPV4_UDP, > - [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =3D > - I40E_FILTER_PCTYPE_NONF_IPV4_TCP, > - [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =3D > - I40E_FILTER_PCTYPE_NONF_IPV4_SCTP, > - [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =3D > - I40E_FILTER_PCTYPE_NONF_IPV4_OTHER, > - [RTE_ETH_FLOW_FRAG_IPV6] =3D I40E_FILTER_PCTYPE_FRAG_IPV6, > - [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =3D > - I40E_FILTER_PCTYPE_NONF_IPV6_UDP, > - [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =3D > - I40E_FILTER_PCTYPE_NONF_IPV6_TCP, > - [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =3D > - I40E_FILTER_PCTYPE_NONF_IPV6_SCTP, > - [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =3D > - I40E_FILTER_PCTYPE_NONF_IPV6_OTHER, > - [RTE_ETH_FLOW_L2_PAYLOAD] =3D I40E_FILTER_PCTYPE_L2_PAYLOAD, > - }; > +uint16_t > +i40e_flowtype_to_pctype(uint16_t flow_type, struct i40e_adapter *adapter= ) > +{ > + int i; > + uint64_t pctype_mask; >=20 > - return pctype_table[flow_type]; > + if (flow_type < I40E_FLOW_TYPE_MAX) { > + pctype_mask =3D adapter->pcypes_tbl[flow_type]; > + for (i =3D I40E_PCTYPE_MAX - 1; i >=3D 0; i--) { > + if (pctype_mask & (1ULL << i)) > + return (uint16_t)i; So, each pcypes_tbl[] would always have only one bit set? If so, wouldn't it be more convenient to store only bit index? > + } > + } > + return 0; As I can see, that function would return 0 for both adapter->pcypes_tbl[flow_type] =3D=3D 0 and adapter->pcypes_tbl[flow_type] = =3D=3D 1 Is that intended? Konstantin > } >=20