From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 0C82A1BAF5 for ; Wed, 11 Apr 2018 02:33:18 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Apr 2018 17:33:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,434,1517904000"; d="scan'208";a="190492379" Received: from irsmsx101.ger.corp.intel.com ([163.33.3.153]) by orsmga004.jf.intel.com with ESMTP; 10 Apr 2018 17:33:16 -0700 Received: from irsmsx102.ger.corp.intel.com ([169.254.2.164]) by IRSMSX101.ger.corp.intel.com ([169.254.1.176]) with mapi id 14.03.0319.002; Wed, 11 Apr 2018 01:33:15 +0100 From: "Ananyev, Konstantin" To: Jerin Jacob CC: Olivier Matz , "dev@dpdk.org" , "Richardson, Bruce" Thread-Topic: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring structure Thread-Index: AQHTy12O1Lx02zh0E02SnZc6w2EUYqPvGHGAgAADSwCAAAVLgIAADRUAgAFW7bCAATwagIAAcLmggACzNACAB9v5IA== Date: Wed, 11 Apr 2018 00:33:14 +0000 Message-ID: <2601191342CEEE43887BDE71AB977258AE913464@IRSMSX102.ger.corp.intel.com> References: <20170630142609.6180-1-olivier.matz@6wind.com> <20180403132644.23729-1-olivier.matz@6wind.com> <20180403150722.GB15937@jerin> <20180403152517.hsjghkj5z6mauze7@platinum> <20180403153703.GA19072@jerin> <20180403155601.rqb7fhu6vggzrh7e@platinum> <20180403163254.GB19072@jerin> <2601191342CEEE43887BDE71AB977258A0AB90E3@irsmsx105.ger.corp.intel.com> <20180405080134.GA2674@jerin> <2601191342CEEE43887BDE71AB977258A0AB9930@irsmsx105.ger.corp.intel.com> <20180406012624.GA12155@jerin> In-Reply-To: <20180406012624.GA12155@jerin> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNTVlMmM5NGYtMjhkZC00YzM0LTg0NGEtZDA1Nzk5ODIxOWRmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6Ik9BSU9KNWlrcWE0UGJiNTQzQnhWSHFpQ3d5c1paRSthbHQwZVwvK1djNEh3PSJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.200.100 dlp-reaction: no-action x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Apr 2018 00:33:19 -0000 Hi Jerin, > -----Original Message----- > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > Sent: Friday, April 6, 2018 2:26 AM > To: Ananyev, Konstantin > Cc: Olivier Matz ; dev@dpdk.org; Richardson, Bruc= e > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring = structure >=20 > -----Original Message----- >=20 > Hi Konstantin, >=20 > > > > > -----Original Message----- > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > Sent: Thursday, April 5, 2018 9:02 AM > > > To: Ananyev, Konstantin > > > Cc: Olivier Matz ; dev@dpdk.org; Richardson, = Bruce > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on r= ing structure > > > > > > -----Original Message----- > > > > Date: Wed, 4 Apr 2018 23:38:41 +0000 > > > > From: "Ananyev, Konstantin" > > > > To: Jerin Jacob , Olivier Matz > > > > > > > > CC: "dev@dpdk.org" , "Richardson, Bruce" > > > > > > > > Subject: RE: [dpdk-dev] [PATCH] ring: relax alignment constraint on= ring > > > > structure > > > > > > > > Hi lads, > > > > > > > > > -----Original Message----- > > > > > From: Jerin Jacob [mailto:jerin.jacob@caviumnetworks.com] > > > > > Sent: Tuesday, April 3, 2018 5:43 PM > > > > > To: Olivier Matz > > > > > Cc: dev@dpdk.org; Ananyev, Konstantin ; Richardson, Bruce > > > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint = on ring structure > > > > > > > > > > -----Original Message----- > > > > > > Date: Tue, 3 Apr 2018 17:56:01 +0200 > > > > > > From: Olivier Matz > > > > > > To: Jerin Jacob > > > > > > CC: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardso= n@intel.com > > > > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constrain= t on ring > > > > > > structure > > > > > > User-Agent: NeoMutt/20170113 (1.7.2) > > > > > > > > > > > > On Tue, Apr 03, 2018 at 09:07:04PM +0530, Jerin Jacob wrote: > > > > > > > -----Original Message----- > > > > > > > > Date: Tue, 3 Apr 2018 17:25:17 +0200 > > > > > > > > From: Olivier Matz > > > > > > > > To: Jerin Jacob > > > > > > > > CC: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richa= rdson@intel.com > > > > > > > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment const= raint on ring > > > > > > > > structure > > > > > > > > User-Agent: NeoMutt/20170113 (1.7.2) > > > > > > > > > > > > > > > > On Tue, Apr 03, 2018 at 08:37:23PM +0530, Jerin Jacob wrote= : > > > > > > > > > -----Original Message----- > > > > > > > > > > Date: Tue, 3 Apr 2018 15:26:44 +0200 > > > > > > > > > > From: Olivier Matz > > > > > > > > > > To: dev@dpdk.org > > > > > > > > > > Subject: [dpdk-dev] [PATCH] ring: relax alignment const= raint on ring > > > > > > > > > > structure > > > > > > > > > > X-Mailer: git-send-email 2.11.0 > > > > > > > > > > > > > > > > > > > > The initial objective of > > > > > > > > > > commit d9f0d3a1ffd4 ("ring: remove split cacheline buil= d setting") > > > > > > > > > > was to add an empty cache line betwee, the producer and= consumer > > > > > > > > > > data (on platform with cache line size =3D 64B), preven= ting from > > > > > > > > > > having them on adjacent cache lines. > > > > > > > > > > > > > > > > > > > > Following discussion on the mailing list, it appears th= at this > > > > > > > > > > also imposes an alignment constraint that is not requir= ed. > > > > > > > > > > > > > > > > > > > > This patch removes the extra alignment constraint and a= dds the > > > > > > > > > > empty cache lines using padding fields in the structure= . The > > > > > > > > > > size of rte_ring structure and the offset of the fields= remain > > > > > > > > > > the same on platforms with cache line size =3D 64B: > > > > > > > > > > > > > > > > > > > > rte_ring =3D 384 > > > > > > > > > > rte_ring.name =3D 0 > > > > > > > > > > rte_ring.flags =3D 32 > > > > > > > > > > rte_ring.memzone =3D 40 > > > > > > > > > > rte_ring.size =3D 48 > > > > > > > > > > rte_ring.mask =3D 52 > > > > > > > > > > rte_ring.prod =3D 128 > > > > > > > > > > rte_ring.cons =3D 256 > > > > > > > > > > > > > > > > > > > > But it has an impact on platform where cache line size = is 128B: > > > > > > > > > > > > > > > > > > > > rte_ring =3D 384 -> 768 > > > > > > > > > > rte_ring.name =3D 0 > > > > > > > > > > rte_ring.flags =3D 32 > > > > > > > > > > rte_ring.memzone =3D 40 > > > > > > > > > > rte_ring.size =3D 48 > > > > > > > > > > rte_ring.mask =3D 52 > > > > > > > > > > rte_ring.prod =3D 128 -> 256 > > > > > > > > > > rte_ring.cons =3D 256 -> 512 > > > > > > > > > > > > > > > > > > Are we leaving TWO cacheline to make sure, HW prefetch do= n't load > > > > > > > > > the adjust cacheline(consumer)? > > > > > > > > > > > > > > > > > > If so, Will it have impact on those machine where it is 1= 28B Cache line > > > > > > > > > and the HW prefetcher is not loading the next caching exp= licitly. Right? > > > > > > > > > > > > > > > > The impact on machines that have a 128B cache line is that = an unused > > > > > > > > cache line will be added between the producer and consumer = data. I > > > > > > > > expect that the impact is positive in case there is a hw pr= efetcher, and > > > > > > > > null in case there is no such prefetcher. > > > > > > > > > > > > > > It is not NULL, Right? You are loosing 256B for each ring. > > > > > > > > > > > > Is it really that important? > > > > > > > > > > Pipeline or eventdev SW cases there could more rings in the syste= m. > > > > > I don't see any downside of having config option which is enabled > > > > > default. > > > > > > > > > > In my view, such config options are good, as in embedded usecases= , customers > > > > > can really fine tune the target for the need. In server usecases,= let the default > > > > > of option be enabled, no harm. > > > > > > > > But that would mean we have to maintain two layouts for the rte_rin= g structure. > > > > > > Is there any downside of having two configurable layout? meaning, we = are not > > > transferring rte_ring structure over network etc(ie no interoperabili= ty > > > issue). Does it really matter? May I am missing something here. > > > > My concern about potential compatibility problems we are introducing - > > library build with 'y', while app wit 'n', or visa-versa. >=20 > Got it. >=20 > > I wonder are there really a lot of users who would be interested in suc= h savings? > > Could it happen that this new option would sit here unused and untested= ? >=20 > OK. Fair enough. I have no objections for Olivier patch. >=20 > As a suggestion, may be we can move "char name[RTE_MEMZONE_NAMESIZE]" in = the > struct rte_ring in place of " empty cacheline" to save 32B. No strong opt= ion > though. That sounds like a good idea to me... But I suppose in that case we need to move to that empty cacheline all fiel= ds that precede prod? Otherwise there will be not much advantage in such move. Konstantin