From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id E71BB201 for ; Wed, 31 Aug 2016 12:31:52 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP; 31 Aug 2016 03:31:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,261,1470726000"; d="scan'208";a="1033555507" Received: from irsmsx106.ger.corp.intel.com ([163.33.3.31]) by fmsmga001.fm.intel.com with ESMTP; 31 Aug 2016 03:31:50 -0700 Received: from irsmsx108.ger.corp.intel.com ([169.254.11.71]) by IRSMSX106.ger.corp.intel.com ([169.254.8.240]) with mapi id 14.03.0248.002; Wed, 31 Aug 2016 11:31:50 +0100 From: "O'Driscoll, Tim" To: "dev@dpdk.org" Thread-Topic: 17.02 Roadmap Thread-Index: AdIDcYG/ve+UXjCwSJKpRudRVbpoEg== Date: Wed, 31 Aug 2016 10:31:50 +0000 Message-ID: <26FA93C7ED1EAA44AB77D62FBE1D27BA675B672A@IRSMSX108.ger.corp.intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMzMzZTg3YmUtMzdmYS00MThiLWE0M2ItNjY0YWI5MTM4MjQ4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IkI3TEdFME93UTI5UWZoSFM0NE45R1JNMWVKakkyOXhXczlCUG9QdFBcL2pJPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: [dpdk-dev] 17.02 Roadmap X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 31 Aug 2016 10:31:53 -0000 Below are the features that we're planning to submit for the 17.02 release.= We'll submit a patch to update the roadmap page with this info. Some things will obviously change during planning/development, so we'll pro= vide a more detailed update in late September/early October. After that, th= ings should hopefully be relatively stable. It would be good if others are also willing to share their plans so that we= can build up a complete picture of what's planned for 17.02 and make sure = there's no duplication. Consistent Filter API phase 2: Extend support for the Consistent Filter API= that will be first implemented in 16.11 to IGB and FM10K. Elastic Flow Distributor: The Elastic Flow Distributor (EFD) is a flow-base= d load balancing library which scales linearly for both lookup and insert w= ith the number of threads or cores. EFD lookup uses a "perfect hashing" sc= heme where only the information needed to compute a key's value (and not th= e key itself) is stored in the lookup table, thus reducing CPU cache storag= e requirements. Cryptodev: Additional Software Algorithms:=20 - Optimize the AES-GCM software PMD. - Enhance the Intel(r) AES-NI MB PMD to add support for cipher-only and aut= hentication-only operations. Add support for AES_CBC_MAC, AES_CMAC_128, AES= _GMAC_128. - Add software support for: 3DES_ECB_128/192, AES_ECB_128/192/256, AES_F8, = AES_XTS, ARC4. Run-Time Configuration of Flow Type (PCTYPE) and Packet Type (PTYPE) for I4= 0E: At the moment all flow types and packet types in DPDK are statically de= fined. This makes impossible to add new values without first defining them = statically and then recompiling DPDK. The ability to configure flow types a= nd packet types at run time will be added for I40E. Extended Stats Latency and Bit Rate Statistics: Enhance the Extended NIC St= ats (Xstats) implementation to support the collection and reporting of late= ncy and bit rate measurements. Latency statistics will include min, max and= average latency, and jitter. Bit rate statistics will include peak and ave= rage bit rate aggregated over a user-defined time period. This will be impl= emented for IXGBE and I40E. Hardware QoS for IXGBE and I40E: Implement support for Hardware QoS for IXG= BE and I40E. This involves using DCB so that a PF or VF can receive packets= for each of the Traffic Classes (TCs) based on the User Priority field (in= the VLAN header). Bandwidth on transmit for each TC is programmable.