From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 970CF454EF; Tue, 25 Jun 2024 13:30:37 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2D14C42F02; Tue, 25 Jun 2024 13:21:24 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mails.dpdk.org (Postfix) with ESMTP id ED03842FBF for ; Tue, 25 Jun 2024 13:18:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719314300; x=1750850300; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gysfIFNI4vSQVXvZT2yMz9Z0Gc0L2RjOnECts5bnoj4=; b=XGLkqGdsbLE6wf3YV4Pch9xAtfPzt+9CA2OLkxTbwHJpRw6GlzyyJOXF dAjYDAi2ZuVlAcdaWKm3WgGniWVZEQ8YlMvVpRfM1u/7nl3Om0QFOc3c0 /N1lf2yW4N+vrH3IhQxNnyabaDK5drFrHn51UyfkN6GBok/nNDoWcM7UX 4uF5c++JF21M2/VxR2VEKqDO/DBu5LoB6qHlWnTUJ3MSzIBG0ZOyS0W6M xZzBs9N6wBBBPjHc/VQ9s0FvoXmQomE7v05CaFpQhTYcA5P/CWfEJX8GY +eaUyKowlnXp3sW6KQISPL0J/JLUewOxynho+NDSE+03ApbrIuE7Hp5nE w==; X-CSE-ConnectionGUID: Gs5/IQkFTXOkY5OI0afykg== X-CSE-MsgGUID: VaoJsxnnSx2ivY2Ief4uQw== X-IronPort-AV: E=McAfee;i="6700,10204,11113"; a="16080674" X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="16080674" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jun 2024 04:18:19 -0700 X-CSE-ConnectionGUID: DIZqyxk3Su6hyZy7xxsAnw== X-CSE-MsgGUID: 0qgTGSWsSem6AvCz6urVgg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,263,1712646000"; d="scan'208";a="43719809" Received: from unknown (HELO silpixa00401119.ir.intel.com) ([10.55.129.167]) by orviesa009.jf.intel.com with ESMTP; 25 Jun 2024 04:18:19 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: bruce.richardson@intel.com, ian.stokes@intel.com, Siddaraju DH , Jacob Keller Subject: [PATCH v3 124/129] net/ice/base: make Tx and Rx vernier offset calibration independent Date: Tue, 25 Jun 2024 12:14:09 +0100 Message-ID: <288fc8bef2fb0a4a15ffd5b6073905561afc5caa.1719313664.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The Tx and Rx calibration and timestamp generation blocks are independent. It is not required to wait for both to complete before programming the offsets. Instead, we can program the offset for each independently as soon as they are ready. Modify the ice_phy_cfg_tx_offset_e822 and ice_phy_cfg_rx_offset_e822 functions with the following additions: a) Check the relevant P_REG_*_OR bit first and do nothing if the offset has already been programmed b) Check the P_REG_*_OV_STATUS bit to determine if the offset status is ready, meaning that the hardware vernier calibration steps have completed. Return ICE_ERR_NOT_READY if the offset is not yet read. The driver can now simply call ice_phy_cfg_rx_offset_e822 and ice_phy_cfg_tx_offset_e822 periodically until the offsets have been programmed. In this way, the Tx and Rx blocks will be enabled independently without each waiting on the other block to complete. This can enable faster calibration on some setups which have a low rate of either Tx or Rx traffic. Signed-off-by: Siddaraju DH Signed-off-by: Jacob Keller Signed-off-by: Anatoly Burakov --- drivers/net/ice/base/ice_ptp_hw.c | 67 +++++++++++++++++++++++++++++-- 1 file changed, 64 insertions(+), 3 deletions(-) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index 8f25d79a53..610512a8a9 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -3851,14 +3851,19 @@ ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) * adjust Tx timestamps by. This is calculated by combining some known static * latency along with the Vernier offset computations done by hardware. * - * This function must be called only after the offset registers are valid, - * i.e. after the Vernier calibration wait has passed, to ensure that the PHY - * has measured the offset. + * This function will not return successfully until the Tx offset calculations + * have been completed, which requires waiting until at least one packet has + * been transmitted by the device. It is safe to call this function + * periodically until calibration succeeds, as it will only program the offset + * once. * * To avoid overflow, when calculating the offset based on the known static * latency values, we use measurements in 1/100th of a nanosecond, and divide * the TUs per second up front. This avoids overflow while allowing * calculation of the adjustment using integer arithmetic. + * + * Returns zero on success, ICE_ERR_NOT_READY if the hardware vernier offset + * calibration has not completed, or another error code on failure. */ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) { @@ -3866,6 +3871,28 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) enum ice_ptp_fec_mode fec_mode; u64 total_offset, val; int err; + u32 reg; + + /* Nothing to do if we've already programmed the offset */ + err = ice_read_phy_reg_e822(hw, port, P_REG_TX_OR, ®); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n", + port, err); + return err; + } + + if (reg) + return 0; + + err = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, ®); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n", + port, err); + return err; + } + + if (!(reg & P_REG_TX_OV_STATUS_OV_M)) + return ICE_ERR_NOT_READY; err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); if (err) @@ -3918,6 +3945,8 @@ int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) if (err) return err; + ice_info(hw, "Port=%d Tx vernier offset calibration complete\n", port); + return 0; } @@ -4120,6 +4149,11 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) * measurements taken in hardware with some data about known fixed delay as * well as adjusting for multi-lane alignment delay. * + * This function will not return successfully until the Rx offset calculations + * have been completed, which requires waiting until at least one packet has + * been received by the device. It is safe to call this function periodically + * until calibration succeeds, as it will only program the offset once. + * * This function must be called only after the offset registers are valid, * i.e. after the Vernier calibration wait has passed, to ensure that the PHY * has measured the offset. @@ -4128,6 +4162,9 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) * latency values, we use measurements in 1/100th of a nanosecond, and divide * the TUs per second up front. This avoids overflow while allowing * calculation of the adjustment using integer arithmetic. + * + * Returns zero on success, ICE_ERR_NOT_READY if the hardware vernier offset + * calibration has not completed, or another error code on failure. */ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) { @@ -4135,6 +4172,28 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) enum ice_ptp_fec_mode fec_mode; u64 total_offset, pmd, val; int err; + u32 reg; + + /* Nothing to do if we've already programmed the offset */ + err = ice_read_phy_reg_e822(hw, port, P_REG_RX_OR, ®); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n", + port, err); + return err; + } + + if (reg) + return 0; + + err = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, ®); + if (err) { + ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n", + port, err); + return err; + } + + if (!(reg & P_REG_RX_OV_STATUS_OV_M)) + return ICE_ERR_NOT_READY; err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); if (err) @@ -4195,6 +4254,8 @@ int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) if (err) return err; + ice_info(hw, "Port=%d Rx vernier offset calibration complete\n", port); + return 0; } -- 2.43.0