From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from m13-4.163.com (m13-4.163.com [220.181.13.4]) by dpdk.org (Postfix) with ESMTP id 39398C458 for ; Fri, 23 Oct 2015 09:38:42 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=Date:From:Subject:MIME-Version:Message-ID; bh=zpzwp YG3YmjV9m51Ss8WcOaehg0ES1ovde5avBoN3e8=; b=hYzP1ejgo0dR69lm9wB+y mTQdxPkEcWS8EnBipKIH3jVL+vHxTtQLVRG5LCsEToFGP3Ky0dojnJQiw9CIc7Cl 6HU5rqEFArApJLUNzFEPskdKqtUFOADSAlS1dSHtgSpr+GV4Jt1HMfyBulteA3Uz MwOa3pVyh9sHsa50IRKbVA= Received: from mablexidana$163.com ( [182.92.253.20] ) by ajax-webmail-wmsvr4 (Coremail) ; Fri, 23 Oct 2015 15:38:38 +0800 (CST) X-Originating-IP: [182.92.253.20] Date: Fri, 23 Oct 2015 15:38:38 +0800 (CST) From: mablexidana To: dev@dpdk.org X-Priority: 3 X-Mailer: Coremail Webmail Server Version SP_ntes V3.5 build 20150911(74783.7961) Copyright (c) 2002-2015 www.mailtech.cn 163com X-CM-CTRLDATA: N8i4A2Zvb3Rlcl9odG09MTc4MzY6NTY= MIME-Version: 1.0 Message-ID: <29f00a47.e2cb.15093a29920.Coremail.mablexidana@163.com> X-CM-TRANSID: BMGowABHTQH_4ylWu3aPAA--.13246W X-CM-SenderInfo: xpdezvp0lgt0rd6rljoofrz/xtbBDh+csFQG1qRYhQAAsA X-Coremail-Antispam: 1U5529EdanIXcx71UUUUU7vcSsGvfC2KfnxnUU== Content-Type: text/plain; charset=GBK Content-Transfer-Encoding: base64 X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: [dpdk-dev] [PATCH 1/2] lpm: add strict if control etc. on version 1.2.3 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Oct 2015 07:38:45 -0000 aGk6ClRoaXMgaXMgdGVzdCBvbiBkcGRrIHZlcnNpb24gMS4yLjMuICAgICAgICAgCkZpeGVzOiAy YTIxNzQ4MDFmYTQgKCIgICAgZml4IGxwbSBidWdzICAgICBhZGQgc3RyaWN0IGlmIGNvbnRyb2ws ZG8gbm90IGxldCB0YmwyNCBwcm9jZXNzIHJ1biBpbnRvIHRibDggcHJvY2VzcyAgICAgYWRkIHZh bGlkX2dyb3VwID0gdmFsaWQsIGluY2FzZSAsdGhlIHZhbGlkX2dyb3VwIGlzIHdyaXRlIHRvIGlu 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AAE87C456 for ; Fri, 23 Oct 2015 09:45:07 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=Date:From:Subject:MIME-Version:Message-ID; bh=eWiGS VP6oGH0rGYDoW5yinIE9SrvQS8mhVUfOQYWMLU=; b=H2E0NYcPNUi3DIqrGF1FE iWE8YJU9wk0CE0om2dIHzs/AzPq5R1HCbjsaJmpBG6sNIp5/bgzOAlgJ7Le+/4YJ tVIeOcVX1Z/M7aQWsz+0MuyZmTWnyCPpW03GYIB+r4l9T/4x9MuNiNTBy7nJUDZf r2K9O+910LOUSGd9TztpQg= Received: from mablexidana$163.com ( [182.92.253.20] ) by ajax-webmail-wmsvr4 (Coremail) ; Fri, 23 Oct 2015 15:45:04 +0800 (CST) X-Originating-IP: [182.92.253.20] Date: Fri, 23 Oct 2015 15:45:04 +0800 (CST) From: mablexidana To: dev@dpdk.org X-Priority: 3 X-Mailer: Coremail Webmail Server Version SP_ntes V3.5 build 20150911(74783.7961) Copyright (c) 2002-2015 www.mailtech.cn 163com In-Reply-To: <29f00a47.e2cb.15093a29920.Coremail.mablexidana@163.com> References: <29f00a47.e2cb.15093a29920.Coremail.mablexidana@163.com> X-CM-CTRLDATA: RTaiXmZvb3Rlcl9odG09Mjc1Mjc6NTY= MIME-Version: 1.0 Message-ID: <7b920919.e5aa.15093a87c7e.Coremail.mablexidana@163.com> X-CM-TRANSID: BMGowADX3gKA5SlWGXuPAA--.25820W X-CM-SenderInfo: xpdezvp0lgt0rd6rljoofrz/1tbiMRacsFUL3JsCOwACsp X-Coremail-Antispam: 1U5529EdanIXcx71UUUUU7vcSsGvfC2KfnxnUU== Content-Type: text/plain; charset=GBK Content-Transfer-Encoding: base64 X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH 2/2] add 3 lpm test cases X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Oct 2015 07:45:09 -0000 aGk6CgoKYnJhbmNoOjEuMi4zCkZpeGVzOiBmZWFiM2U4NDQzMmIgKCJhZGQgMyBscG0gdGVzdCBj YXNlcyIpCnRlc3QgcHJvY2VkdXJlOgogMSksYWRkLT5sb29rdXAKIDIpLGFkZC0+ZGVsZXRlLT5s b29rdXAKIDMpLGFkZC0+ZGVsZXRlLT5hZGQtPmxvb2t1cAoKClJlZ2FyZHMKCgp5dWVyeGluCgoK LS0tCiBhcHAvdGVzdC90ZXN0X2xwbS5jIHwgNDU2ICsrKysrKysrKysrKysrKysrKysrKysrKysr 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ICAgICAgbHBtX3JvdXRlX3Nob3cobHBtKTsKKyAgICAgICAgcHJpbnRmKCJ0ZXN0X3JhbmRvbV9s cG1fY2FzZV8zLCBmYWlsZWQuLi5cbiIpOworICAgICAgICByZXQgPSAtMTsKKyAgICAgICAgZ290 byBPVVQ7CisgICAgfQorICAgIHByaW50ZigidGVzdF9yYW5kb21fbHBtX2Nhc2VfMywgb2suLi5c biIpOworCitPVVQ6CisgICAgcnRlX2xwbV9mcmVlKGxwbSkgOworICAgIHJldHVybiByZXQ7Cit9 CisKKwogLyoKICAqIFNlcXVlbmNlIG9mIG9wZXJhdGlvbnMgZm9yIGZpbmQgZXhpc3RpbmcgZmJr IGhhc2ggdGFibGUKICAqCi0tCjEuOC41LjIgKEFwcGxlIEdpdC00OCk= >From mablexidana@163.com Fri Oct 23 09:48:02 2015 Return-Path: Received: from m13-4.163.com (m13-4.163.com [220.181.13.4]) by dpdk.org (Postfix) with ESMTP id EE768C474 for ; Fri, 23 Oct 2015 09:47:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=Date:From:Subject:MIME-Version:Message-ID; bh=u/19R jKX1l0stm1KBLrY+klUx++KPDvoZNilPl8/d/M=; b=AAqVmwDk5KlJBrbMaxUCm KZsWit6ehCWeUO3ydNcl4fDdKabNdY6hG7ng6TuTaN1voF+aycUmTidv9m+Vkd8h iF19ACJRgO/Ku6O+WjXaQG4PLtEpsflNBwT7OiYuKiQhrZz46mnl+PZSOsQ2ivIY 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Content-Transfer-Encoding: base64 X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH] fix lpm bugs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Oct 2015 07:48:02 -0000 aGk6ClRoaXMgaXMgdGVzdCBvbiBkcGRrIHZlcnNpb24gMi4xCgoKUmVnYXJkcyAKCgoKCnl1ZXJ4 aW4KCgp0IDIwMTUtMTAtMjIgMTA6MTU6MTYsICJtYWJsZXhpZGFuYSIgPG1hYmxleGlkYW5hQDE2 My5jb20+IHdyb3RlOgpoaToKICAgIEZpeGVzOiAyNWU0ZjUxNWZlNjMgKCJmaXggbHBtIGJ1Z3Mi KQoKCgoKICAgdGhlIHJhbmRvbSB0ZXN0IG9mIGxwbSAsIG11bHRpcGxlIGRlbGV0ZSBhbmQgYWRk IGlwIGFkZHJlc3MsIGl0IGRvIG5vdCByZWNvdmVyIHRoZSBsYXN0IHJpZ2h0IGlwIGFkZHJlc3Mu CiAgZWcxOiAKICAgYWRkIGEgbG90IG9mIHJvdXRlczoKIHJ1bGUgaWQgOiAxLCBpcCA6IDE2LjMy LjAuMC8xOSwgbmV4dF9ob3AgOiA2MiwgCnJ1bGUgaWQgOiAyLCBpcCA6IDE2LjMyLjI4LjAvMjIs IG5leHRfaG9wIDogOTcsCnJ1bGUgaWQgOiAgMjgsIGlwOjE2LjMyLjAuMC8yMSwgbmV4dF9ob3Ag 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NzgxLDcgKzc4Miw3IEBAIGRlbGV0ZV9kZXB0aF9zbWFsbChzdHJ1Y3QgcnRlX2xwbSAqbHBtLCB1 aW50MzJfdCBpcF9tYXNrZWQsCj4+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICBscG0tPnRibDI0W2ldLmRlcHRoIDw9IGRlcHRoICkgewo+PiAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgIGxwbS0+dGJsMjRbaV0gPSBuZXdfdGJsMjRfZW50cnk7Cj4+ICAgICAg ICAgICAgICAgICAgICAgICAgIH0KPj4gLSAgICAgICAgICAgICAgICAgICAgICAgZWxzZSB7Cj4+ ICsgICAgICAgICAgICAgICAgICAgICAgIGVsc2UgIGlmIChscG0tPnRibDI0W2ldLmV4dF9lbnRy eSA9PSAxKSB7Cj4+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgLyoKPj4gICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgKiBJZiBUQkwyNCBlbnRyeSBpcyBleHRlbmRlZCwg dGhlbiB0aGVyZSBoYXMKPj4gICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgKiB0byBi ZSBhIHJ1bGUgd2l0aCBkZXB0aCA+PSAyNSBpbiB0aGUKPj4gLS0KPj4gMS44LjUuMiAoQXBwbGUg R2l0LTQ4KQoKCgoKCiA= >From shaopeng.he@intel.com Fri Oct 23 09:54:03 2015 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 27CF2C48A for ; Fri, 23 Oct 2015 09:54:02 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP; 23 Oct 2015 00:54:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,185,1444719600"; d="scan'208";a="586520031" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by FMSMGA003.fm.intel.com with ESMTP; 23 Oct 2015 00:53:54 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 23 Oct 2015 00:53:53 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.253]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.47]) with mapi id 14.03.0248.002; Fri, 23 Oct 2015 15:53:52 +0800 From: "He, Shaopeng" To: "Chen, Jing D" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 2/5] fm10k: enable Rx queue interrupts for PF and VF Thread-Index: AQHRDJY3qZvulrKMuUecPlJLVrX7/Z54lzNA Date: Fri, 23 Oct 2015 07:53:51 +0000 Message-ID: References: <1443159425-32502-1-git-send-email-shaopeng.he@intel.com> <1443159425-32502-3-git-send-email-shaopeng.he@intel.com> <4341B239C0EFF9468EE453F9E9F4604D02AE1B12@shsmsx102.ccr.corp.intel.com> In-Reply-To: <4341B239C0EFF9468EE453F9E9F4604D02AE1B12@shsmsx102.ccr.corp.intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH 2/5] fm10k: enable Rx queue interrupts for PF and VF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Oct 2015 07:54:03 -0000 Hi, Mark Thanks for the comments, please find my reply inline. Thanks, --Shaopeng > -----Original Message----- > From: Chen, Jing D > Sent: Thursday, October 22, 2015 2:52 PM > To: He, Shaopeng; dev@dpdk.org > Subject: RE: [dpdk-dev] [PATCH 2/5] fm10k: enable Rx queue interrupts for > PF and VF >=20 > Hi, >=20 > Best Regards, > Mark >=20 >=20 > > -----Original Message----- > > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shaopeng He > > Sent: Friday, September 25, 2015 1:37 PM > > To: dev@dpdk.org > > Subject: [dpdk-dev] [PATCH 2/5] fm10k: enable Rx queue interrupts for > > PF and VF > > > > The patch does below things for fm10k PF and VF: > > - Setup NIC to generate MSI-X interrupts > > - Set the RXINT register to map interrupt causes to vectors > > - Implement interrupt enable/disable functions >=20 > The description is too simple, can you help to extend? > Besides that, there are complicated changes in this patch. > Can you help you split it to several smaller ones for better understandin= g? Sure, I will send v2 to split into smaller ones. >=20 > > > > Signed-off-by: Shaopeng He > > --- > > drivers/net/fm10k/fm10k_ethdev.c | 147 > > +++++++++++++++++++++++++++++++++++++-- > > 1 file changed, 140 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/net/fm10k/fm10k_ethdev.c > > b/drivers/net/fm10k/fm10k_ethdev.c > > index a82cd59..6648934 100644 > > --- a/drivers/net/fm10k/fm10k_ethdev.c > > +++ b/drivers/net/fm10k/fm10k_ethdev.c > > > > static int > > +fm10k_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t > > queue_id) > > +{ > > + struct fm10k_hw *hw =3D FM10K_DEV_PRIVATE_TO_HW(dev->data- > > >dev_private); > > + > > + /* Enable ITR */ > > + if (hw->mac.type =3D=3D fm10k_mac_pf) > > + FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)), > > + FM10K_ITR_AUTOMASK | > > FM10K_ITR_MASK_CLEAR); > > + else > > + FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)), > > + FM10K_ITR_AUTOMASK | > > FM10K_ITR_MASK_CLEAR); > > + rte_intr_enable(&dev->pci_dev->intr_handle); > > + return 0; > > +} > > + > > +static int > > +fm10k_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t > > queue_id) > > +{ > > + struct fm10k_hw *hw =3D FM10K_DEV_PRIVATE_TO_HW(dev->data- > > >dev_private); > > + > > + /* Disable ITR */ > > + if (hw->mac.type =3D=3D fm10k_mac_pf) > > + FM10K_WRITE_REG(hw, FM10K_ITR(Q2V(dev, queue_id)), > > + FM10K_ITR_MASK_SET); > > + else > > + FM10K_WRITE_REG(hw, FM10K_VFITR(Q2V(dev, queue_id)), > > + FM10K_ITR_MASK_SET); >=20 > In previous enable function, you'll use rte_intr_enable() to enable inter= rupt, > but You needn't disable it in this function? rte_intr_enable() is needed in fm10k_dev_rx_queue_intr_enable to re-enable the interrupt in port level. To disable individual queue interrupt, current= ly only=20 need to disable the hardware side by register setting. >=20 > > + return 0; > > +} > > + > > +static int > > +fm10k_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) { > > + struct fm10k_hw *hw =3D FM10K_DEV_PRIVATE_TO_HW(dev->data- > > >dev_private); > > + struct rte_intr_handle *intr_handle =3D &dev->pci_dev->intr_handle; > > + uint32_t intr_vector, vec; > > + uint16_t queue_id; > > + int result =3D 0; > > + > > + /* fm10k needs interrupt for mailbox > > + * so igb_uio is not supported for rx interrupt > > + */ >=20 > I guess you'll support both igb_uio and VFIO, RX interrupt mode only enab= led > in case VFIO is used. > I suggest you add more comments here for better understanding. You are right, current igb_uio only has one interrupt vector, and mailbox needs that, so igb_uio cannot support RX interrupt mode. I will add more comments here in next version. >=20 > > + if (!rte_intr_cap_multiple(intr_handle) || > > + dev->data->dev_conf.intr_conf.rxq =3D=3D 0) > > + return result; > > + > > + intr_vector =3D dev->data->nb_rx_queues; > > + > > + /* disable interrupt first */ > > + rte_intr_disable(&dev->pci_dev->intr_handle); > > + if (hw->mac.type =3D=3D fm10k_mac_pf) > > + fm10k_dev_disable_intr_pf(dev); > > + else > > + fm10k_dev_disable_intr_vf(dev); > > + > > + if (rte_intr_efd_enable(intr_handle, intr_vector)) { > > + PMD_INIT_LOG(ERR, "Failed to init event fd"); > > + result =3D -EIO; > > + } > > + > > + if (rte_intr_dp_is_en(intr_handle) && !result) { > > + intr_handle->intr_vec =3D rte_zmalloc("intr_vec", > > + dev->data->nb_rx_queues * sizeof(int), 0); > > + if (intr_handle->intr_vec) { > > + for (queue_id =3D 0, vec =3D RX_VEC_START; > > + queue_id < dev->data- > > >nb_rx_queues; > > + queue_id++) { > > + intr_handle->intr_vec[queue_id] =3D vec; > > + if (vec < intr_handle->nb_efd - 1 + > > RX_VEC_START) > > + vec++; >=20 > No "else" to handle exceptional case? For the "else" case, when all available efd (event fd) are used, currently = we just reuse the last efd, keep the same value for "vec", so no "else" is nee= ded. >=20 > > + } > > + } else { > > + PMD_INIT_LOG(ERR, "Failed to allocate %d > > rx_queues" > > + " intr_vec", dev->data->nb_rx_queues); > > + result =3D -ENOMEM; > > + } > > + } > > + > > + if (hw->mac.type =3D=3D fm10k_mac_pf) > > + fm10k_dev_enable_intr_pf(dev); > > + else > > + fm10k_dev_enable_intr_vf(dev); > > + rte_intr_enable(&dev->pci_dev->intr_handle); > > + hw->mac.ops.update_int_moderator(hw); > > + return result; > > +} > > + > > +static int > > fm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr) { > > struct fm10k_fault fault; > > @@ -2050,6 +2181,8 @@ static const struct eth_dev_ops > > fm10k_eth_dev_ops =3D { > > .tx_queue_setup =3D fm10k_tx_queue_setup, > > .tx_queue_release =3D fm10k_tx_queue_release, > > .rx_descriptor_done =3D fm10k_dev_rx_descriptor_done, > > + .rx_queue_intr_enable =3D fm10k_dev_rx_queue_intr_enable, > > + .rx_queue_intr_disable =3D fm10k_dev_rx_queue_intr_disable, > > .reta_update =3D fm10k_reta_update, > > .reta_query =3D fm10k_reta_query, > > .rss_hash_update =3D fm10k_rss_hash_update, > > @@ -2060,7 +2193,7 @@ static int > > eth_fm10k_dev_init(struct rte_eth_dev *dev) { > > struct fm10k_hw *hw =3D FM10K_DEV_PRIVATE_TO_HW(dev->data- > > >dev_private); > > - int diag; > > + int diag, i; > > struct fm10k_macvlan_filter_info *macvlan; > > > > PMD_INIT_FUNC_TRACE(); > > @@ -2177,7 +2310,7 @@ eth_fm10k_dev_init(struct rte_eth_dev *dev) > > fm10k_dev_enable_intr_vf(dev); > > } > > > > - /* Enable uio intr after callback registered */ > > + /* Enable intr after callback registered */ > > rte_intr_enable(&(dev->pci_dev->intr_handle)); > > > > hw->mac.ops.update_int_moderator(hw); > > @@ -2185,7 +2318,6 @@ eth_fm10k_dev_init(struct rte_eth_dev *dev) > > /* Make sure Switch Manager is ready before going forward. */ > > if (hw->mac.type =3D=3D fm10k_mac_pf) { > > int switch_ready =3D 0; > > - int i; > > > > for (i =3D 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) { > > fm10k_mbx_lock(hw); > > @@ -2291,7 +2423,8 @@ static struct eth_driver rte_pmd_fm10k =3D { > > .pci_drv =3D { > > .name =3D "rte_pmd_fm10k", > > .id_table =3D pci_id_fm10k_map, > > - .drv_flags =3D RTE_PCI_DRV_NEED_MAPPING | > > RTE_PCI_DRV_DETACHABLE, > > + .drv_flags =3D RTE_PCI_DRV_NEED_MAPPING | > > RTE_PCI_DRV_INTR_LSC | > > + RTE_PCI_DRV_DETACHABLE, > > }, > > .eth_dev_init =3D eth_fm10k_dev_init, > > .eth_dev_uninit =3D eth_fm10k_dev_uninit, > > -- > > 1.9.3