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From: "Guo, Jia" <jia.guo@intel.com>
To: "Han, YingyaX" <yingyax.han@intel.com>,
	"Jiang, JunyuX" <junyux.jiang@intel.com>,
	"dev@dpdk.org" <dev@dpdk.org>
Cc: "Xing, Beilei" <beilei.xing@intel.com>,
	"Jiang, JunyuX" <junyux.jiang@intel.com>,
	"stable@dpdk.org" <stable@dpdk.org>
Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH] net/i40e: fix incorrect byte counters
Date: Thu, 10 Sep 2020 05:58:32 +0000
Message-ID: <2c0b8b4ff5ce41d6868c5889e5a0c379@intel.com> (raw)
In-Reply-To: <BN7PR11MB281872AA23873A6D58D332C7FF270@BN7PR11MB2818.namprd11.prod.outlook.com>

Hi, junyu

> -----Original Message-----
> From: Han, YingyaX <yingyax.han@intel.com>
> Sent: Thursday, September 10, 2020 10:18 AM
> To: Jiang, JunyuX <junyux.jiang@intel.com>; dev@dpdk.org
> Cc: Guo, Jia <jia.guo@intel.com>; Xing, Beilei <beilei.xing@intel.com>; Jiang,
> JunyuX <junyux.jiang@intel.com>; stable@dpdk.org
> Subject: RE: [dpdk-stable] [PATCH] net/i40e: fix incorrect byte counters
> 
> Tested-by: Yingya Han <yingyax.han@intel.com>
> 
> -----Original Message-----
> From: stable <stable-bounces@dpdk.org> On Behalf Of Junyu Jiang
> Sent: Thursday, September 10, 2020 9:54 AM
> To: dev@dpdk.org
> Cc: Guo, Jia <jia.guo@intel.com>; Xing, Beilei <beilei.xing@intel.com>; Jiang,
> JunyuX <junyux.jiang@intel.com>; stable@dpdk.org
> Subject: [dpdk-stable] [PATCH] net/i40e: fix incorrect byte counters
> 
> This patch fixed the issue that rx/tx bytes overflowed on 48 bit limitation by
> enlarging the limitation.
> 
> Fixes: 4861cde46116 ("i40e: new poll mode driver")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Junyu Jiang <junyux.jiang@intel.com>
> ---
>  drivers/net/i40e/i40e_ethdev.c | 47
> ++++++++++++++++++++++++++++++++++
>  drivers/net/i40e/i40e_ethdev.h |  9 +++++++
>  2 files changed, 56 insertions(+)
> 
> diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
> index 11c02b188..e3d4b7f4f 100644
> --- a/drivers/net/i40e/i40e_ethdev.c
> +++ b/drivers/net/i40e/i40e_ethdev.c
> @@ -3070,6 +3070,13 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi)
> i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
>      vsi->offset_loaded, &oes->rx_broadcast,
>      &nes->rx_broadcast);
> +/* enlarge the limitation when rx_bytes overflowed */ if
> +(vsi->offset_loaded) { if (I40E_RXTX_BYTES_LOW(vsi->old_rx_bytes) >
> +nes->rx_bytes)
> +nes->rx_bytes += (uint64_t)1 << I40E_48_BIT_WIDTH; rx_bytes +=
> +nes->I40E_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
> +}
> +vsi->old_rx_bytes = nes->rx_bytes;
>  /* exclude CRC bytes */
>  nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
>  nes->rx_broadcast) * RTE_ETHER_CRC_LEN; @@ -3096,6 +3103,13 @@
> i40e_update_vsi_stats(struct i40e_vsi *vsi)
>  /* GLV_TDPC not supported */
>  i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
>      &oes->tx_errors, &nes->tx_errors);
> +/* enlarge the limitation when tx_bytes overflowed */ if
> +(vsi->offset_loaded) { if (I40E_RXTX_BYTES_LOW(vsi->old_tx_bytes) >
> +nes->tx_bytes)
> +nes->tx_bytes += (uint64_t)1 << I40E_48_BIT_WIDTH; tx_bytes +=
> +nes->I40E_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
> +}
> +vsi->old_rx_bytes = nes->rx_bytes;

It should be tx, right?

>  vsi->offset_loaded = true;
> 
>  PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start
> *******************", @@ -3168,6 +3182,24 @@
> i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
>      pf->offset_loaded,
>      &pf->internal_stats_offset.tx_broadcast,
>      &pf->internal_stats.tx_broadcast);
> +/* enlarge the limitation when internal rx/tx bytes overflowed */ if
> +(pf->offset_loaded) { if
> +(I40E_RXTX_BYTES_LOW(pf->internal_old_rx_bytes) >
> +    pf->internal_stats.rx_bytes)
> +pf->internal_stats.rx_bytes +=
> +(uint64_t)1 << I40E_48_BIT_WIDTH;
> +pf->internal_stats.rx_bytes +=
> +I40E_RXTX_BYTES_HIGH(pf->internal_old_rx_bytes);
> +
> +if (I40E_RXTX_BYTES_LOW(pf->internal_old_tx_bytes) >
> +    pf->internal_stats.tx_bytes)
> +pf->internal_stats.tx_bytes +=
> +(uint64_t)1 << I40E_48_BIT_WIDTH;
> +pf->internal_stats.tx_bytes +=
> +I40E_RXTX_BYTES_HIGH(pf->internal_old_tx_bytes);
> +}
> +pf->internal_old_rx_bytes = pf->internal_stats.rx_bytes;
> +pf->internal_old_tx_bytes = pf->internal_stats.tx_bytes;
> 
>  /* exclude CRC size */
>  pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast + @@ -3191,6
> +3223,14 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw
> *hw)
>      I40E_GLPRT_BPRCL(hw->port),
>      pf->offset_loaded, &os->eth.rx_broadcast,
>      &ns->eth.rx_broadcast);
> +/* enlarge the limitation when rx_bytes overflowed */ if
> +(pf->offset_loaded) { if (I40E_RXTX_BYTES_LOW(pf->old_rx_bytes) >
> +ns->eth.rx_bytes)
> +ns->eth.rx_bytes += (uint64_t)1 << I40E_48_BIT_WIDTH; eth.rx_bytes +=
> +ns->I40E_RXTX_BYTES_HIGH(pf->old_rx_bytes);
> +}
> +pf->old_rx_bytes = ns->eth.rx_bytes;
> +
>  /* Workaround: CRC size should not be included in byte statistics,
>   * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
>   * packet.
> @@ -3249,6 +3289,13 @@ i40e_read_stats_registers(struct i40e_pf *pf,
> struct i40e_hw *hw)
>      I40E_GLPRT_BPTCL(hw->port),
>      pf->offset_loaded, &os->eth.tx_broadcast,
>      &ns->eth.tx_broadcast);
> +/* enlarge the limitation when tx_bytes overflowed */ if
> +(pf->offset_loaded) { if (I40E_RXTX_BYTES_LOW(pf->old_tx_bytes) >
> +ns->eth.tx_bytes)
> +ns->eth.tx_bytes += (uint64_t)1 << I40E_48_BIT_WIDTH; eth.tx_bytes +=
> +ns->I40E_RXTX_BYTES_HIGH(pf->old_tx_bytes);
> +}
> +pf->old_tx_bytes = ns->eth.tx_bytes;
>  ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
>  ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
> 
> diff --git a/drivers/net/i40e/i40e_ethdev.h
> b/drivers/net/i40e/i40e_ethdev.h index 19f821829..5d17be1f0 100644
> --- a/drivers/net/i40e/i40e_ethdev.h
> +++ b/drivers/net/i40e/i40e_ethdev.h
> @@ -282,6 +282,9 @@ struct rte_flow {
>  #define I40E_ETH_OVERHEAD \
>  (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
> 
> +#define I40E_RXTX_BYTES_HIGH(bytes) ((bytes) & ~I40E_48_BIT_MASK)
> +#define I40E_RXTX_BYTES_LOW(bytes) ((bytes) & I40E_48_BIT_MASK)
> +
>  struct i40e_adapter;
>  struct rte_pci_driver;
> 
> @@ -399,6 +402,8 @@ struct i40e_vsi {
>  uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */  uint8_t
> vlan_filter_on; /* The VLAN filter enabled */  struct i40e_bw_info bw_info;
> /* VSI bandwidth information */
> +uint64_t old_rx_bytes;
> +uint64_t old_tx_bytes;
>  };
> 
>  struct pool_entry {
> @@ -1156,6 +1161,10 @@ struct i40e_pf {
>  uint16_t switch_domain_id;
> 
>  struct i40e_vf_msg_cfg vf_msg_cfg;
> +uint64_t old_rx_bytes;
> +uint64_t old_tx_bytes;
> +uint64_t internal_old_rx_bytes;
> +uint64_t internal_old_tx_bytes;
>  };
> 
>  enum pending_msg {
> --
> 2.17.1
> 


  reply	other threads:[~2020-09-10  5:58 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-10  1:54 [dpdk-dev] " Junyu Jiang
2020-09-10  2:18 ` [dpdk-dev] [dpdk-stable] " Han, YingyaX
2020-09-10  5:58   ` Guo, Jia [this message]
2020-09-10  6:45     ` Jiang, JunyuX
2020-09-16  1:51 ` [dpdk-dev] [PATCH v2] " Junyu Jiang
2020-09-16  2:39   ` [dpdk-dev] [dpdk-stable] " Han, YingyaX
2020-09-16  5:21   ` [dpdk-dev] " Guo, Jia
2020-09-16  5:50     ` Zhang, Qi Z
2020-09-16 12:30   ` [dpdk-dev] [dpdk-stable] " Ferruh Yigit
2020-09-18  3:44     ` Jiang, JunyuX
2020-09-18  9:23       ` Igor Ryzhov
2020-09-18 13:42         ` Ferruh Yigit
2020-09-21  1:55           ` Jiang, JunyuX
2020-09-18 13:37       ` Ferruh Yigit
2020-09-21  9:59 ` [dpdk-dev] [PATCH v3] " Junyu Jiang
2020-09-21 11:41   ` Ferruh Yigit
2020-09-22  7:37 ` [dpdk-dev] [PATCH v4] " Junyu Jiang
2020-09-22  9:06   ` Ferruh Yigit
2020-09-22  9:19 ` [dpdk-dev] [PATCH v5] " Junyu Jiang
2020-09-22 12:59   ` Zhang, Qi Z

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