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Fri, 12 Oct 2018 11:09:38 +0000 From: Igor Russkikh To: "dev@dpdk.org" CC: Pavel Belous , Igor Russkikh , "ferruh.yigit@intel.com" Thread-Topic: [PATCH v6 15/22] net/atlantic: implement RSS and RETA manipulation API Thread-Index: AQHUYhwR90kEsOYWZ0S7PCAGU/CPGA== Date: Fri, 12 Oct 2018 11:09:38 +0000 Message-ID: <2f0052e401a50913d2706875895d078010c4bece.1539338074.git.igor.russkikh@aquantia.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM5PR0701CA0008.eurprd07.prod.outlook.com (2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com (2a01:111:e400:522a::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Igor.Russkikh@aquantia.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [95.79.108.179] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY1PR0701MB1627; 6:P6JIu8ysIR+pe3h7ZYCvXeO6ZNBsMwt0DA2r7csQIisGQe9okrXfXuTEbAc8qA28AuqnOzyt7HBlCOUY2YJKqOaPSaDW6MJ3RErNNf4UIh0xWxgxvVuai6JDz9mu2S+D51qGilAKxTT/cBKd93b3HWIFMG/UqdKo56Md7jTQz5Ex5FYkxT0rpQHD+zhN6aQsjEfe7o6SbZKu6fkdLcv5NAi5MZRMT1/4q0bJonvmLLeNW14Lag6JhJGBA15rJru8UyEFc3gEMRxV7n+/v7s8uNToBQRicnkVGJRQ5jpbECokMrk3LtvVAvnSIE5ZeqLk8HGOeqYn7/NfT1JpyNxY7vVfuubSHIUX6zOwNI3vT52m0gk2UNclpcjLe/pGHY9k5wy03/lvTuQPz+rFFZ8lShbc4KhCHrHM4t9eFNsoRq4GojUIqpu9bUGl7dNzkOwgegcS66s65PdIjiU94M7/A3/QYN3qZdi3JBwvu/kWiMY=; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: aquantia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ebbf6024-f890-46c5-825b-08d63033334d X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 11:09:38.7431 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 83e2e134-991c-4ede-8ced-34d47e38e6b1 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0701MB1627 Subject: [dpdk-dev] [PATCH v6 15/22] net/atlantic: implement RSS and RETA manipulation API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Oct 2018 11:09:41 -0000 Add support for Receive Side Scaling feature. RSS hash and reta table configuration. Signed-off-by: Igor Russkikh Signed-off-by: Pavel Belous --- doc/guides/nics/atlantic.rst | 1 + doc/guides/nics/features/atlantic.ini | 3 + drivers/net/atlantic/atl_ethdev.c | 107 ++++++++++++++++++++++++++++++= ++++ drivers/net/atlantic/atl_ethdev.h | 14 +++++ drivers/net/atlantic/atl_rxtx.c | 5 ++ 5 files changed, 130 insertions(+) diff --git a/doc/guides/nics/atlantic.rst b/doc/guides/nics/atlantic.rst index b09c79babdf4..80591b13c185 100644 --- a/doc/guides/nics/atlantic.rst +++ b/doc/guides/nics/atlantic.rst @@ -16,6 +16,7 @@ Supported features - Promiscuous mode - Multicast mode - Port statistics +- RSS (Receive Side Scaling) - Checksum offload - Jumbo Frame upto 16K =20 diff --git a/doc/guides/nics/features/atlantic.ini b/doc/guides/nics/featur= es/atlantic.ini index 347ac80a1ceb..592af817931e 100644 --- a/doc/guides/nics/features/atlantic.ini +++ b/doc/guides/nics/features/atlantic.ini @@ -11,6 +11,9 @@ Queue start/stop =3D Y Jumbo frame =3D Y Promiscuous mode =3D Y Allmulticast mode =3D Y +RSS hash =3D Y +RSS key update =3D Y +RSS reta update =3D Y CRC offload =3D Y L3 checksum offload =3D Y L4 checksum offload =3D Y diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_e= thdev.c index 5223b57ebd83..2f365844752c 100644 --- a/drivers/net/atlantic/atl_ethdev.c +++ b/drivers/net/atlantic/atl_ethdev.c @@ -58,6 +58,19 @@ static int atl_dev_interrupt_action(struct rte_eth_dev *= dev, struct rte_intr_handle *handle); static void atl_dev_interrupt_handler(void *param); =20 +/* RSS */ +static int atl_reta_update(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); +static int atl_reta_query(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); +static int atl_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf); +static int atl_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf); + + static int eth_atl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev); static int eth_atl_pci_remove(struct rte_pci_device *pci_dev); @@ -208,6 +221,11 @@ static const struct eth_dev_ops atl_eth_dev_ops =3D { =20 .rxq_info_get =3D atl_rxq_info_get, .txq_info_get =3D atl_txq_info_get, + + .reta_update =3D atl_reta_update, + .reta_query =3D atl_reta_query, + .rss_hash_update =3D atl_rss_hash_update, + .rss_hash_conf_get =3D atl_rss_hash_conf_get, }; =20 static inline int32_t @@ -260,12 +278,18 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev) /* Hardware configuration - hardcode */ adapter->hw_cfg.is_lro =3D false; adapter->hw_cfg.wol =3D false; + adapter->hw_cfg.is_rss =3D false; + adapter->hw_cfg.num_rss_queues =3D HW_ATL_B0_RSS_MAX; + adapter->hw_cfg.link_speed_msk =3D AQ_NIC_RATE_10G | AQ_NIC_RATE_5G | AQ_NIC_RATE_2G5 | AQ_NIC_RATE_1G | AQ_NIC_RATE_100M; =20 + adapter->hw_cfg.aq_rss.indirection_table_size =3D + HW_ATL_B0_RSS_REDIRECTION_MAX; + hw->aq_nic_cfg =3D &adapter->hw_cfg; =20 /* disable interrupt */ @@ -747,6 +771,10 @@ atl_dev_info_get(struct rte_eth_dev *dev, struct rte_e= th_dev_info *dev_info) dev_info->rx_desc_lim =3D rx_desc_lim; dev_info->tx_desc_lim =3D tx_desc_lim; =20 + dev_info->hash_key_size =3D HW_ATL_B0_RSS_HASHKEY_BITS / 8; + dev_info->reta_size =3D HW_ATL_B0_RSS_REDIRECTION_MAX; + dev_info->flow_type_rss_offloads =3D ATL_RSS_OFFLOAD_ALL; + dev_info->speed_capa =3D ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; dev_info->speed_capa |=3D ETH_LINK_SPEED_100M; dev_info->speed_capa |=3D ETH_LINK_SPEED_2_5G; @@ -998,6 +1026,85 @@ atl_dev_interrupt_handler(void *param) atl_dev_interrupt_action(dev, dev->intr_handle); } =20 +static int +atl_reta_update(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + int i; + struct aq_hw_s *hw =3D ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct aq_hw_cfg_s *cf =3D ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private)= ; + + for (i =3D 0; i < reta_size && i < cf->aq_rss.indirection_table_size; i++= ) + cf->aq_rss.indirection_table[i] =3D min(reta_conf->reta[i], + dev->data->nb_rx_queues - 1); + + hw_atl_b0_hw_rss_set(hw, &cf->aq_rss); + return 0; +} + +static int +atl_reta_query(struct rte_eth_dev *dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + int i; + struct aq_hw_cfg_s *cf =3D ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private)= ; + + for (i =3D 0; i < reta_size && i < cf->aq_rss.indirection_table_size; i++= ) + reta_conf->reta[i] =3D cf->aq_rss.indirection_table[i]; + reta_conf->mask =3D ~0U; + return 0; +} + +static int +atl_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct aq_hw_s *hw =3D ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct aq_hw_cfg_s *cfg =3D + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + static u8 def_rss_key[40] =3D { + 0x1e, 0xad, 0x71, 0x87, 0x65, 0xfc, 0x26, 0x7d, + 0x0d, 0x45, 0x67, 0x74, 0xcd, 0x06, 0x1a, 0x18, + 0xb6, 0xc1, 0xf0, 0xc7, 0xbb, 0x18, 0xbe, 0xf8, + 0x19, 0x13, 0x4b, 0xa9, 0xd0, 0x3e, 0xfe, 0x70, + 0x25, 0x03, 0xab, 0x50, 0x6a, 0x8b, 0x82, 0x0c + }; + + cfg->is_rss =3D !!rss_conf->rss_hf; + if (rss_conf->rss_key) { + memcpy(cfg->aq_rss.hash_secret_key, rss_conf->rss_key, + rss_conf->rss_key_len); + cfg->aq_rss.hash_secret_key_size =3D rss_conf->rss_key_len; + } else { + memcpy(cfg->aq_rss.hash_secret_key, def_rss_key, + sizeof(def_rss_key)); + cfg->aq_rss.hash_secret_key_size =3D sizeof(def_rss_key); + } + + hw_atl_b0_hw_rss_set(hw, &cfg->aq_rss); + hw_atl_b0_hw_rss_hash_set(hw, &cfg->aq_rss); + return 0; +} + +static int +atl_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct aq_hw_cfg_s *cfg =3D + ATL_DEV_PRIVATE_TO_CFG(dev->data->dev_private); + + rss_conf->rss_hf =3D cfg->is_rss ? ATL_RSS_OFFLOAD_ALL : 0; + if (rss_conf->rss_key) { + rss_conf->rss_key_len =3D cfg->aq_rss.hash_secret_key_size; + memcpy(rss_conf->rss_key, cfg->aq_rss.hash_secret_key, + rss_conf->rss_key_len); + } + + return 0; +} + RTE_PMD_REGISTER_PCI(net_atlantic, rte_atl_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_atlantic, pci_id_atl_map); RTE_PMD_REGISTER_KMOD_DEP(net_atlantic, "* igb_uio | uio_pci_generic"); diff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_e= thdev.h index c315e0436dca..1e29999b539c 100644 --- a/drivers/net/atlantic/atl_ethdev.h +++ b/drivers/net/atlantic/atl_ethdev.h @@ -10,6 +10,17 @@ #include "atl_types.h" #include "hw_atl/hw_atl_utils.h" =20 +#define ATL_RSS_OFFLOAD_ALL ( \ + ETH_RSS_IPV4 | \ + ETH_RSS_NONFRAG_IPV4_TCP | \ + ETH_RSS_NONFRAG_IPV4_UDP | \ + ETH_RSS_IPV6 | \ + ETH_RSS_NONFRAG_IPV6_TCP | \ + ETH_RSS_NONFRAG_IPV6_UDP | \ + ETH_RSS_IPV6_EX | \ + ETH_RSS_IPV6_TCP_EX | \ + ETH_RSS_IPV6_UDP_EX) + #define ATL_DEV_PRIVATE_TO_HW(adapter) \ (&((struct atl_adapter *)adapter)->hw) =20 @@ -19,6 +30,9 @@ #define ATL_DEV_PRIVATE_TO_INTR(adapter) \ (&((struct atl_adapter *)adapter)->intr) =20 +#define ATL_DEV_PRIVATE_TO_CFG(adapter) \ + (&((struct atl_adapter *)adapter)->hw_cfg) + #define ATL_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) #define ATL_FLAG_NEED_LINK_CONFIG (uint32_t)(4 << 0) =20 diff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxt= x.c index fbd50a766098..01267214088b 100644 --- a/drivers/net/atlantic/atl_rxtx.c +++ b/drivers/net/atlantic/atl_rxtx.c @@ -336,6 +336,7 @@ int atl_rx_init(struct rte_eth_dev *eth_dev) { struct aq_hw_s *hw =3D ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + struct aq_rss_parameters *rss_params =3D &hw->aq_nic_cfg->aq_rss; struct atl_rx_queue *rxq; uint64_t base_addr =3D 0; int i =3D 0; @@ -379,6 +380,10 @@ atl_rx_init(struct rte_eth_dev *eth_dev) } } =20 + for (i =3D rss_params->indirection_table_size; i--;) + rss_params->indirection_table[i] =3D i & + (eth_dev->data->nb_rx_queues - 1); + hw_atl_b0_hw_rss_set(hw, rss_params); return err; } =20 --=20 2.7.4