From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id F3CCD3978 for ; Mon, 19 Sep 2016 15:58:16 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP; 19 Sep 2016 06:58:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,362,1470726000"; d="scan'208";a="1033120032" Received: from irsmsx106.ger.corp.intel.com ([163.33.3.31]) by orsmga001.jf.intel.com with ESMTP; 19 Sep 2016 06:58:15 -0700 Received: from irsmsx155.ger.corp.intel.com (163.33.192.3) by IRSMSX106.ger.corp.intel.com (163.33.3.31) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 19 Sep 2016 14:58:14 +0100 Received: from irsmsx102.ger.corp.intel.com ([169.254.2.248]) by irsmsx155.ger.corp.intel.com ([169.254.14.133]) with mapi id 14.03.0248.002; Mon, 19 Sep 2016 14:58:14 +0100 From: "Kulasek, TomaszX" To: "Ananyev, Konstantin" , "dev@dpdk.org" CC: "jerin.jacob@caviumnetworks.com" Thread-Topic: [dpdk-dev] [PATCH v2 5/6] ixgbe: add Tx preparation Thread-Index: AQHSDQU0NP52Ldd9HkGh5yq8thBaCKCAvz0AgAAZG0A= Date: Mon, 19 Sep 2016 13:58:12 +0000 Message-ID: <3042915272161B4EB253DA4D77EB373A14F1923D@IRSMSX102.ger.corp.intel.com> References: <1472228578-6980-1-git-send-email-tomaszx.kulasek@intel.com> <1473691487-10032-1-git-send-email-tomaszx.kulasek@intel.com> <1473691487-10032-6-git-send-email-tomaszx.kulasek@intel.com> <2601191342CEEE43887BDE71AB9772583F0B5811@irsmsx105.ger.corp.intel.com> In-Reply-To: <2601191342CEEE43887BDE71AB9772583F0B5811@irsmsx105.ger.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 5/6] ixgbe: add Tx preparation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Sep 2016 13:58:17 -0000 Hi Konstantin, > -----Original Message----- > From: Ananyev, Konstantin > Sent: Monday, September 19, 2016 14:55 > To: Kulasek, TomaszX ; dev@dpdk.org > Cc: jerin.jacob@caviumnetworks.com > Subject: RE: [dpdk-dev] [PATCH v2 5/6] ixgbe: add Tx preparation >=20 >=20 > Hi Tomasz, >=20 [...] > > +uint16_t > > +ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t > > +nb_pkts) { > > + int i, ret; > > + struct rte_mbuf *m; > > + struct ixgbe_tx_queue *txq =3D (struct ixgbe_tx_queue *)tx_queue; > > + > > + for (i =3D 0; i < nb_pkts; i++) { > > + m =3D tx_pkts[i]; > > + > > + /** > > + * Check if packet meets requirements for number of segments > > + * > > + * NOTE: for ixgbe it's always (40 - WTHRESH) for both TSO and > non-TSO > > + */ > > + > > + if (m->nb_segs > IXGBE_TX_MAX_SEG - txq->wthresh) { > > + rte_errno =3D -EINVAL; > > + return i; > > + } > > + > > + if ((m->ol_flags & PKT_TX_OFFLOAD_MASK) !=3D > > + (m->ol_flags & IXGBE_TX_OFFLOAD_MASK)) { >=20 >=20 > As a nit, it probably makes sense to: > #define IXGBE_TX_OFFLOAD_NOTSUP_MASK (PKT_TX_OFFLOAD_MASK ^ > IXGBE_TX_OFFLOAD_MASK) >=20 > and then here: > (m->ol_flags & IXGBE_TX_OFFLOAD_NOTSUP_MASK) >=20 > Might help to save few cycles. >=20 Ok. >=20 > > + rte_errno =3D -EINVAL; > > + return i; > > + } > > + > > +#ifdef RTE_LIBRTE_ETHDEV_DEBUG > > + ret =3D rte_validate_tx_offload(m); > > + if (ret !=3D 0) { > > + rte_errno =3D ret; > > + return i; > > + } > > +#endif > > + ret =3D rte_phdr_cksum_fix(m); >=20 > We probable need to update rte_phdr_cksum_fix() to take into account > tx_offload outer lengths in case PKT_TX_OUTER_IP_CKSUM is defined. > As both ixgbe and i40e can do it these days. > Sorry for not spotting that earlier. >=20 Ok. >=20 > > + if (ret !=3D 0) { > > + rte_errno =3D ret; > > + return i; > > + } > > + } > > + > > + return i; > > +} > > + [...] > > > > ********************************************************************** > > / @@ -2290,6 +2369,7 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, > > struct ixgbe_tx_queue *txq) > > } else > > #endif > > dev->tx_pkt_burst =3D ixgbe_xmit_pkts_simple; > > + dev->tx_pkt_prep =3D ixgbe_prep_pkts_simple; >=20 > Shouldn't we setup ixgbe_prep_pkts_simple when vTX is selected too? >=20 It is, but source code is formatted like below: #ifdef RTE_IXGBE_INC_VECTOR if (txq->tx_rs_thresh <=3D RTE_IXGBE_TX_MAX_FREE_BUF_SZ && (rte_eal_process_type() !=3D RTE_PROC_PRIMARY || ixgbe_txq_vec_setup(txq) =3D=3D 0)) { PMD_INIT_LOG(DEBUG, "Vector tx enabled."); dev->tx_pkt_burst =3D ixgbe_xmit_pkts_vec; } else #endif dev->tx_pkt_burst =3D ixgbe_xmit_pkts_simple; dev->tx_pkt_prep =3D ixgbe_prep_pkts_simple; > > } else { > > PMD_INIT_LOG(DEBUG, "Using full-featured tx code path"); > > PMD_INIT_LOG(DEBUG, > > @@ -2301,6 +2381,7 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, > struct ixgbe_tx_queue *txq) > > (unsigned long)txq->tx_rs_thresh, > > (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST); > > dev->tx_pkt_burst =3D ixgbe_xmit_pkts; > > + dev->tx_pkt_prep =3D ixgbe_prep_pkts; > > } > > } > > > > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.h > > b/drivers/net/ixgbe/ixgbe_rxtx.h index 2608b36..7bbd9b8 100644 > > --- a/drivers/net/ixgbe/ixgbe_rxtx.h > > +++ b/drivers/net/ixgbe/ixgbe_rxtx.h > > @@ -80,6 +80,8 @@ > > #define RTE_IXGBE_WAIT_100_US 100 > > #define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2 > > > > +#define IXGBE_TX_MAX_SEG 40 > > + > > #define IXGBE_PACKET_TYPE_MASK_82599 0X7F > > #define IXGBE_PACKET_TYPE_MASK_X550 0X10FF > > #define IXGBE_PACKET_TYPE_MASK_TUNNEL 0XFF > > -- > > 1.7.9.5 Tomasz.