From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from na01-by2-obe.outbound.protection.outlook.com (mail-by2on0135.outbound.protection.outlook.com [207.46.100.135]) by dpdk.org (Postfix) with ESMTP id B101811F5 for ; Mon, 29 Sep 2014 08:14:44 +0200 (CEST) Received: from BY2PR0301MB0695.namprd03.prod.outlook.com (25.160.63.15) by BY2PR0301MB0680.namprd03.prod.outlook.com (25.160.63.147) with Microsoft SMTP Server (TLS) id 15.0.1039.15; Mon, 29 Sep 2014 06:21:17 +0000 Received: from BY2PR0301MB0693.namprd03.prod.outlook.com (25.160.63.148) by BY2PR0301MB0695.namprd03.prod.outlook.com (25.160.63.15) with Microsoft SMTP Server (TLS) id 15.0.1034.13; Mon, 29 Sep 2014 06:21:15 +0000 Received: from BY2PR0301MB0693.namprd03.prod.outlook.com ([25.160.63.148]) by BY2PR0301MB0693.namprd03.prod.outlook.com ([25.160.63.148]) with mapi id 15.00.1039.011; Mon, 29 Sep 2014 06:21:16 +0000 From: "Hemant@freescale.com" To: Chao Zhu , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 10/12] Add cache size define for IBM Power Architecture Thread-Index: AQHP2W2AVqn56GQRA0iGrlzXOjJ/c5wXp5/g Date: Mon, 29 Sep 2014 06:21:15 +0000 Message-ID: <307e2643dd894afc9e53e0c3de74c32a@BY2PR0301MB0693.namprd03.prod.outlook.com> References: <1411724186-8036-1-git-send-email-bjzhuc@cn.ibm.com> <1411724186-8036-11-git-send-email-bjzhuc@cn.ibm.com> In-Reply-To: <1411724186-8036-11-git-send-email-bjzhuc@cn.ibm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [192.88.169.1] x-microsoft-antispam: BCL:0;PCL:0;RULEID:;SRVR:BY2PR0301MB0695;UriScan:; x-forefront-prvs: 034902F5BC x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(6009001)(199003)(51704005)(189002)(86362001)(105586002)(99286002)(92566001)(95666004)(106116001)(99396003)(106356001)(76482002)(76576001)(20776003)(120916001)(10300001)(77096002)(66066001)(64706001)(85852003)(83072002)(83322001)(85306004)(107046002)(76176999)(107886001)(50986999)(2501002)(90102001)(19580395003)(101416001)(80022003)(79102003)(31966008)(77982003)(81542003)(74502003)(74662003)(81342003)(46102003)(54356999)(74316001)(21056001)(108616004)(4396001)(33646002)(2656002)(87936001)(97736003)(24736002)(80792004); DIR:OUT; SFP:1102; SCL:1; SRVR:BY2PR0301MB0695; H:BY2PR0301MB0693.namprd03.prod.outlook.com; FPR:; MLV:sfv; PTR:InfoNoRecords; A:1; MX:1; LANG:en; Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY2PR0301MB0680; X-OriginatorOrg: freescale.com Subject: Re: [dpdk-dev] [PATCH 10/12] Add cache size define for IBM Power Architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 29 Sep 2014 06:14:45 -0000 > --- a/mk/arch/powerpc/rte.vars.mk > +++ b/mk/arch/powerpc/rte.vars.mk > @@ -32,7 +32,7 @@ > ARCH ?=3D powerpc > CROSS ?=3D >=20 > -CPU_CFLAGS ?=3D -m64 > +CPU_CFLAGS ?=3D -m64 -DCACHE_LINE_SIZE=3D128 [hemant] Instead of hardcoding the CACHE_LINE_SIZE, can you drive the CA= CHE_LINE_SIZE from config file. Other powerpc processor have it as 64. > CPU_LDFLAGS ?=3D > CPU_ASFLAGS ?=3D -felf64 >=20 > -- > 1.7.1