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From: "Hemant@freescale.com" <Hemant@freescale.com>
To: Chao Zhu <bjzhuc@cn.ibm.com>, "dev@dpdk.org" <dev@dpdk.org>
Thread-Topic: [dpdk-dev] [PATCH 10/12] Add cache size define for IBM Power
 Architecture
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Date: Mon, 29 Sep 2014 06:21:15 +0000
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Subject: Re: [dpdk-dev] [PATCH 10/12] Add cache size define for IBM
	Power	Architecture
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> --- a/mk/arch/powerpc/rte.vars.mk
> +++ b/mk/arch/powerpc/rte.vars.mk
> @@ -32,7 +32,7 @@
>  ARCH  ?=3D powerpc
>  CROSS ?=3D
>=20
> -CPU_CFLAGS  ?=3D -m64
> +CPU_CFLAGS  ?=3D -m64 -DCACHE_LINE_SIZE=3D128

 [hemant]  Instead of hardcoding the CACHE_LINE_SIZE,  can you drive the CA=
CHE_LINE_SIZE from config file.  Other powerpc processor have it as 64.


>  CPU_LDFLAGS ?=3D
>  CPU_ASFLAGS ?=3D -felf64
>=20
> --
> 1.7.1